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DE69840237D1 - Verbesserte ätztechnik mit einer photomaske - Google Patents

Verbesserte ätztechnik mit einer photomaske

Info

Publication number
DE69840237D1
DE69840237D1 DE69840237T DE69840237T DE69840237D1 DE 69840237 D1 DE69840237 D1 DE 69840237D1 DE 69840237 T DE69840237 T DE 69840237T DE 69840237 T DE69840237 T DE 69840237T DE 69840237 D1 DE69840237 D1 DE 69840237D1
Authority
DE
Germany
Prior art keywords
photomask
heating technology
improved heating
improved
technology
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69840237T
Other languages
English (en)
Inventor
Barbara Haselden
John Lee
Chau Arima
Eddie Chiu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lam Research Corp
Original Assignee
Lam Research Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Research Corp filed Critical Lam Research Corp
Application granted granted Critical
Publication of DE69840237D1 publication Critical patent/DE69840237D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/80—Etching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
DE69840237T 1997-12-23 1998-12-11 Verbesserte ätztechnik mit einer photomaske Expired - Lifetime DE69840237D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/997,346 US6121154A (en) 1997-12-23 1997-12-23 Techniques for etching with a photoresist mask
PCT/US1998/026502 WO1999033095A1 (en) 1997-12-23 1998-12-11 Improved techniques for etching with a photoresist mask

Publications (1)

Publication Number Publication Date
DE69840237D1 true DE69840237D1 (de) 2009-01-02

Family

ID=25543912

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69840237T Expired - Lifetime DE69840237D1 (de) 1997-12-23 1998-12-11 Verbesserte ätztechnik mit einer photomaske

Country Status (7)

Country Link
US (1) US6121154A (de)
EP (1) EP1042791B1 (de)
JP (1) JP4351806B2 (de)
KR (1) KR100595090B1 (de)
DE (1) DE69840237D1 (de)
TW (1) TW464976B (de)
WO (1) WO1999033095A1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1301840B1 (it) * 1998-06-30 2000-07-07 Stmicroelettronica S R L Metodo per incrementare la seletttvita' tra un film di materialefotosensibile ed uno strato da sottoporre ed incisione in processi
US6110779A (en) * 1998-07-17 2000-08-29 Advanced Micro Devices, Inc. Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride
US6291357B1 (en) 1999-10-06 2001-09-18 Applied Materials, Inc. Method and apparatus for etching a substrate with reduced microloading
US6461969B1 (en) * 1999-11-22 2002-10-08 Chartered Semiconductor Manufacturing Ltd. Multiple-step plasma etching process for silicon nitride
US6660646B1 (en) * 2000-09-21 2003-12-09 Northrop Grumman Corporation Method for plasma hardening photoresist in etching of semiconductor and superconductor films
JP4128365B2 (ja) 2002-02-07 2008-07-30 東京エレクトロン株式会社 エッチング方法及びエッチング装置
US6923920B2 (en) * 2002-08-14 2005-08-02 Lam Research Corporation Method and compositions for hardening photoresist in etching processes
US6797610B1 (en) 2002-12-11 2004-09-28 International Business Machines Corporation Sublithographic patterning using microtrenching
US7232766B2 (en) * 2003-03-14 2007-06-19 Lam Research Corporation System and method for surface reduction, passivation, corrosion prevention and activation of copper surface
US20040224524A1 (en) * 2003-05-09 2004-11-11 Applied Materials, Inc. Maintaining the dimensions of features being etched on a lithographic mask
US7682516B2 (en) * 2005-10-05 2010-03-23 Lam Research Corporation Vertical profile fixing
US7341953B2 (en) * 2006-04-17 2008-03-11 Lam Research Corporation Mask profile control for controlling feature profile
US7785753B2 (en) * 2006-05-17 2010-08-31 Lam Research Corporation Method and apparatus for providing mask in semiconductor processing
CN104465386A (zh) * 2013-09-24 2015-03-25 中芯国际集成电路制造(北京)有限公司 半导体结构的形成方法
CN107968046B (zh) * 2016-10-20 2020-09-04 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US11675278B2 (en) * 2021-01-14 2023-06-13 Texas Instruments Incorporated Exhaust gas monitor for photoresist adhesion control

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4613400A (en) * 1985-05-20 1986-09-23 Applied Materials, Inc. In-situ photoresist capping process for plasma etching
US4713141A (en) * 1986-09-22 1987-12-15 Intel Corporation Anisotropic plasma etching of tungsten
US4844773A (en) * 1987-07-16 1989-07-04 Texas Instruments Incorporated Process for etching silicon nitride film
JP2824584B2 (ja) * 1989-05-25 1998-11-11 日本電信電話株式会社 ドライエツチング方法
JP3729869B2 (ja) * 1990-09-28 2005-12-21 セイコーエプソン株式会社 半導体装置の製造方法
JP2758771B2 (ja) * 1992-03-11 1998-05-28 シャープ株式会社 素子分離領域の形成方法
US5275692A (en) * 1992-06-22 1994-01-04 Keystone Applied Research Method for fabricating integrated circuits
US5332653A (en) * 1992-07-01 1994-07-26 Motorola, Inc. Process for forming a conductive region without photoresist-related reflective notching damage
JPH08321484A (ja) * 1995-05-24 1996-12-03 Nec Corp 半導体装置の製造方法
US5726102A (en) * 1996-06-10 1998-03-10 Vanguard International Semiconductor Corporation Method for controlling etch bias in plasma etch patterning of integrated circuit layers

Also Published As

Publication number Publication date
TW464976B (en) 2001-11-21
KR20010033406A (ko) 2001-04-25
JP4351806B2 (ja) 2009-10-28
WO1999033095A1 (en) 1999-07-01
US6121154A (en) 2000-09-19
EP1042791B1 (de) 2008-11-19
EP1042791A1 (de) 2000-10-11
KR100595090B1 (ko) 2006-07-03
JP2001527287A (ja) 2001-12-25

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