DE69433599T2 - Flash EPROM integrated circuit architecture - Google Patents

Description

The This patent relates to a co-pending application titled A FLASH EPROM TRANSISTOR ARRAY AND METHOD FOR MANUFACTURING THE SA-ME, the same The day the present application was filed by the inventors Shone et al., And owned by the same Applicant, as the present application now and at the time of the invention.

BACKGROUND OF THE INVENTION

Field of the invention

The The present invention relates to flash EPROM memory technology and more particularly to an improved flash EPROM memory architecture and data cell construction.

Description of the related State of the art

Flash EPROM are a growing class of non-volatile memory integrated circuits. These flash EPROMs have the capability of electrical deletion, Programming and reading a memory cell in the chip. The memory cell in a flash EPROM is formed using transistors with so-called floating gate, in which the data is stored in a cell by the floating gate loaded or unloaded. The floating gate consists of a leiffähigen Material typically made of polysilicon, which is derived from the Channel of the transistor through a thin oxide layer or another Insulating material is separated and which opposite the control gate or the word line of the transistor through a second layer of insulating Material is isolated.

dates are stored in the memory cell by the potential-free Gate is charged or discharged. The floating gate is going through Loaded a Fowler-Nordheim tunneling mechanism, adding a big positive Voltage between the gate and the source or the drain is provided. This causes electrons through the thin insulator be injected into the floating gate. alternative An avalanche injection mechanism can also be used by Potentials are applied to high energy electrons in the Channel of the cell to be induced by the insulator in the floating gate to be injected. When the floating gate is charged is the threshold voltage, which causes the memory cell conducts, over the tension increases, the while a read operation is applied to the word line. Accordingly, directs a loaded cell does not when it addresses during a read becomes. The non-conductive state of the cell can be interpreted as a binary 1 or 0, depending on the polarity the polling circuit.

The potential-free gate is discharged to the opposite memory state provide. This feature is typically done by a F-N tunneling mechanism between the floating gate and the Source or the drain of the transistor or between the potential-free Gate and the substrate executed. For example, the floating gate can be discharged through the source, by having a big one providing positive voltage from the source to the gate, while the drain on a floating potential or potential-free (floating) is held.

The high voltages that are used to the floating gate to load and unload, bring considerable restrictions in the design of flash memory devices with, especially if the cell dimensions and process specifications in their dimensions be reduced. Details of the structure and function from flash EPROMs according to the prior art, it is found in review the following US patents, who for the purpose of teaching over the background of the corresponding technology here by reference to be included:

• Bergemont et al., U.S. Patent No. 5,012,446, issued to April 30, 1991,
• Mukherjee et al., U.S. Patent No. 4,698,787, issued 6 October 1987 and
• Holler et al., U.S. Patent No. 4,780,423, issued October 25 1988th

Further advanced technology, which integrated flash EPROM circuits is concerned in the European Patent Application No. 90 104 002.2 to Belleza on September 12, 1990, by Woo et al., "A Novel Memory Cell Using Flash Array Contactless EPROM (FACE) Technology ", IEDM 1990, published by IEEE, pp. 91-94. Further, Woo et al., "A Poly-buffered "FACE" Technology for High Density Memories ", 1992 SYMPOSIUM ON VLSI TECHNOLOGY, pp. 73-74. A "contactless" EPROM array architecture will be described in Kazerounian et al., "Alternate Metal Virtual Ground EPROM Array Implemented in A 0.8 μM Process for Very High Density Applications, IEDM, released by IEEE 1991, p. 11.5.1-11.5.4.

As described by the Bergemont patent and the publications by Belleza, Woo et al. and Kazerounian et al. There is an increasing interest in a non-volatile memory model with contactless array. So-called contactless arrays comprise an array of memory cells buried by diffusion and the buried diffusion is only periodically connected by contacts to a metallic bit line. Previous Flash EPROM models, such as the Mukherjee et al. System, required a "half" metal contact for each memory cell. Since metal contacts consume a significant amount of area on an integrated circuit, they are a major obstacle to generating high density memory technology. Furthermore, as the device becomes smaller and smaller, area reduction by the metal is limited over the contact spacing of adjacent drain and source bit lines which are used to access the memory cells in the array.

It is therefore desirable a flash EPROM cell, architecture, and method of manufacture to provide it, which is non-volatile High density memory circuit and which some of the Overcome problems, those with high programming and erase voltages connected are.

The US-A-4,460,982, which forms the basis for the preamble of claim 1 describes an EEPROM which provides automatic program verification provides. The contents of the cells are checked to verify that the deletion is complete is. If this is not the case, the deletion will continue until the Cells deleted are. When data is written to cells, writing becomes the data is continued in the cells until the programming is verified has been. The verification is performed with potentials that others are considered the normal reference potential to ensure that the Cells with either binary Zeros or with binary Ones are programmed securely.

SUMMARY OF THE INVENTION

Under In a first aspect, the present invention provides a method for programming a data pattern in a set of flash memory cells ready, with: Loading the data pattern into a buffer, programming of the set of flash memory cells by connecting the Buffers on bitlines for the set of flash memory cells and application of programming potentials at least at the control gates of the set of flash memory cells, after the step of programming comparing the output values from the set of flash memory cells with the data in the buffer verify the programming, and for cells in the set of flash memory cells, which output values delete one that matches the data in the buffer corresponding bits in the buffer, and if any bits of the data pattern in the buffer undeleted stay, re-trying the steps of programming and Comparing.

According to one embodiment The present invention provides a method of programming a new, contactless flash EPROM cell provided which preferably on a particular drain-source-drain configuration in which a single source diffusion of two columns is shared by transistors. Such an approach leads to a dense, segmentable flash EPROM chip. Furthermore, a new Memory circuit architecture used for the flash EPROM cells of the present invention is provided.

According to one embodiment The present invention provides a flash EPROM transistor array. One elongated first drain diffusion region, an elongated source diffusion region and a longish one second drain diffusion region are in a semiconductor substrate formed along substantially parallel lines. It leaves field oxide areas on opposite Sides of the first and second drain diffusion regions grow. potential free Gates and control gate word lines become perpendicular to the drain-source-drain structure designed to provide two columns of memory cells, which have a shared source area. The shared Source area is connected to a virtual ground terminal. The drain diffusion regions are provided by selection transistors connected to global bitlines. The cell structure according to a embodiment The invention uses a metallic global bitline which substantially parallel to the drain, source and drain diffusion regions for two Columns of cells, and a virtual ground supply, which with a plurality of columns of transistors with a virtual ground connection over one horizontal conductor is connected, such. a buried diffusion line. Accordingly, for the two columns of flash EPROM cells in each drain-source-drain structure only a repeating distance of the metal contacts needed.

Thus, in accordance with one embodiment of the present invention, an integrated flash EPROM circuit module is provided on a semiconductor substrate. The module has a memory array having at least M rows and 2N columns of flash EPROM cells. M word lines respectively connected to the flash EPROM cells in one of the M rows of the flash EPROM cells and N global bit lines are included therein. A data input and output circuit is connected to the N global bit lines, which ensures the reading and writing of data in the memory array. A selector circuit connected to the 2N columns of flash EPROM cells and to the N global bitlines provides one optionally, provide connection of two columns of the 2N columns with each of the N global bitlines such that access to the 2N columns of flash EPROM cells is provided by the data input and output circuitry via N global bitlines. Furthermore, the structure can be extended to provide the sharing of a metallic bitline for more than two columns of cells.

The Array according to another embodiment has a plurality of segments of drain-source-drain structures on, as described above. The selection circuit points in this embodiment a segment selection circuit connected to two local bitlines connected by the drain diffusion regions in the segment provided. The segment selection circuit sees an optional one Connecting the first and second columns of cells with a given Segment for one of the bit lines. Accordingly, the selection circuit includes where the drain diffusion regions provide local bitlines, a first Transistor, whose first terminal in the first drain diffusion region of the structure and its second terminal with a contact one of N global bit lines is connected. The second transistor has a first connection, which with the second drain diffusion region of the structure and a second connected to the contact terminal is connected. The first and second transistors are represented by left and right select lines, which run parallel to the word lines, independently controlled.

The Array becomes even more compact by reducing the number of required word line drivers is reduced. According to this embodiment each word line driver controls a plurality of word lines, such as. eight, in parallel. Each of the word lines, by a given word line driver are located in another segment of each column of segments containing the Form an array. Thus, the selected word line is replaced by the Segment selection circuit as well as decoded by the Wortleitungsdecodierschaltung. This makes the layout of the array much more compact, adding eight word lines only one word line driver is required.

According to one another embodiment According to the present invention, the semiconductor substrate has a first one Conductivity type, a first well in the substrate of a second conductivity type and a second well of the first conductivity type in the first one Well. The flash EPROM cells are formed in the second well to prevent the application of a negative Potentials at least either at the source and / or at the drain while an operation of charging the floating gate in the cells enable. This reduces the size of the high positive voltage considerably, which must be applied to the gate to induce F-N tunneling for cells to be charged. The array of one embodiment also uses a negative potential at the gate to be discharged Cells. This reduces considerably the size of the potential, which must be applied to the drain to perform an F-N tunneling for discharge to induce the cell. The voltages used with lower Values facilitate the specifications for the components of the integrated Circuits handling the programming and erase voltages, what the establishment of economic and easier to make. At the same time, the durability the memory improves by during programmer operation a generation hotter holes is reduced. According to one another embodiment According to the present invention, the array is configured such that the "erased" state is a charged state potential-free gate so that the erased cell does not conduct when it is addressed, and the "programmed" state results from unloading the cell, so that the programmed cell conductive is when it is addressed. This allows for a deletion process can be done without programming.

In yet another embodiment of the present invention, the array includes redundant rows of flash EPROM cells. The redundant rows are used to replace a row in the main array that is addressed by a single word line or a set of word lines connected to a single driver. Because of the discharged state corresponding to a programmed state and the use of the negative potentials for programming and erasing, as set forth above, row redundancy is enabled. Prior art flash EPROM cells could not use row redundancy because of the interference caused by the failed row in the main array. In particular, since the failed row could not be isolated from the program and / or erase potentials in the main array, the cells in the failed row would still go into an over-erased state, contribute to leakage on the array, and eventually cause column failure , Thus, an integrated flash EPROM circuit module according to an embodiment of the present invention may be fabricated using a two-well process in which the semiconductor substrate has the first conductivity type in the semiconductor substrate, a first well of a second conductivity type in the substrate, and a second well of the first conductivity type in the first well. An array of flash EPROM cells will be in the second Well, where the array contains 2N columns of flash EPROM cells and M rows. The 2N columns of flash EPROM cells have N pairs of columns of flash EPROM cells, each pair of columns containing a plurality of segments. Each segment in the plurality has a first drain diffusion region elongated in a first direction in the second well, a source diffusion region elongated in the first direction in the second well and spaced from the first drain diffusion region, and a first drain diffusion region second drain diffusion region formed longitudinally in the first direction in the second well and spaced from the source diffusion region. This provides a drain-source-drain structure that provides two columns of flash EPROM cells within a given segment.

A first insulating layer is over the substrate, over the first and second channel regions formed between the drain-source-drain structures are, and over the source and Draindiffusionsbereichen are arranged. Electrodes for the potential-free Gates are over the first insulating layer for the two columns of cells are placed in the segment. The second Insulating layer is over the floating gate electrodes arranged. This leads to, that every Segment a first set of Flash EPROM cells in a first from a pair of columns and a second set of flash EPROM cells in a second of the pair of columns.

M Word lines, each with the flash EPROM cells in one The M rows of flash EPROM cells are connected. Members of a subset of the M wordlines are each with a flash EPROM cell in the first set in a given segment and a flash EPROM cell in the second set in a given one Segment connected. Thus, each word line cuts two cells in each pair of columns within a given segment.

The Array includes N global bitlines. A data input and output circuit is connected to the N global bit lines to read and Writing data (using a programming and / or Erase sequence) in the 2N columns of flash EPROM cells.

A Selection circuit is with the first and second drain diffusion regions connected in each of the plurality of segments, causing a connection the 2N columns of flash EPROM cells with provides the N global bitlines. The selection circuit provides an optional connection of two columns of the 2N columns with each of the N global bitlines so that access to the 2N columns of Flash EPROM cells through the data input and output circuit via the N global bitlines.

The Programming and clearing circuit lays while an operation for charging the floating gate of selected flash EPROM cells negative potential on the global bitlines, and sets during one A process for discharging the floating gate of selected flash EPROM cells a negative potential on the word lines, so that the magnitude of positive voltages, the other connections is needed is reduced.

Therefore a unique array architecture is provided with a virtual mass configuration to achieve a high packing density. The basic unit of the memory array comprises segments of two columns of cells in a drain-source-drain configuration. The resulting array structure provides lower programming and erase noise problems for the neighboring, not selected Bit lines. It also reduces the complexity of the design of the Y-decoder in comparison to an array structure acting as a source-drain-source-drain array is designed.

In the array layout, two cells share a metal spacing, which the design standards for the metallic Repeat distance loosens even further. The decoding for the two Columns of cells connected to a given metal line, is ensured by left and right selection transistors, which are connected to each drain-source-drain segment.

The special left and right selection transistors are each with connected to a set of rows of up to 64 word lines to improve the reading speed and programing problems mitigate.

The array is designed to provide a conductive state to programmed cells using negative wordline voltages during page programming operations. In addition, during an erase operation designed to provide a non-conductive state for the cell, negative drain, source, and substrate voltages are applied. This, too, reduces the noise problems and the magnitude of the positive voltage that must be applied during the operations. Finally, the array provides redundant row and redundant column replacement configurations that were not available in prior art models. The aspects and advantages of the present invention can be seen by looking at the figures, the exact Description and the claims recognize that follow.

BRIEF DESCRIPTION OF THE FIGURES

1 FIG. 10 is a schematic diagram of an integrated flash EPROM circuit module according to the present invention. FIG.

2 FIG. 10 is a schematic diagram of a flash EPROM array according to an embodiment of the present invention in a virtual ground drain-source-drain configuration. FIG.

3 Figure 3 is a schematic diagram of an alternative embodiment of the present invention having two columns of flash EPROM cells sharing a single metallic bitline.

4 FIG. 12 is a schematic block diagram of a segmentable flash EPROM array having redundant rows for correcting erroneous rows in the main array. FIG.

4A Fig. 10 is a flowchart of a page program operation according to the present invention.

4B Fig. 10 is a simplified diagram showing the program verification circuit according to the present invention.

5A - 5H illustrate the steps in fabricating a first type of flash EPROM cell according to the present invention with an extended floating gate for improved coupling ratio.

6A - 6G illustrate the final six steps in a sequence that begins as in the 5A - 5D to implement an alternative embodiment of the flash EPROM cells according to the present invention.

7 provides a perspective view of the layout of a flash EPROM segment according to the present invention.

8th - 14 are mask layouts for implementing the flash EPROM segment after 7 , in which:

8th shows the layout of a first diffusion and a field oxide isolation in the substrate,

9 shows the range of a p + -type cell implant for increasing the threshold voltage in the tents of the array,

10 shows the layout of a first polysilicon layer,

11 shows the layout of a second polysilicon layer,

12 shows the layout of a third polysilicon layer,

13 showing the positioning of metal contacts,

14 shows the layout of the overlying metal lines.

PRECISE DESCRIPTION

A detailed description of preferred embodiments of the present invention will be provided with reference to the figures of which 1 provides an overview of the layout of an integrated flash EPROM circuit module according to the present invention. Accordingly, the integrated circuit module comprises 1 a flash EPROM memory array 100 which is provided with a plurality of redundant memory cells 101 connected to replace defective cells in the main array, as is known in the art. A plurality of reference cells 102 is using query amplifiers 107 used for a differential query of the state of the cells in the memory array.

With the storage array 100 are word line and block select decoders 104 connected for horizontal decoding in the memory array. Furthermore, with the memory array 100 the column decoder and the virtual ground circuit 105 connected for vertical decoding in the array.

With the column decoder and the virtual ground circuit 105 are the programming data in structures 103 connected. Accordingly, provide the sense amplifier 107 and the programming data in the structures 103 a data input and output circuit connected to the memory array.

The flash EPROM integrated circuit is typically operated in a read only mode, a program mode, and an erase mode. Accordingly, a mode control circuit 106 with the array 100 connected.

Finally, according to an embodiment of the present invention, during the program and erase modes, a negative potential is applied to either the gate or source and the drain of the memory cells. Therefore become a generator 108 for a negative voltage and a generator 109 used for positive voltage for the supply of different reference voltages to the array. The generator 108 for negative voltage and the generator 109 for positive voltage are driven by the power supply voltage V _CC .

2 shows two segments within a larger integrated circuit. The segments are approximately along the dashed line 50 divided and include the segment 51A essentially above the dashed line 50 and the segment 51B essentially below the dashed line 50 , A first couple 52 of columns in the segment 51A is a mirror image of a second pair 53 of columns in the segment 51B along a given global bitline pair (eg, the bitlines 70 . 71 ) formed a mirror image. As one progresses along the bitline pair, the memory segments are flipped over to form the virtual ground conductors 54A . 54B (buried diffusion) and the metal diffusion contacts 55 . 56 . 57 . 58 use together. The virtual ground leader 54A . 54B extend in a horizontal direction along the array to a vertical, metallic virtual ground line 59 through metal diffusion contacts 60A - 60B , The segments repeat on opposite sides of the metallic virtual ground line 59 such that adjacent segments define a metallic virtual ground line 59 use together. Thus, the layout of the segment requires 2 For each column of two transistor cells, two metal contact spacings for the global bit lines and one metal contact spacing per segment for the metallic virtual ground line 59 ,

Each of the pairs of columns (for example 52 . 53 ) along a given bit line pair comprises a set of EPROM cells. According to show the cells 75-1 . 75-2 . 75-N a first set of flash EPROM cells in a first of the pair 77 of columns. The cells 76-1 . 76-2 . 76-N assign a second set of Flash EPROM cells in the second column of the pair 77 of columns.

The first set of cells and the second set of cells share a common buried diffusion source line 78 , The cells 75-1 . 75-2 . 75-N are with the buried diffusion drain pipe 79 connected. The cells 76-1 . 76-2 . 76-N are with the buried diffusion drain pipe 80 connected. The selection circuit, which is the upper selection transistor 81 and the upper selection transistor 82 has, connects the corresponding drain diffusion lines 79 . 80 with metallic, global bitlines 83 respectively. 84 , Accordingly, the transistor 81 with its source with the drain diffusion line 79 and with its drain with a metal contact 57 connected. The transistor 82 is with its source with the drain diffusion line 80 and with its drain with the metal contact 58 connected. The gates of the transistors 81 and 82 are controlled by the signal TBSEL _A to form the respective columns of flash EPROM cells with the global bit lines 83 and 84 connect to.

The source diffusion line 78 is connected to the drain of the selection transistor 85 connected. The source of the selection transistor 85 is with a virtual mass diffusion line 54A connected. The gate of the transistor 85A is controlled by the signal BBSEL _A.

Furthermore, a sector of two or more segments may share wordline signals as in FIG 2 because of the additional decoding provided by the upper and lower block selection signals TBSEL _A , TBSEL _B and BBSEL _B. In one embodiment, eight segments share wordline drivers and provide an eight-segment deep sector.

As It can be seen represents the architecture according to the present invention a sectored flash EPROM array ready. This is advantageous given the source and drain of transistors in non-selected segments while a read, program or erase cycle from the streams and voltages on the bit lines and the virtual ground lines can be isolated. Accordingly, during a read operation improves the query because leakage current from segments, which is not selected are not contributing to power on the bitlines. During the programming and Deletions are the voltages of the virtual ground line and the bit lines from the unselected Isolated segments. this makes possible a sector-by-sector deletion process, either segmentally or, preferably, sectorally when the segments within a given sector word line drivers in common use.

It should be understood that the lower block select transistors (eg, the transistors 65A . 65B ) may not be required in a given implementation as described in 3 shown below. Furthermore, these block select transistors may share a lower block select signal with an adjacent segment. Alternatively, the lower block select transistors (eg 65A . 65B ) by individual isolation transistors at or adjacent to the virtual ground terminals 60A . 60B be replaced.

3 shows an alternative architecture of the flash EPROM array according to the present invention In which two columns of flash EPROM cells share a single metallic bit line. 3 Figure 4 shows four pairs of columns of the array, with each pair of columns having flash EPROM cells in a drain-source-drain configuration. Accordingly, the first pair 120 columns a first drain diffusion line 121 , a source diffusion line 122 and a second drain diffusion line 123 on. Word lines WLO through WL63 are respectively above the floating gates of one cell in a first of the pair of columns and a cell in the second of the pair of columns. As shown in the figure, a first pair 120 of columns one column on which the cell 124 , Cell 125 , Cell 126 and cell 127 includes. Not shown are cells connected to word lines WL2 to WL61. The second of the couple 120 of columns indicates the cell 128 , the cell 129 , Cell 130 and cell 131 on. Along the same column of the array is a second pair 135 represented by columns. It has a similar architecture to the couple 120 from columns except for the fact that it is mirror-inverted.

Thus, as can be seen, the transistor in the first of the pair of columns, such as the cell, includes 125 , a drain in the drain diffusion line 121 and a source in the source diffusion line 122 , A floating gate is above the channel region between the first drain diffusion line 121 and the source diffusion line 122 arranged. The word line WL1 is located above the floating gate of the cell 125 to provide a flash EPROM cell.

The column pair 120 and the column pair 135 use a virtual mass diffusion line 136 (ARVSS) in common. Accordingly, the source diffusion line 122 of the column pair 120 with mass diffusion 136 connected. Similarly, the source diffusion line 137 of the column pair 135 with mass diffusion 136 connected.

As mentioned above, each pair of columns share a single metal line. Thus, a right block select transistor 138 and a left block selection transistor 139 contain. The transistor 139 has a drain in the drain diffusion line 121 , a source that has a metal contact 144 and a gate connected to the control signal BLTR1 on line 141 is connected. Similarly, the right select transistor 138 a source in the drain diffusion line 123 , a drain that is in contact with the metal 140 is connected and a gate which, with the control signal BLTRO on line 121 connected is. Thus, the selection circuit includes the transistors 138 and 139 an optional connection of the first drain diffusion line 121 with a second drain diffusion line 123 to the metal line 143 over the metal contact 140 ago. As you can see, the column pair has 135 the left select transistor 144 and the right selection transistor 145 on that in a similar way with a metal contact 146 are connected. The contact 146 is with the same metal line 143 like the contact 140 connected, which with a pair of columns 120 connected is. The metal line can be shared by more than two columns of cells with an additional select circuit.

In the 2 and 3 The architecture shown is based on a drain-source-drain unit which forms two columns of cells which are insulated from adjacent drain-source-drain units to avoid leakage current from adjacent columns of cells. The architecture may be extended to units with more than two columns, with appropriate leakage current limits in the interrogation circuit or with other controls of current leakage from unselected cells. Thus, for example, fourth and fifth diffusion lines within a given isolated area could be added to create a drain-source-drain-source-drain structure having four columns of cells.

column pairs are arranged horizontally and vertically to provide an array of flash EPROM cells, which has M word lines and 2N columns. The array requires only N metallic bitlines, each with a pair of columns from flash EPROM cells over a selection circuit are connected, as described above.

Even if the figure only four pairs of columns 120 . 135 . 150 and 151 shows that with two metallic bit lines 143 and 152 (MTBLO-MTBL1), the array may be repeatedly provided in the horizontal and vertical directions as required to provide a flash EPROM memory array on a larger scale. Accordingly, the column pairs repeat 120 and 150 that share a word line in the horizontal direction to represent a segment of the array. Segments are repeated in the vertical direction. A group of segments (eg, eight segments) having respective wordlines connected to a shared wordline driver may be considered as a sector of the array.

The layout of the array is compact because of the virtual ground configuration, the reduced metal spacing requirement for the layout, and further the ability to divide word line drivers from a plurality of rows into different ones shared segments. Thus, the word line WL63 'may share a word line driver with the word line WL63. In a preferred system, eight word lines share a single word line driver. Thus, only the pitch of a wordline driver circuit is needed for each set of eight rows of cells. The additional decoding which is done by the left and right selection transistors ( 139 . 138 for the segment 120 ), allow configuration with a shared wordline. The shared wordline configuration has the disadvantage that, during a sector erase operation, eight rows of cells all receive the same wordline voltage, creating a wordline disturb on cells that are not to be erased. If it is a problem for a given array, this issue can be eliminated by ensuring that all sector clearances are decoded for segments including all rows of cells connected to the shared wordline drivers. For eight word lines sharing a single driver, minimum sector deletion of eight segments may be required.

4 Figure 3 is a schematic block diagram of a flash EPROM array intended to illustrate certain features of the present invention. Accordingly, the flash EPROM memory module, which is incorporated in 4 a flash EPROM main array including sectors 170-1 . 170-2 . 170-3 . 170-N , each sector comprising eight segments (eg SEGO-SEG7). A plurality of sets of shared word line drivers 171-1 . 171-2 . 171-3 . 171-N are used to drive the shared word lines of the eight segments in the respective sectors. As for the shared wordline drivers 171-1 As shown, there are 64 shared drivers for the sector 170-1 , Each of the 64 drivers provides an output on line 172 , Each of these outputs is used to provide eight word lines in corresponding segments of the sector 170-1 to drive, as shown schematically in the figure by the division into the eight sets of 64 lines.

Furthermore, with the array are a plurality of block selection drivers 173-1 . 173-2 . 173-3 . 173-N connected. The block select drivers each provide a left and a right block select signal for each segment. If the segments are implemented as in 3 As shown, there are a pair of block select signals BLTR1 and BLTRO which are supplied to each of the 64 word lines.

In addition, there are N global bit lines in the flash EPROM array. The N bit lines are used to access the 2N columns of flash EPROM cells in the array for the data in the circuit and sense amplifiers 191 to grant. The N bit lines 174 are with a column selection decoder 175 connected. Similarly, the block selection drivers 173-1 to 173-N connected to a block decoder. The shared wordline drivers 171-1 to 171-N be with the row decoder 177 connected. The column selection decoder 175 , the block decoder 176 and the row decoder 177 receive address signals on the address input line 178 ,

With the column selection decoder 175 is a page programming buffer 190 connected. The page programming buffer 190 has N switches, one for each of the N bit lines. Thus, one data page may be considered wide as N bits, with each row of cells being two pages, page 0 and page 1, wide. Pages in a given row are selected using the left and right decoding described above.

Selectable voltage sources 179 are used to provide the reference potentials for the read-only, program and erase modes for the flash EPROM array, as conceptually illustrated in the figure, by the wordline drivers 171-1 to 171-N and through the bitlines.

The virtual ground lines in the array are with the virtual ground driver 181 connected, which is connected to the array. Also, p-well and n-well reference voltage sources 199 connected to the corresponding wells of the array. Accordingly, how to get in 4 can recognize the 64 word line drivers, such as the word line drivers 171-1 , used with 512 (64 × 8) rows in the array. The extra decoding provided by the block selection drivers (e.g. 173-1 ), allows the layout of the shared word lines.

The architecture of the flash EPROM array according to the present invention allows for row redundancy as shown schematically in FIG 4 is shown. Thus, W bit lines extend from the main array via lines 182 to a redundant array, which sectors 183-1 and 183-2 includes. The redundant array is driven by the redundant wordline drivers 184-1 and 184-2 driven. Similarly, the redundant block selectors are drivers 185-1 and 185-2 connected to the redundant array.

If, during testing, a cell of a given row is found to be defective these rows and the seven other rows sharing the wordline driver through corresponding rows in the redundant array 183-1 and 183-2 be replaced. Thus, the system would be a cell 198 Content Addressable Memory (CAM) include a redundant decoder 186 which receives the address data. As is known in the art, faulty rows in the main array may be identified during testing and the address of these rows will be in the CAM cell 198 saved. If the address is ADDRIN on line 178 with the in the CAM cell 198 stored address, then a match signal on line 187 generated. The match signal switches the shared wordline drivers 171-1 to 171-N in the main array. The redundant decoder 186 controls the redundant word line drivers 184-1 and 184-2 and controls the redundant block selection drivers 185-1 and 185-2 to select the appropriate replacement row.

The Redundant row decoding can also be done with redundant column decoding coupled, as is known in the art, to a Flash EPROM array with a much higher yield in the production provide.

The column selection decoder 175 is with side programming switches 190 including at least one switch for each of the N bit lines. Furthermore, the column selection decoder 175 with the data input circuit and the sense amplifiers 191 connected. Together, these circuits provide a data input and output circuit for use with the flash EPROM array.

A Redundant row decoding also provides the ability to correct short circuits between adjacent word lines. In particular, if two word lines are shorted, the two word lines by two corresponding Word lines are replaced in the redundant array. In the described embodiment, where there are eight wordlines that share a common wordline driver use two sets of eight word lines together used to corresponding two sentences of eight word lines in the main array. Accordingly, the two shorted word lines in the main array through the Row redundancy to be repaired.

The Cells in the preferred embodiment are for a sector deletion process designed, which causes a charging of the floating gate (Electrons enter the floating gate), so that when interrogating one deleted Cell the cell is not conducting and the output value on the sense amplifier is high is. Furthermore, the architecture is for page programming designed, which includes the unloading of potential-free gates (Electrons leave the floating gate), so that when querying a programmed cell is conductive.

The operating voltages for the programming operation are positive 5V at the drain of a low threshold state (data = zero) cell to be programmed, negative 10V at the gate and 0V or floating at the source. The substrate or in the 5G and 6F shown p-well 200 is or are grounded. This results in a Fowler-Nordheim tunnel mechanism for discharging the floating gate.

Of the deletion is running by applying negative 6V to the drain, positive 12V to the drain Gate and negative 6V at the source. The p-well 200 is negative Biased 6V. this leads to to a Fowler-Nordheim tunnel mechanism for loading the potential-free Gates. The read potentials are 1.2V at the drain, 5V at the gate and 0V at the source.

This represents the ability ready to be deleted using word line decoding, chosen Cells perform a sector deletion. Of the Erase disturbance condition for non-selected cells within a segment yields -6V at the drain, 0V at the Gate and - 6V at the source. This is well within the tolerance of the cells, to sustain these potentials without a significant disruption of the charge in the cell to cause.

In similar The amount of fault conditions for programming for cells, which share the same bitline in the same segment, 5V at the drain, 0V at the gate and 0V or floating at the gate Source. In this state, there is no drive from gate to drain and he disturbs the Cell not significant.

For cells, which share the same wordline, but not the same Bit line, or an addressed cell, which is in a high state should remain the fault condition 0V at the drain, -10V at the gate and 0V or floating at the source. This too Condition does not lead to a significant disorder the cargo in the unselected Cells.

Two-well technology is critical to applying the negative voltage to the drain and source voltage fusion regions. Without the negative voltages at the source and the drain, the gate potential for a cell would have to be within a coupling ratio of 59% about 9V voltage drop at the junction from floating gate to drain requires about 18V. These very high voltages on integrated circuits require specially designed circuits and special process technology. Similarly, the negative voltage at the gate allows lower positive potentials at the drain for the programming operation.

4A FIG. 11 is a flow chart illustrating the programming procedure for the flash EPROM circuit. FIG 4 shows. The process begins by deleting the sector (for example sector 170-1 ), in which data should be programmed (block 600 ). After deleting the sector, an erase verify operation is performed (block 601 ). Next, the page number, either 0 or 1, and the segment number (1-8) are set in response to the input address by the host processor (Block 602 ).

After setting the page number and the segment number, the page buffer is loaded with the data for the page (block 603 ). This page buffer can be loaded with a full N bits of data, or with a single byte of data, depending on how it fits a particular programming operation. Next, a verify operation is performed, provided the user does not pre-erase to determine which cells need programming (Block 604 ). After loading the page buffer, the programming potentials are applied to the segment being programmed (block 605 ). After the programming process, a verification process is performed in which the page is verified. In the verify operation, the bits in the page buffer that correspond to successfully programmed cells are turned off (Block 606 ). Next, the algorithm determines if all page bits in the page buffer are turned off (block 607 ). If they are not all turned off, the algorithm determines if a maximum number of retries has been performed (Block 610 ), and if not, it goes to block in a loop 605 to reprogram the page so that the erroneous bits are reprogrammed. The bits that pass are not reprogrammed because the corresponding bits in the page buffer have been reset to zero during the verify process. If the maximum number of retries in block 610 has been performed, the algorithm is terminated and indicates an unsuccessful operation.

If in block 607 all bits are off, the algorithm determines if the sector has been completed, ie if both sides of the sector should be written and if both are complete (block 608 ). This is a parameter determined by a CPU. If the sector is not completed, the algorithm loops to block 602 and updates the corresponding page number or segment number.

If the sector is in block 608 has ended, then the algorithm is done (block 609 ).

As with reference to block 605 from 4A has been mentioned, the program verification circuit comprises the bit-by-bit resetting of the data in the page buffer which successfully passes through the erase verification. Thus, a structure as simplified in 4B is shown in the flash EPROM included. The query amplifier 650 of the array are using a comparator circuit 651 connected. The inputs to the comparator circuit are the page buffer switches 652 , Thus, a byte of data from the sense amplifiers is compared to a corresponding byte from the page buffer. A pass / fail signal for the byte will go to a bit reset on the page buffer 652 fed back. Thus, bits that exist (the verification) are reset in the page buffer. When all the bits in the page buffer have been reset, or when a set number of retries of the program operation has been performed, the programming operation is completed.

The 5A - 5H show manufacturing steps for a flash EPROM array according to an embodiment of the present invention. 5A - 5G are not drawn to scale. 5H is an approximate scale drawing to provide a view of the resulting structure. 6A - 6G represent an alternative approach to the manufacture of the flash EPROM cell, which incorporates the same initial steps as described in U.S.P. 5A - 5D are shown. As in the case of 5H , is also the 6G an approximate scale drawing of the resulting structure. 7 and 8th - 14 are used to layout a test array with three word lines by six columns for reference to the 5A - 5H and 3 to describe described embodiment.

The process of 5A - 5H will be described first. The cell is fabricated using a 0.6 micron CMOS double metallic well (two wells in the array, a third for the peripheral circuitry) and a triple polysilicon technique. The first steps associated with the production of the cell are in the 5A - 5H played.

5A illustrates the first step in the process. Starting with a silicon substrate 200 p-type (or a portion of the substrate), an n-type deep well 198 of about 6 microns in depth is formed. Next, a p-world 199 of about 3 microns depth is formed within the n-well.

Of the deep n-well 198 is first implanted by implanting a dopant n-type formed in the substrate, wherein the n-well region is determined by a photoresist mask. After implantation the photomask is removed and the substrate becomes at high temperature for one annealed for a relatively long time to drive in the n-type dopant and activate to form the deep well ("pit"). Then a similar Process performed, to implement a p-well within the deep n-well.

In the next step, a well-known LOCOS field oxidation process is used to create relatively thick field oxide regions 201 and 202 grow up, which are elongated in a direction perpendicular to the side. In addition, a sacrificial oxide layer is grown, which is then removed to prepare the surface of p-well 199 for subsequent steps.

As in 5B is shown, one leaves a thin tunnel oxide 203 grow with about 90Å. As in 5C is shown, a first polysilicon layer 204 of about 800Å on the tunnel oxide 203 deposited. Then a thin nitride layer 205 of about 200Å on top of the polysilicon layer 204 deposited.

As in 5D As shown, a photomasking process is used to define the floating gates and the n + source and drain diffusion regions. Accordingly, photomask layers 206 . 207 fixed to the floating gate regions in the first polysilicon layer 204 to protect. The first polysilicon layer 204 and the nitride layers 205 are etched away except where the masks 206 and 207 Protect to set the drain, source and drain areas. Next, n-type dopants are implanted into p-well 199, as indicated by arrows 208 is illustrated within the exposed areas. These regions are therefore with the floating gate in the first polysilicon layer 204 and the field oxidation regions 201 and 204 aligned identically.

As in 5E As shown, the substrate is annealed to activate the dopants and the drain diffusion regions 213 and 214 as well as the source diffusion area 215 define. Furthermore, drain oxides are allowed 216 . 217 and source oxides 218 grow by about 2,000Å, along with oxides 225 and 226 covering the sides of the polysilicon layer 204 of the floating gate.

The next step is the nitride layer 205 the floating gates are removed and it becomes a second layer 219 polysilicon (poly two) deposited on the first layer. The second layer 219 is about 800Å thick and deposited on top of the first polysilicon layer (poly one). This layer is implanted with an n-type dopant.

As in 5F A photomasking process is used to define the pattern of poly two, which in turn defines the effective floating gate region as seen from the control gate formed in the polysilicon layer 3 (poly three) must be deposited. The effective floating gate area is increased by the poly-two deposition so that the coupling ratio is large enough and is preferably about 50% or greater. During the subsequent high temperature annealing steps, the n-type dopants distribute evenly between the layers poly two and poly one, resulting in a very low contact resistance between the two layers.

As in 5G shown, one leaves an ONO layer 220 growing on top of the poly two layer. The ONO layer is about 180Å thick. Finally, a third polysilicon layer 231 (poly three) deposited on top of the ONO layer and after the deposition of tungsten silicide, as in 5H is etched to define the word line for the memory cells.

5H shows the layer of tungsten silicide 234 over the poly-3 layer 221 , which is used to improve the conductivity of the word lines. 5H is an approximate scale sketch of the structure of the resulting cell. According to the process after the 5A - 5H becomes the drain diffusion area 213 in a region between the field oxide 202 and the poly-1 layer of the floating gate 230 formed, which is about 0.6 microns wide. Similarly, the poly-1 region of the floating gate 230 about 0.6 microns wide. The source diffusion region between the floating gate regions 230 and 232 is approximately 1.0 microns wide. The drain diffusion area 214 is approximately 0.6 microns wide.

The 1 micron wide source diffusion area 215 is made slightly wider to provide alignment tolerances for the poly-2 deposition process. With a more precisely controlled alignment process, the width of the source diffusion region could 215 be reduced.

The vertical dimensions of the different elements are in 5H reproduced approximately to scale. Accordingly, the tunnel oxide 203 under the poly-1 region of the floating gate electrode 230 or 232 about 90Å thick. The deposition poly-1 230 is about 800Å thick. The oxide area 216 over the drain diffusion area 213 and, similarly, the oxides over the source diffusion region 215 and the drain diffusion region 214 can be grown to about 2,000 to 2,500 Å thickness, but they are in the final state in the range of 1,000 to 1,500Å.

The sidewall oxide 226 on the poly-1 area of the floating gate 230 is in the range of 600Å thick. As you can see in the sketch, it fuses with the thermal oxide 216 across the source or drain diffusion region, as appropriate.

The thickness of the second polysilicon deposition 231 is approximately 800Å. The thickness of the ONO layer 220 is about 180Å. The third poly layer 221 is about 2,500Å. The tungsten silicide layer 234 is about 2,000Å thick. The field oxide area 202 in the finished product is in the range of a thickness of 6,500 to 5,000 Å.

5H illustrates a feature of the process of 5A - 5H , As you can see, covers in 5G the second poly-deposition 233 only partially the drain diffusion area 214 from. In 5H For example, an alternative mask is used so that the poly-2 region of the floating gate extends over the drain diffusion region and partially the field oxide region 202 overlaps. This variability in the process allows the coupling ratio of the floating gate to be varied, as appropriate to the needs of a particular design, by extending its length across the field oxide region.

Metallization and passivation layers (not shown) are placed over the circuit of the 5H deposited.

Accordingly, how to get in 5H can provide a floating gate structure for a flash EPROM segment having a drain-source-drain configuration made up of a first polysilicon layer 230 and a second polysilicon layer 231 consists. The first layer of poly 230 is used for the self-alignment of the source and drain diffusion regions. The second layer poly 231 is used to expand the surface area of the floating gate to increase the coupling ratio of the cell.

In the drain-source-drain configuration, it can be seen that the floating gate, which consists of the poly-1 layer 230 and the poly-2 layer 231 for the cell on the left side, and the floating gate, which consists of the poly-1 layer 232 and the poly-2 layer 233 for the cell on the right side of the figure, are substantially mirror images of each other. This allows expansion of the floating gate beyond the drain diffusion regions in the drain-source-drain configuration without creating a significant short across the shared source diffusion region.

The Cell technology and layout have a number of advantages. The tunnel oxide is allowed to proceed grow the source / drain implant of the array. Accordingly, be Oxide thickening and dopant depletion effects made minimal. The source and drain implantation of the memory cell is self-aligning to the poly-1 pattern. Thus, the channel length of the Cell be well controlled.

There is a lazy scale for the metal design that can be used with the flash array, especially in architecture 3 , The source-block transistor merges with the source / drain diffusion of the memory cell in the cell layout. This overlap area provides a connection between these two diffusion areas. The field oxide is used to isolate the bit line pairs from adjacent bit lines. Within the bit line pair, the structure is flat.

Furthermore, for in the 5A - 5H 1, the effective gate coupling region, as seen from the control gate, is determined by the area of the second polysilicon layer. Therefore, a reasonably high gate coupling ratio can be achieved by extending the second layer of polysilicon over the buried diffusion or field oxide regions to compensate for the low gate coupling ratio that would be obtained solely by the first layer of polysilicon. Further, by extending the length of extension of the second layer of polysilicon beyond the diffusion regions and isolation regions, different gate coupling ratios can be readily achieved to accommodate different product applications.

An alternative cell structure is according to the 6A - 6G played. This structure begins with the same manufacturing steps as those in the 5A - 5D are shown above.

Accordingly, how to go in 6A can see the sequence of the structure after 5D Continue by first the masks 206 and 207 be removed and then a nitride layer 250 above that Area is deposited. The nitride layer covers the sides of the polysilicon layer 204 of the floating gate, as shown in the figure.

In the next step, as in 6B shown using anisotropic etching to the deposited nitride layer 250 with the exception of those areas of the layer on top of the polysilicon layer 204 of the floating gate and on the sides thereof.

The etching may take a small amount of nitride on the edges of the field oxide regions 201 . 202 leave. However, this is not essential to the process.

After the anisotropic etching of the nitride, the wafer is annealed to drive in the dopants around the drain diffusion regions 213 and 214 and the source diffusion region 215 train. In addition, the thermal oxides are allowed 216 . 217 and 218 grow over the drain diffusion regions or the source diffusion region. The nitride layers 205 and 250 protect the polysilicon layer 204 of the floating gate from oxide formation.

In the next step, as it is in 6C shown, the nitride residues of the layer 205 and the layer 250 removed from the structure what the potential-free gate elements 204 the poly-1 exposes.

The next step is how it works in 6D is shown, a second poly-deposition 219 deposited on the structure. This second layer of poly 219 is deposited to a thickness of about 1,500 to 2,000 Å and doped or implanted with an n-type dopant.

As in 6E is shown are spacers 214 and 241 formed of polysilicon along the edges of the poly-1 pattern using a self-aligned plasma etching on the poly-2-Schciht.

During the Following high-temperature steps, the dopants are distributed n-type in the poly-2 deposition uniformly between the poly-1 and the poly-2 elements and make a good electrical contact ago.

As in 6F is an ONO layer 220 deposited over the floating gate structures on the poly-1 element 242 and the poly-2 spacers 240 and 241 are formed. In addition, in this process, a range of polysilicon 243 next to the field oxide area 201 be left. However, there is no electrical contact in this area and it should not affect the operation of the device. After depositing the ONO layer 220 becomes a third polysilicon layer 221 deposited with a thickness of about 2,500 Å to form the word lines of the device.

6G illustrates the last step in the process of depositing a layer of tungsten silicide 234 with a thickness of about 2,000Å over the poly-3 word line 221 to improve the conductivity of the structure.

6G is also an approximate scale drawing of the structure. Thus, as can be seen, the drain diffusion regions become 213 and 214 in a region between a field oxide 202 and the floating gate 204 formed of about 0.5 microns wide. The poly-1 deposition 204 of the floating gate has a thickness of about 0.15 microns. In addition, the source diffusion range 215 , which is formed between the poly-1 floating gates, in this embodiment, about 0.6 microns. The narrower source diffusion area 215 compared to the after 5H This approach is possible because of the self-aligning nature of the poly-2 spacers 214 and 241 , There is a layout with a structure like it is in 6 There is no need to consider mask misregistration tolerances necessary to align the mask to detect the poly-2 floating gate expansions 5H to build. This makes up the structure 6G expandable as the dimensions of the process shrink without requiring error tolerances for mask misalignment.

The thicknesses of the areas in the vertical dimensions are similar to those of the 5H , The poly-1 deposition 242 however, it is about 1,500 to 1,600 Å thick. The spacers 214 and 241 extend about 2,000 Å beyond the source and drain diffusion regions.

In an alternative process for fabricating a structure as shown in FIG 6G is shown, the second nitride layer 250 not separated. During the tempering step after 6B however, oxide is allowed to grow on the side of poly-1 deposition. These oxides on the sides of the polysilicon layer can be etched away so that contact between poly-1 and poly-2 can be provided in the subsequent steps. However, etching the oxide on the side of the poly-1 region of the floating gate entails the risk of etching the oxide between the floating and the substrate. If this region is etched too far, a short circuit may occur during poly-2 deposition on the substrate. Accordingly, in the 6A - 6G illustrated process for many applications may be preferable.

The used in the described structure Polysilicon for the potential-free gate can be replaced by amorphous silicon.

For a better understanding of the layout of the integrated circuit according to the invention, the 7 - 14 used to describe the layout of a test array that has dimensions of six columns by three wordlines. 7 is a composite view that is better in terms of the layout views after the 8th to 14 understands. How to get in 7 can recognize, the test array includes five field isolation areas 400 . 401 . 402 . 403 and 404 , The layout of these isolation areas can be done according to 8th recognize where the field oxide areas with reference numbers 400 - 404 are marked and the hatched area 405 corresponds to an active area within the well 199 from the p-type 5G ,

9 Figure 12 illustrates the layout of a p-type implant used to increase the threshold voltage VT of the memory cells. The implantation agent in the area 406 causes a higher initial VT for the memory cells in the block than for the selection transistors (in areas passing through the lines 436 and 437 in 7 are circled).

The array also includes the poly-3 control lines 407 and 408 for the corresponding right and left select transistors for each of the three segments. 7 also shows three word lines 409 . 410 and 411 that are above the three segments of the array. The first poly layer is in 7 through the solid outline 415 reproduced and one recognizes them more clearly also in 10 , There are segments 416 . 417 . 418 . 419 . 420 and 421 in the first poly-layer, as in 10 which are used for self-alignment of the left and right selection transistors. These segments are later removed after the formation of the source and drain regions of the cells. Thus illustrated 10 the masking of the poly-1 deposition. Poly-1 is deposited and within the area passing through the line 415 is defined, as well as in the areas which the layout is based on 10 surrounded, etched, after the first layer polysilicon of the floating gates after 5G provide.

11 shows the mask pattern for the second poly layer for the in 5G represented cell. areas 412 . 413 and 414 are in 7 recognizable. areas 422 and 423 correspond segments of the polysilicon layer of the floating gates over the field isolation regions 401 and 403 in 7 , The poly-2 pattern is later formed to after the extended floating gate 5G provide.

12 illustrates the layout of the poly-3 control lines 407 and 408 and the wordlines 409 . 410 and 411 ,

13 illustrates the metal contacts 424 . 425 . 426 . 427 . 428 and 429 in the test array. The contact 424 is used to control the poly-3 control line 408 to contact. The contact 428 is used to make a metal contact for the poly-3 control line 407 manufacture. contacts 425 . 426 and 427 are used to make contact from the diffusion region of the selected transistor to the global metallic bit lines that pass over the array (in FIG 7 not shown). The contact 429 is used to make contact with the source diffusions of the array. The layout of the metal lines is in 7 shown. As you can see, they align themselves with the contacts 425 . 426 and 427 off and over the segments in the array. Accordingly, the metallic bit line 430 with the contact 125 connected, the metallic bit line 431 is with the contact 426 connected and the metallic bit line 432 is with the contact 427 connected. The metal pads 433 and 434 are with contacts 428 respectively. 424 connected. The metal pad 435 is with the contact 429 connected.

Accordingly, in 8th in the sequence a field isolation and diffusion step is shown. Next, an implantation step of VT elevation in the in 9 shown area 406 executed. Next, the polysilicon layer of the floating gate is deposited. In addition, the segments 416 - 421 with poly-1 deposited to provide the channels for the left and right block select transistors. Then, a source / drain implant is performed to form the drain-source-drain structure and the buried diffusions for the left and right block selection transistors and the virtual ground terminal. After this implantation, the poly-2 is deposited as shown in FIG 11 is shown. Poly-2 is patterned as described above to provide the extended floating gates. An insulating layer is placed over poly-2 and the third layer of polysilicon is deposited in a pattern as shown in FIG 12 is shown. Finally, an insulation is deposited over the poly-3 layer, the metal contacts are made, and the metallic bit lines overlying the array are deposited. How to get in 7 can recognize, the left selection transistor is located under the control line 408 in that by the line 436 circled area. Similarly, the right one lies Selection transistor for the first segment under the control line 407 in the area that goes through the line 437 circled. The contact 425 reaches a diffusion area 438 , The diffusion area 438 is opposite to a diffusion region 439 through the masked area 440 isolated, which was defined by the poly-1 deposition. similarly, the diffusion region is 438 from the diffusion area 441 through the masked area 442 isolated, which was masked by the poly-1 deposition. Thus, a selection column for the left column is provided over the channel passing through the area 442 is defined. The diffusion area 441 is in or is connected to the drain diffusion region for the segment. Similarly, the diffusion region is located 439 within the drain diffusion region for the segment or is connected to the right side thereof.

The current path for the contact 425 to the left diffusion area for the segment is indicated by the arrow line 443 shown. As can be seen, this path becomes through the transistor channel in the area 242 interrupted. Accordingly, the control line 408 a connection for the left drain diffusion region to the contact 425 ready.

The current path for the right block select transistor is indicated by the arrow line 444 shown. As you can see, this path through the channel is in the area 440 interrupted. The two selection transistors in the areas 436 and 437 thus provide an optional connection of the contact 425 ready with either the left or the right diffusion area. In this way, two columns of flash EPROM cells are placed over the contact 425 optionally connected to a single metallic bit line.

As those skilled in the art will recognize, the masking sequence of the 8th - 14 for the in 6G The cell shown changes with respect to the deposition steps of poly-2. The basic layout of the array, however, remains unchanged.

Accordingly a new flash EPROM cell and array architecture is provided Service. The architecture provides a very dense core array which is obtained by unique cell layouts wherein two adjacent local drain bit lines have a common source bit line use together. Besides that is The layout has been optimized to use a single metallic one Headed for allow two columns of cells in the array. Farther The layout is further reduced or simplified by common used word lines, so that the Repeat distance of word line drivers not the dimensions of the main array (negative) affected. A sector clearing is possible using the segmentable architecture of the present invention Invention. Furthermore is for a flash EPROM using this structure provides row redundancy available. Using these technologies, you can create a high-performance, reliable flash memory array to reach.

It is an n-channel embodiment of the flash EPROM array. Professionals in the field recognize that equivalent p-channel circuits can be used using techniques which are known in the art. Furthermore, the architecture is regarding flash EPROM cells been developed. Many aspects of architecture, however, can adapted to a variety of memory array circuits.

The above description of a preferred embodiment of the invention for the purpose of illustration and description. It should not be exhaustive and not the invention to the exact forms shown restrict. Obviously, many modifications and variations are experienced Practitioners in this field are obvious. The scope of the invention is intended by the following claims and their equivalents be determined.

Claims (10)

A method of programming a data structure in a set of flash memory cells, comprising: loading the data structure into a buffer ( 190 ; 652 ), Programming ( 605 ) of the set of flash memory cells by connecting the buffer with bitlines for the set of flash memory cells and applying programming potentials at least to the control gates of the set of flash memory cells, after the step of programming, comparing ( 651 ) of the outputs from the set of flash memory cells with the data in the buffer to verify the programming, the method being characterized by: clearing ( 606 ) of a corresponding bit in the buffer for cells in the set of flash memory cells whose output values match the data in the buffer and, if any bits of the data structure in the buffer remain undeleted, re-executing the steps of programming and comparing. The method of claim 1, wherein the step of programming ( 605 ) leads to a discharge of the floating gates in the flash memory cells, and further including before the programming step loading the floating gates of the set of flash memory cells. The method of claim 2, wherein the pro programming step ( 605 ) apply a negative potential to control gates of the cells in the set in combination with applying a positive potential to the drains of the cells in the set to be discharged as well as applying a second potential lower than the positive potential the drains of the cells in the set that should remain loaded according to the data in the buffer. The method of claim 3, wherein the second potential is essentially mass. The method of claim 3, wherein the step of Loading the floating gates, creating a positive potential at control gates, applying a negative potential to drains and applying a negative potential to sources of the cells in the sentence. The method of claim 5, wherein the set of flash memory cells formed with a p-type well and the p-type well within an n-type well in one Semiconductor substrate is formed, and wherein the step of loading floating gates of cells in the set bias the well p-type having a negative potential. The method of claim 1, wherein, after retrying the steps of programming and comparing, not all cells are confirmed, the deleting and retrying steps are repeated until all cells pass the test or until a maximum number of retries ( 610 ) was executed. The method of claim 3, wherein the set of flash memory cells comprises at least 2N columns of cells ( 170-1 . 170-2 . 170-3 ... 170-N ) and N global bitlines ( 174 ) having at least 2N columns of cells through a selection circuit ( 138 . 139 ), and wherein the step of connecting the buffer to bit lines comprises operating the selection circuit in response to an address signal ( 178 ) to connect the buffer to N columns of the at least 2N columns of cells. The method of claim 8, wherein the buffer is a Page of data having N bits of data such that rows of memory cells in the set of flash memory cells, respectively save at least two pages of datastores. The method of claim 1, wherein the set of flash memory cells consists of flash EPROM cells.