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DE602005027338D1 - Abzweigungsvorhersageeinrichtung, verfahren dafür und prozessor - Google Patents

Abzweigungsvorhersageeinrichtung, verfahren dafür und prozessor

Info

Publication number
DE602005027338D1
DE602005027338D1 DE602005027338T DE602005027338T DE602005027338D1 DE 602005027338 D1 DE602005027338 D1 DE 602005027338D1 DE 602005027338 T DE602005027338 T DE 602005027338T DE 602005027338 T DE602005027338 T DE 602005027338T DE 602005027338 D1 DE602005027338 D1 DE 602005027338D1
Authority
DE
Germany
Prior art keywords
branching
processor
method therefor
precision device
precision
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005027338T
Other languages
English (en)
Inventor
Mikio Hondou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE602005027338D1 publication Critical patent/DE602005027338D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3848—Speculative instruction execution using hybrid branch prediction, e.g. selection between prediction techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE602005027338T 2004-04-21 2005-04-20 Abzweigungsvorhersageeinrichtung, verfahren dafür und prozessor Active DE602005027338D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004125465 2004-04-21
PCT/JP2005/007557 WO2005103886A1 (ja) 2004-04-21 2005-04-20 分岐予測装置、その方法、及びプロセサ

Publications (1)

Publication Number Publication Date
DE602005027338D1 true DE602005027338D1 (de) 2011-05-19

Family

ID=35197153

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005027338T Active DE602005027338D1 (de) 2004-04-21 2005-04-20 Abzweigungsvorhersageeinrichtung, verfahren dafür und prozessor

Country Status (7)

Country Link
US (1) US7827393B2 (de)
EP (1) EP1739549B1 (de)
JP (1) JP4213181B2 (de)
KR (1) KR100785723B1 (de)
CN (1) CN100520713C (de)
DE (1) DE602005027338D1 (de)
WO (1) WO2005103886A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7523298B2 (en) * 2006-05-04 2009-04-21 International Business Machines Corporation Polymorphic branch predictor and method with selectable mode of prediction
US8935517B2 (en) * 2006-06-29 2015-01-13 Qualcomm Incorporated System and method for selectively managing a branch target address cache of a multiple-stage predictor
CN101533344B (zh) * 2008-03-10 2011-04-06 王得安 一种用以储存目标地址的分支目标缓冲器系统及方法
CN101763248A (zh) * 2008-12-25 2010-06-30 世意法（北京）半导体研发有限责任公司 用于多模式分支预测器的系统和方法
CN102053818B (zh) * 2009-11-05 2014-07-02 无锡江南计算技术研究所 分支预测方法及装置
US20210149676A1 (en) * 2019-11-14 2021-05-20 Higon Austin R&D Center Corporation Branch Prediction Method, Branch Prediction Unit and Processor Core

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4943908A (en) * 1987-12-02 1990-07-24 International Business Machines Corporation Multiple branch analyzer for prefetching cache lines
JPH0628184A (ja) 1991-08-26 1994-02-04 Internatl Business Mach Corp <Ibm> ブランチ予測方法及びブランチプロセッサ
US5519841A (en) * 1992-11-12 1996-05-21 Digital Equipment Corporation Multi instruction register mapper
US5729726A (en) * 1995-10-02 1998-03-17 International Business Machines Corporation Method and system for performance monitoring efficiency of branch unit operation in a processing system
JP3760041B2 (ja) * 1996-12-09 2006-03-29 松下電器産業株式会社 分岐予測する情報処理装置
JPH10240526A (ja) 1997-02-27 1998-09-11 Fujitsu Ltd 分岐予測装置
US6427206B1 (en) * 1999-05-03 2002-07-30 Intel Corporation Optimized branch predictions for strongly predicted compiler branches
JP2002163150A (ja) 2000-11-28 2002-06-07 Toshiba Corp プロセッサ
US7134005B2 (en) * 2001-05-04 2006-11-07 Ip-First, Llc Microprocessor that detects erroneous speculative prediction of branch instruction opcode byte
JP4027620B2 (ja) * 2001-06-20 2007-12-26 富士通株式会社 分岐予測装置、プロセッサ、及び分岐予測方法
US7461243B2 (en) * 2005-12-22 2008-12-02 Sun Microsystems, Inc. Deferred branch history update scheme

Also Published As

Publication number Publication date
CN100520713C (zh) 2009-07-29
JPWO2005103886A1 (ja) 2008-03-13
KR20070009594A (ko) 2007-01-18
US20070005945A1 (en) 2007-01-04
JP4213181B2 (ja) 2009-01-21
CN1947093A (zh) 2007-04-11
EP1739549B1 (de) 2011-04-06
US7827393B2 (en) 2010-11-02
EP1739549A4 (de) 2008-04-30
KR100785723B1 (ko) 2007-12-18
EP1739549A1 (de) 2007-01-03
WO2005103886A1 (ja) 2005-11-03

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