DE602004006620T2 - A FET ARRANGEMENT AND A METHOD FOR MAKING A FET ARRANGEMENT - Google Patents

Abstract

Provided is a method of manufacturing a field effect transistor with an organic semiconductor, and particularly a device comprising a plurality of field effect transistors with an interconnect structure. Herein, use is made of three photolithographical masks for four layers. Thereto, the transistor is provided in a top-gate structure, and the organic semiconductor layer ( 307 ) and the dielectric layer ( 309 ) are structure and patterned together. The semiconductor layer ( 307 ) and the dielectric layer ( 309 ) may be removed from areas not associated with field effect transistors ( 300 ) or with crossing conductors of the first and second conductor layer ( 303, 305, 501 ).

Description

The The invention relates to a method for producing an electronic Arrangement, wherein in the method at least one field effect transistor created with an organic semiconductor layer on a substrate becomes.

The The invention also relates to an electronic device a plurality of field effect transistors with an organic Semiconductor layer and a connection structure to the transistors to connect with each other and / or with an output terminal.

It has been known for many years electronic semiconductor components such as bipolar and field effect transistors using semiconductor materials such as silicon, germanium and gallium arsenide. specially integrated circuits with many electronic components will be by deposition of conductive, semiconducting and dielectric layers made on a substrate.

In In recent years it has been recognized that some organic materials, such as pentacene, can exhibit semiconductor properties. Semiconductor components, groupings and circuits with organic semiconductors promise a number of advantages over traditional semiconductor-based structures including mechanical Flexibility, Solution processability and low temperature treatment. Accordingly, much research has been done in the field of organic semiconductors and the production of on organic semiconductors based semiconductor components and circuits.

Currently, organic semiconductor transistors are fabricated using standard photolithographic techniques. 1 illustrates the structure 100 of an organic semiconductor according to the prior art (see also US 6,335,539 for further references). The fabrication of the semiconductor involves a minimum of three or four mask steps. The semiconductor structure 100 is on a substrate 101 produced. First, the gate layer 103 (usually a metal layer, for example gold) on the substrate 101 deposited and structured by photolithography. Then, a dielectric layer 105 deposits (for example, an organic HPR504 layer) and patterned to make holes for vertical connections. The third layer 107 . 109 is a source-drain layer (made, for example, of gold) that is patterned to be the source 107 and the drain 109 of the transistor. Finally, an organic semiconductor 111 landfilled. The gate-source and gate-drain overlap is typically 5 μm, which is the same size normally used for the channel length (ie, the gap between the source and the drain).

Patterning of the semiconductor is desired to access the electrodes of the gate layer. In addition, patterning of the semiconductor layer is preferred to reduce leakage current and avoid the generation of false transistors caused by gate layer interconnections 103 , the semiconductor areas between electrodes of the source-drain layer 107 . 109 cross, be formed. But the patterning of the semiconductor requires an additional structuring step, which makes the manufacturing process a four-mask process.

deposition of the different layers is basically a cheap and simple process. For example, spin coating may be used In order to inexpensively and efficiently a dielectric or semiconductor layer to distribute. But structuring generally uses lithographic techniques, which are relatively expensive and complicated lithographic techniques. Accordingly would be a reduction advantageous in manufacturing costs and complexity.

The conventional method for producing an organic field effect transistor involves processing the source-drain layer between deposition the dielectric and the semiconductor layer. This has a tendency To introduce impurities between the dielectric and the semiconductor layer while reducing the power of the transistor. Accordingly would be one improved performance and a reduced amount of impurities advantageous.

A electronic arrangement with field effect transistors, such as an integrated Circuit, which is manufactured with the conventional approach has typically one or more layers (e.g., the dielectric layer or the semiconductor layer) extending over the entire surface of the Grouping extend. This reduces the mechanical reliability the structure significantly, which increased causing mechanical stress and reduced mechanical flexibility. Accordingly would be an electronic device with field effect transistors and a Manufacturing process, the improved mechanical characteristics and resistance achieved, advantageous.

Accordingly the invention preferably seeks one or more of the above-mentioned disadvantages individually or in any combination to milder, reduce or to eliminate.

According to a first aspect of the invention, a method for producing a field effect transistor array provided on a substrate, the method comprising the steps of: applying a patterned first conductor layer on the substrate; Depositing an organic semiconductor layer on the first conductor layer; Depositing a dielectric layer on the semiconductor layer; joint structuring of the semiconductor layer and the dielectric layer; and applying a patterned second conductor layer on the patterned dielectric layer.

The Application of the structured conductor layers can either directly by applying the conductive material in the desired Structure (e.g., by vapor deposition through a shadow mask) or can be a two-step process of deposition of the conductive material followed by a step of structuring the layer. Transfer a pattern in or structuring a layer generally contains any suitable means for providing a desired pattern or pattern in the layer.

The Invention allows a field effect transistor array to be made which is both a structured dielectric layer as well has a semiconductor layer while only three masks are used. Especially by structuring the layers in the way that the semiconductor and the dielectric Layer can be structured together, is only one Structuring step for structuring these layers necessary. In particular, only a single photolithography step is for structuring the semiconductor and the dielectric layer necessary, what thereby reduces the number of photolithographic steps necessary are a structured semiconductor and dielectric layer to achieve.

So allows the invention a 3-mask process for organic electronics, while the Structuring of both the dielectric and semiconductor layers achieved. Since production of organic electronics inexpensive deposition techniques combined with relatively expensive photolithography, the reduction is the number of masks is very important and leads to a significant Reduction of manufacturing costs.

One Advantage of the invention is that the dielectric layer directly can be deposited on the semiconductor layer before any Structuring performed becomes. This allows a very clean interface between these layers, what mobility in the semiconductor and thus improves the performance of the field effect transistor. Especially can the dielectric and the semiconductor layer immediately one behind the other and be deposited in the same environment. This ensures a significant improved integrity of the dielectric-semiconductor interface with significantly reduced dimensions of impurities.

The Structuring of the dielectric and semiconductor layer allowed Furthermore an increased mechanical flexibility and reduced mechanical stress. This allows an improved Reliability. While the known method results in a structure in which the Semiconductor layer and especially the dielectric layer at some Surfaces not exist, the method of the invention results in that the dielectric layer and the semiconductor layer are present in some areas are.

It is another advantage of the method of the invention that for the dielectric Layer a dielectric material with a relatively high dielectric constant can be used. While in the process of the prior art, the dielectric layer as a "glamor" layer and therefore as the isolation between different transistors acts has the dielectric applied as in the process of the invention Layer a function in the transistor and limited at the crossing points Area.

In a preferred embodiment The method of the invention comprises the structuring step the semiconductor layer and the dielectric layer remove the organic semiconductor layer and the dielectric layer of surfaces, not related to the at least one field effect transistor stand, and surfaces, the non-intersecting conductors of the first and second conductor layers being related.

This significantly reduces mechanical stress and increases compliance and / or flexibility the field effect transistor grouping. In particular, the semiconductor and dielectric layer of a significant portion of the total Area removed and the mechanical properties of the structure can be overwhelming be determined by the mechanical properties of the substrate. Specifically, the invention may be flexible or flexible structures or Structures with an elevated resistance allow against vibration and mechanical shocks.

It be noted that on surfaces, where the first and second conductor layers overlap, and the semiconductor layer and the dielectric layer are removed, a vertical connection is formed. These vertical links are essential to the necessary connections from and to the individual To create transistors. The vertical connections also allow to connect the drain and gate of a transistor, so that the transistor can be used as a diode, i. for one rectifying function.

In a further preferred embodiment contain the mentioned areas, which are associated with a field effect transistor, and / or the areas mentioned, which are related to intersecting ladders, protected zones, a minimum lateral distance between a first conductor in the first conductor layer and a second conductor in the second Create a ladder level.

When As a result of the method of the invention, the semiconductor layer extends to the side surfaces Semiconductor Dielectric Island. A second leader, over the Island extends, therefore, in contact with the semiconductor layer come. This can lead to a leakage current between this second conductor and a first conductor underlying the semiconductor dielectric island lies, lead. Creating protection zones increases the lateral distance between this first and this second ladder. Because the leakage current is inversely proportional to the lateral distance, is He significantly reduced by these protection zones. The protection zones generally have a length in of the order of magnitude from 0.5 to 10 microns, preferably 1-5 microns. The resulting shape the semiconductor dielectric island is then perpendicular to the substrate plane seen, oblong.

In another embodiment becomes the size of the protection zones deliberately chosen, by a resistance desired Size between to create the first and the second ladder.

In an embodiment For example, the organic semiconductor layer is a polymeric semiconductor layer. Suitable polymeric semiconductor layers include, without limitation, polyarylamines, Polyfluorenes, polythienylene vinyls, polyphenylene vinyls, polyfuranylene vinyls, polythiophenes, especially poly-3 (alkyl) thiophenes. These semiconductor materials can by desired substituted aliphatic and aromatic side groups, to improve the processing of them. In addition, the polymeric semiconductors Be networks and copolymers. These networks and copolymers may comprise groups which show no semiconductor behavior. Suitable copies are in the not previously published application WO-IB03 / 01062 (PHNL020257).

alternative For example, the organic semiconductor is an oligomeric compound such as Oligothiophene and an oligocene, in which the number of repeating units generally between 3 and 15. Thus particularly preferred is the Oligocene with 5 repeating units, in general known as pentacene. These molecules can also have desired side groups, as it is known, and can in polymeric networks and / or copolymers, such as in the above mentioned Application is described. Pentacen is special in terms of his mobility prefers. Those skilled in the art are further oligomeric and polymeric organic semiconductors known.

It will be clear that a field effect transistor in general a source and a drain electrode in the first conductor layer adjacent to the semiconductor layer and a gate electrode in the second conductor layer extending from the semiconductor layer through the dielectric Layer is separated. Above all, has a vertical projection the gate electrode on the semiconductor layer an overlap with the channel in this semiconductor layer between the source and the drain electrode. The gate may be, for example, a metal layer like gold or can be e.g. to be an organic leader.

According to one Another feature of the invention comprises the step of applying an organic semiconductor layer on the first conductor layer Applying an organic semiconductor or a precursor thereof by spin coating. This makes for a particularly simple Low cost manufacturing process. The use of a precursor molecule is in the area a well-known technique. The predecessor can after its deposition be converted into the semiconductor material.

According to one Another feature of the invention comprises the step of applying a dielectric layer on the first conductor layer the application a dielectric material by spin coating. This takes care of a particularly simple manufacturing process with low costs. Especially can the dielectric and semiconductor layers are both spin-coated in the same spin-coating device are applied, What a high integration and high purity of the interface allowed between the dielectric layer and the semiconductor layer. The Cost and complexity of the manufacturing process be kept low by only one masking step for structuring the dielectric and semiconductor layer is used after these through the low cost spin coating operation have been applied.

In in the event that a predecessor for the Semiconductor is applied, which is a conversion at elevated temperature needed This conversion can be done after applying the dielectric Layer take place. This is particularly suitable in the case in the dielectric layer also requires a heat treatment (for example after irradiation with a chemically active radiation). Then both can heat treatments be combined.

structuring a layer after the deposition of this layer generally includes the application of a mask, followed by etching. It is preferred that the step of patterning the semiconductor layer and the dielectric Layer comprises a photolithography process. This is a layer structured using a chemically active radiation, about chemical changes effect in the irradiated layer. This layer can be behind as an etching mask be used. A photolithography process is especially common Structuring of the dielectric and semiconductor layer suitable.

It is particularly preferred herein, that the dielectric layer as a photoresist layer for the lithography process acts. So no additional mask needed in the photolithography process. The dielectric layer preferably comprises a material which also acts as a photoresist. Examples of suitable Materials include HPR504 or SC100 (Olin Hunt). By using the same layer as well as a dielectric layer as well as a photoresist layer, the need for an additional Apply photoresist layer, avoided, and so can the complexity and costs of the manufacturing process are further reduced. Besides the dielectric layer preferably comprises an organic material, for an excellent flexibility to have. When a photoresist on this dielectric layer is off organic material is applied, becomes a very selective etchant needed to subsequently remove the photoresist mask, without the dielectric Negative influence on the layer.

According to one Another feature of the invention includes the method of preparation further the step of applying a protective layer. The protective layer is preferably added to the second conductor layer and can preferably materials such as polystyrene, zeonex, PMMA, polycarbonate and PVDF include. The protective layer provides additional protection of the structure and increased mechanical resistance. For one Display arrangement, the protective layer is preferably substantially transparent.

In a preferred embodiment According to the invention, the electronic device comprises a plurality of field effect transistors. Preferably, other components are also including both semiconductor components including memory units as also resistance components available. These can all be in the four-layer stack of first and second conductors, dielectric Layer and semiconductor layer are created. But in addition can more layers will be present. The manufacturing process allows so, complicated arrangements with complex functions at one low complexity and a budget Manufacture process. In particular, the arrangement be an integrated circuit.

In a further preferred embodiment is or does the electronic device comprise a display grouping. A display can thus be manufactured with a simple and inexpensive manufacturing process become. Field effect grouping (e.g., the stack of layers, in which the field effect transistors are created) is typical only part of the display. The structuring of both the dielectric as well as the semiconductor layer can for improved mechanical properties including reduced stress and increased flexibility. In particular, a flexible display can be made.

In yet another embodiment the substrate is substantially transparent. That allows one Display arrangement in which a displayed image through the substrate can be considered, and the substrate is accordingly preferred for a Image to be viewed through the substrate, sufficient transparent.

The Choice of the electro-optical layer in the display mainly determines that Functional principle of the display. A well-known electro-optical Layer is a layer of liquid crystalline material. However, it is preferred that an electrophoretic electro-optical Layer is applied. That makes for a particularly fitting, simple, low-cost method of manufacturing a display. Especially the rate at which the display has to be refreshed, is for electrophoretic displays lower than for liquid crystal displays, and so on the energy consumption is reduced. The display is in this sense very suitable for use in mobile telecommunications applications, where performance management is an absolute must. Another thing The electrophoretic display is that the display quality from viewing angles less than 90 degrees is quite good. This is important for a flexible display where the viewing angle is often uneven with respect to the display plane 90 degrees.

According to a second aspect of the invention, there is provided an electronic device comprising a plurality of field effect transistors having an organic semiconductor layer and a connection structure for connecting the transistors to each other and / or to an output terminal, the field effect transistors being arranged in a stack of: one the structured first conductor layer applied to the substrate; an organic semiconductor layer deposited on the first conductor layer; a dielectric layer deposited on the semiconductor layer; one on the dielek trical layer applied structured second conductor layer. According to the invention, the semiconductor layer and the dielectric layer are patterned according to a substantially identical pattern. As a consequence, the interface of the semiconductor and dielectric layers is very clean, thus providing improved transistor performance, especially improved carrier mobility.

In The arrangement of the invention, the semiconductor layer and the Dielectric layer, preferably of areas not with the at least a field effect transistor, and surfaces that not with intersecting conductors of the first and second conductor layers related, removed. That causes the arrangement due to the structuring of both the dielectric and the Semiconductor layer has an improved mechanical performance.

These and other aspects, features and advantages of the invention will become apparent out and explained with reference to the embodiment (s) described hereinafter.

A embodiment The invention will be described, by way of example only, with reference to the drawings described. In this show:

1 the structure of an organic semiconductor according to the prior art;

2 a flowchart of a method for producing a field effect transistor grouping according to an embodiment of the invention;

3 a cross-section of a field effect transistor structure after the application of a dielectric and semiconductor layer according to an embodiment of the invention;

4 a cross-section of a field effect transistor structure after the structuring of the dielectric and semiconductor layer according to an embodiment of the invention;

5 a cross-section of a field effect transistor structure after the application of the second conductor layer according to an embodiment of the invention;

6 a plan view of an intersection of second conductors of the different conductor layers;

7 a cross-sectional view corresponding to the top view of 6 ;

8th a plan view of a second embodiment of an intersection of two conductors of the different conductor layers; and

9 a cross-sectional view corresponding to the top view of 8th ,

2 FIG. 10 illustrates a flowchart of a method for producing an organic field effect grouping (FET) according to an embodiment of the invention. The organic field effect transistor is created on a substrate which was glass in the experiment used for testing. Typically, this substrate is attached to a carrier that provides support and mechanical stability to the FET structure. Then the support is made of glass and the substrate in this case is a polymer film, for example made of polyimide. The substrate can be released from the carrier in a suitable manner. Preferred is a method in which the substrate is attached to the carrier with a UV-releasable adhesive. Peeling is then done by irradiating the UV-releasable adhesive through the transparent support.

In step 201 In the manufacturing process, a structured first conductor layer is applied to the substrate. In the preferred embodiment, a gold layer is applied to the substrate, followed by subsequent lithographic patterning of the gold layer, as is well known in the art.

In the preferred embodiment The sources and drains of the FETs are passed through the first conductor layer formed and the structuring of the first conductor layer is so, that created at the appropriate positions source and drain electrodes become. additionally the first conductor layer creates a first connection layer to the Make the connections for the implementation of an electronic circuit required are.

In step 203 An organic semiconductor layer is deposited on the first conductor layer. In the preferred embodiment, the semiconductor layer is deposited on the first conductor layer. The deposited layer covers the substrate surface and thus is in contact with the first conductor layer and directly with the substrate where the first conductor has been removed by the patterning.

In the preferred embodiment, the organic semiconductor layer is pentacene (0.25% by weight, with 10% polystyrene added to the solution) which is preferably applied to the substrate as a precursor. The precursor used is 6,13-dihydro-6,13- (2,3,4,5-tetrachloro-2,4-cyclohexadiene) pentacene. It is applied by spin-coating on the first conductor layer. After spin coating, conversion of the precursor into pentacene is allowed to proceed for 10 seconds 200 ° C on a hot plate.

In step 205 In the manufacturing process, a dielectric layer is deposited on the semiconductor layer. The dielectric layer is preferably applied by spin coating, and preferably in the same operation as applying the semiconductor layer in step 203 , The dielectric layer in the preferred embodiment is a dielectric having suitable characteristics and may preferably be a photoresist (such as HPR504).

In the case of being a precursor the semiconductor is applied, the conversion can be in the current Semiconductors take place after the dielectric layer is deposited has been. In the case of the dielectric layer, especially a photoresist after application (and photolithographic processing) a cure needed can be the conversion of the precursor in the semiconductors and the curing the dielectric layer combined in a single treatment become. This heat treatment can heat up at different temperatures for different Include periods of time.

To the spin coating is applied to the dielectric Layer in the preferred embodiment for 30 s at 90 ° C on a hot Dried plate.

3 shows a cross section of an FET structure 300 after applying the dielectric and semiconductor layers according to an embodiment of the invention. So illustrated 3 a cross section of the FET structure after step 205 ,

As in 3 Illustrated become a source 303 and a drain 305 through the on the substrate 301 formed first conductor layer 303 . 305 educated. The semiconductor layer 307 is on the first conductor layer 303 . 305 deposited and in contact with this and with the substrate 301 , On the semiconductor layer, the dielectric layer 309 landfilled.

In step 207 Both the semiconductor layer and the dielectric layer are patterned together. Specifically, both the semiconductor and dielectric layers are patterned in a single operation or step. So the same mask is applied to both layers and the two layers finally have the same structure.

In the preferred embodiment, the patterning of the semiconductor and dielectric layers is done by a photolithography process. In the preferred embodiment, the dielectric layer is selected so that the dielectric layer also functions as a photoresist layer. For example, HPR504 can be used for the dielectric layer. In this embodiment, the structure is exposed to UV light via a contact mask and then developed and rinsed. The structuring of the dielectric and semiconductor layer is then achieved by a conventional etching process such as reactive ion etching (RIE) with, for example, Ar / O ₂ gas.

So is the structuring of the semiconductor dielectric stack for the described Arrangement extremely simple, since the dielectric material used is photosensitive and therefore acts as a resist for etching the semiconductor. This avoids the need for an additional photoresist layer the stack.

If the substrate is a polymeric film, the etching may be up expand into the substrate. There are several ways, the negative influence to limit it. Above all, you can the etching times and conditions are optimized. The properties and thicknesses the semiconductor layer and the dielectric layer are well known and so optimization is possible. Second, an etch stop layer may occur be applied to the substrate or be part of the substrate. etch stop layers are known per se. Preferably, an electrically insulating material which uses any capacitive coupling or shorts between the second conductor layer and the etching stop layer are avoided.

Particularly suitable materials for etch stop layers are particles filled with particles, especially nanoparticles. Suitable polymers include polyimide, polystyrene, polyimide, polyethylene terephthalate and so on. Suitable nanoparticles include carbon black, SiO ₂ , TiO ₂ , BaTiO ₃ , ferrites as well as other inorganic compounds and especially oxides. The nanoparticles can have a diameter of the order of 1 nm up to 500 nm. Such nanoparticle-filled polymers have the following advantageous properties: they can be used as an etch stop, the surface of the layer is relatively flat, allowing for direct deposition of the second conductor layer, the layer is flexible, and the polymer can be chosen such that the resulting layer has a thermal expansion coefficient that is comparable to the substrate and the other layers. It is a further advantage that, with an appropriate choice of particles, the resulting etch stop layer can also inhibit radiation so as to protect the organic semiconductor layer from radiation that leads to damage.

In the preferred embodiment, the organic semiconductor layer and the dielectric layer are removed from areas other than components of the field effect transistor array or intersecting conductors of the first and second conductor layers.

in the Contrary to conventional procedures is the structuring of the Semiconductor layer in the preferred embodiment with the process producing the contacts and connections in the dielectric Layer combined. This reduces the number of people through the process required masks from four to three, resulting in a significant Cost reduction of the manufacturing process results. Preferably the dielectric layer will be everywhere except at the transistor surfaces and the area the intersections between the two conductive layers removed. One additional The advantage is that it increases the mechanical flexibility of the assembly, since removing the dielectric layer the stress and consequently the chance of Cracks and movie releases reduced.

4 shows a cross section of an FET structure 300 after structuring the dielectric and semiconductor layers according to an embodiment of the invention. So illustrated 4 a cross section of the FET structure after step 207 , As in 4 can be seen are the semiconductor and dielectric layers 307 . 309 reduced to the area above the source and drain electrodes.

In step 209 a patterned second conductor layer is deposited on the patterned dielectric layer. In the preferred embodiment, the second conductor layer includes a gate of the field effect transistor. In the preferred embodiment, a patterned gold gate layer is deposited directly by evaporation through a shadow mask. But in other embodiments, a two-step process of applying a conductive layer followed by patterning may be used. In some embodiments, an organic conductor material may be used for the gate.

5 shows a cross section of the FET structure 300 after the deposition of the second conductor layer according to an embodiment of the invention. So illustrated 5 a cross section of the FET structure after step 209 ,

As in 5 can be seen is a gate electrode 501 has been applied to the dielectric layer. So a FET with a channel between a source 303 and drain 305 Electrode and an overlying gate 501 been formed. Thus, a very simple manufacturing process is achieved for an organic FET with a top-gate structure that uses only three masks while patterning both the semiconductor and dielectric layers.

FETs can be produced with a very clean integration of the semiconductor and dielectric layers, whereby high performance of the organic FET can be achieved. Experiments have shown that a mobility of 2 × 10 ^-2 cm ² / Vs can be achieved. This is comparable to or better than the conventional bottom-gate structures under the same conditions.

In the preferred embodiment the insulation layer is removed from all surfaces that are not with Components of field effect transistor grouping or intersecting Ladders of the first and second conductor layer are related. So the dielectric layer and the semiconductor layer are maintained, when connections of the two layers intersect, the required To create isolation between these.

6 shows a plan view of an intersection of two conductors of the different conductor layers. A first leader 601 the first lower conductor layer substantially intersects vertically below a second conductor 603 the upper second conductor layer. The two leaders 601 . 603 are through an area or island 605 dielectric material of the dielectric layer isolated.

7 shows a cross section of the junction of the two conductors 601 . 603 the different conductor layers. As in 7 shown, caused the island 605 dielectric material that is an island 701 of semiconductor material remains. But this semiconductor island is in contact with both conductors 601 . 603 and accordingly, a leakage current path is formed between the two conductive layers. This leakage current can be made as small as required by the proper geometry of the dielectric-semiconductor island 605 . 701 is selected. In extreme cases where the leakage current is completely removed, it could be that the spread of the island is completely below the upper conductive electrode 603 is.

8th shows schematically a plan view of a second embodiment of the intersection of the two conductors 601 . 603 the different conductive layers. 9 shows the corresponding cross-sectional view. The numerals used herein are, as far as possible, identical to those in FIG 6 and 7 , In this embodiment, the island is 605 the dielectric and semiconductor layer with respect to in 6 extended island shown. This is done to protected areas 702 to accomplish. These protection zones 702 create a minimum lateral distance between the first conductor 601 in the first conductor layer and the second conductor 603 in the second conductor layer. The guard zone is about 5.0 micrometers in this example. The width of the second conductor is about 2.0 microns. Pentacene has a conductivity of 1.3 · 10 ^-4 S / cm. That results in a resistance of about 2 x 10 ⁴ Ω. Because the voltage differences between the first conductor 601 and the second conductor 603 this is unproblematic only in short periods of substantial size.

So can according to the preferred embodiment a single organic FET through the described manufacturing process produced or an organic FET grouping with several or a variety of FETs can be made. In some embodiments becomes an integrated circuit with both semiconductor components as well as compounds required to achieve a desired functionality, produced.

In some embodiments can use the FET array in a display or electroluminescent arrangement become. Especially pixel FETs can according to the described Procedures are produced. In this case, the FET grouping preferably comprises a number of FETs in a matrix format with rows and columns are arranged. The gate of each pixel FET is preferably connected to one Row electrode connected and the source of each FET is preferably connected to a column electrode. Each individual pixel FET can then be activated and by a well-known scanning operation be provided with the appropriate charge.

For some Display applications, at least one of the substrates is transparent and preferably for an image to be seen through the layer sufficiently transparent. This allows the picture to be taken from the appropriate direction by light penetrating the appropriate layer is seen.

In the preferred embodiment for a display application The manufacturing process further includes the step of applying an electrophoretic electro-optical layer. The electrophoretic Electro-optical layer includes charged particles that depend on move the charge applied to the pixel transistor, where they while a visible color of the pixel according to the applied Generate charge.

In the preferred embodiment the manufacture further comprises the step of applying a Protective layer. For example, a protective layer of polymethyl methacrylate, Polyvinyl alcohol, polyvinylphenol, polyacrylate, polystyrene, polyvinylchloride, Polyester, polyethers, benzocyclobutene, polyimide, epoxies, glass-filled polymers or inorganic dielectrics by spin coating after application the second conductive layer or the electrophoretic layer applied become. This protective layer increases the mechanical resistance the arrangement.

The Invention may be by any suitable device and in any suitable form be implemented. The elements and components for implementation an embodiment of the invention be physical, functional and logical in every appropriate way. Really, the functionality can in a single unit, in a variety of units or be implemented as part of other units. As such, can the invention can be implemented in a single unit or can be physically and functionally distributed to different units become.

Also when the present invention in conjunction with the preferred embodiment it is not intended to be described herein limit the specific form presented. More precisely, that is Scope of the present invention only limited by the accompanying claims. In the claims includes the term does not "include" the presence other elements or steps. In addition, although listed individually, a variety of means, elements or method steps e.g. be implemented by a single unit. Although individual Features may be included in different claims, these may be additionally possibly be combined advantageously, and the leg position in different claims does not imply that a combination of properties is not feasible and / or is advantageous. additionally shut down singular covers not a variety. Thus, references to "on", "a" "first," "second," etc., do not include one Variety.

Claims (10)

Method for producing an electronic device, wherein in the method at least one field-effect transistor ( 300 ) on a substrate ( 301 ), wherein the provision of at least one field-effect transistor comprises the following steps: 201 ) a structured first conductor layer ( 303 . 305 ) on the substrate ( 301 ); - application ( 203 ) an organic semiconductor layer ( 307 ) on the first conductor layer ( 303 . 305 ); - application ( 205 ) a dielectric layer ( 309 ) on the semiconductor layer ( 307 ); - Common structuring ( 207 ) of the organic semiconductor layer ( 307 ) and the dielectric layer ( 309 ); and - application ( 209 ) a structured second conductor layer ( 501 ) on the structured dielectric layer ( 309 ). The method of claim 1, wherein the step of patterning the organic semiconductor layer ( 307 ) and the dielectric layer ( 309 ) the removal of the organic semiconductor layer ( 307 ) and the dielectric layer ( 309 ) surfaces that are not associated with the at least one field effect transistor and surfaces that are not intersecting conductors of the first and second conductor layers ( 303 . 305 . 501 ). Method according to claim 2, in which said surfaces, the associated with a field effect transistor, and / or the areas mentioned, which are related to intersecting ladders, protected zones contain a minimum lateral distance between one first conductor in the first conductor layer and a second conductor in the second ladder level. The method of claim 1, wherein the applying step ( 203 ) of an organic semiconductor layer on the first conductor layer ( 303 . 305 ) comprises applying an organic semiconductor or a precursor thereof by spin-coating. Method according to claim 1, in which the dielectric layer ( 309 ) comprises an initiator which is sensitive to chemically active radiation and, after irradiation, functions as a mask for patterning the semiconductor layer. The method of claim 4, wherein the dielectric Layer comprises a photoresist material. The method of claim 1, which includes the additional Comprises the step of applying an electro-optical layer, to create a display arrangement. Method according to claim 6, in which the substrate ( 301 ) is substantially transparent. Electronic arrangement with a multiplicity of field-effect transistors on a substrate ( 301 ) and a connection structure in order to connect the transistors to one another and / or to an output connection, wherein the field-effect transistors and at least a part of the connection structure are created in a stack comprising: - a structured first conductor layer applied to the substrate ( 303 . 305 ); - one on the first conductor layer ( 303 . 305 ) applied organic semiconductor layer ( 307 ); - one on the semiconductor layer ( 307 ) applied dielectric layer ( 309 ); - one on the dielectric layer ( 309 ) applied structured second conductor layer ( 501 ); In which the semiconductor layer ( 307 ) and the dielectric layer ( 309 ) have identical lateral dimensions. An electronic device as claimed in claim 9, in which the semiconductor layer and the dielectric layer are not on surfaces not associated with the field effect transistors and not on surfaces which are not crossed by conductors of the first and second conductor layers ( 303 . 305 . 501 ).