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DE60020742D1 - Frequenzteilung/vervielfachung mit minimierung des jitters - Google Patents

Frequenzteilung/vervielfachung mit minimierung des jitters

Info

Publication number
DE60020742D1
DE60020742D1 DE60020742T DE60020742T DE60020742D1 DE 60020742 D1 DE60020742 D1 DE 60020742D1 DE 60020742 T DE60020742 T DE 60020742T DE 60020742 T DE60020742 T DE 60020742T DE 60020742 D1 DE60020742 D1 DE 60020742D1
Authority
DE
Germany
Prior art keywords
mux
pll
multiplication
jitter
minimization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60020742T
Other languages
English (en)
Other versions
DE60020742T2 (de
DE60020742T3 (de
Inventor
Siavash Fallahi
Myles Wakayama
Pieter Vorenkamp
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=22620640&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE60020742(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Broadcom Corp filed Critical Broadcom Corp
Publication of DE60020742D1 publication Critical patent/DE60020742D1/de
Publication of DE60020742T2 publication Critical patent/DE60020742T2/de
Application granted granted Critical
Publication of DE60020742T3 publication Critical patent/DE60020742T3/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/68—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a base which is a non-integer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0996—Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
  • Dc Digital Transmission (AREA)
DE60020742T 1999-12-14 2000-12-14 Frequenzteilung/vervielfachung mit minimierung des jitters Expired - Lifetime DE60020742T3 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17062199P 1999-12-14 1999-12-14
US170621P 1999-12-14
PCT/US2000/033908 WO2001045263A1 (en) 1999-12-14 2000-12-14 Frequency division/multiplication with jitter minimization

Publications (3)

Publication Number Publication Date
DE60020742D1 true DE60020742D1 (de) 2005-07-14
DE60020742T2 DE60020742T2 (de) 2006-03-16
DE60020742T3 DE60020742T3 (de) 2009-09-17

Family

ID=22620640

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60020742T Expired - Lifetime DE60020742T3 (de) 1999-12-14 2000-12-14 Frequenzteilung/vervielfachung mit minimierung des jitters

Country Status (6)

Country Link
US (4) US6441655B1 (de)
EP (1) EP1254517B2 (de)
AT (1) ATE297607T1 (de)
AU (1) AU2100301A (de)
DE (1) DE60020742T3 (de)
WO (1) WO2001045263A1 (de)

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AU2100301A (en) * 1999-12-14 2001-06-25 Broadcom Corporation Frequency division/multiplication with jitter minimization
US6807552B2 (en) * 2000-12-20 2004-10-19 International Business Machines Corporation Programmable non-integer fractional divider
US6992792B2 (en) * 2001-06-29 2006-01-31 Electronics For Imaging, Inc. Digital pulse width modulator for use in electrostatic printing mechanisms
US7035367B2 (en) 2001-09-26 2006-04-25 Nokia Corporation Fractional multi-modulus prescaler
US6542013B1 (en) * 2002-01-02 2003-04-01 Intel Corporation Fractional divisors for multiple-phase PLL systems
FR2841405B1 (fr) * 2002-06-19 2004-08-06 Commissariat Energie Atomique Boucle a verrouillage de retard
US20040125869A1 (en) * 2002-12-31 2004-07-01 May Michael R. Method and apparatus for non-intrusive transceiver property adjustment
US7003274B1 (en) * 2003-03-05 2006-02-21 Cisco Systems Wireless Networking (Australia) Pty Limited Frequency synthesizer and synthesis method for generating a multiband local oscillator signal
US7295077B2 (en) * 2003-05-02 2007-11-13 Silicon Laboratories Inc. Multi-frequency clock synthesizer
US7288998B2 (en) * 2003-05-02 2007-10-30 Silicon Laboratories Inc. Voltage controlled clock synthesizer
US7064617B2 (en) * 2003-05-02 2006-06-20 Silicon Laboratories Inc. Method and apparatus for temperature compensation
US7436227B2 (en) * 2003-05-02 2008-10-14 Silicon Laboratories Inc. Dual loop architecture useful for a programmable clock source and clock multiplier applications
US7187241B2 (en) * 2003-05-02 2007-03-06 Silicon Laboratories Inc. Calibration of oscillator devices
US6956793B2 (en) * 2003-11-20 2005-10-18 International Business Machines Corporation Phase clock selector for generating a non-integer frequency division
CA2453292A1 (en) * 2004-01-07 2005-07-07 John W. Bogdan Noise filtering edge detectors
US7113009B2 (en) * 2004-03-24 2006-09-26 Silicon Laboratories Inc. Programmable frequency divider
US7405601B2 (en) * 2004-05-03 2008-07-29 Silicon Laboratories Inc. High-speed divider with pulse-width control
US7187216B2 (en) * 2004-05-03 2007-03-06 Silicon Laboratories Inc. Phase selectable divider circuit
US7042260B2 (en) * 2004-06-14 2006-05-09 Micron Technology, Inc. Low power and low timing jitter phase-lock loop and method
EP1624575B1 (de) * 2004-08-06 2009-01-28 Stmicroelectronics SA Frequenzsynthetiser Architektur
US20060132200A1 (en) * 2004-12-22 2006-06-22 Markus Dietl Fractional-N divider, fractional-N phase locked loop and method of dividing a frequency f of an output signal by N, wherein N is a non-integer
US20060215296A1 (en) * 2005-03-24 2006-09-28 Gennum Corporation Bidirectional referenceless communication circuit
US7873133B2 (en) * 2005-06-30 2011-01-18 Infinera Corporation Recovery of client clock without jitter
US7417565B2 (en) * 2005-09-13 2008-08-26 Research In Motion Limited Keyboard for hand-held devices
JP4745127B2 (ja) * 2006-05-23 2011-08-10 ルネサスエレクトロニクス株式会社 クロック切替回路
US7551009B2 (en) * 2007-02-28 2009-06-23 Silicon Laboratories Inc. High-speed divider with reduced power consumption
US7605665B2 (en) * 2007-05-25 2009-10-20 Broadcom Corporation Fractional-N phase locked loop
EP2238416A1 (de) 2008-02-01 2010-10-13 Stichting Voor De Technische Wetenschappen Synchrone phasenerkennungsschaltung
US8086974B2 (en) * 2008-03-31 2011-12-27 International Business Machines Corporation Structure for fractional-N phased-lock-loop (PLL) system
US7705641B2 (en) * 2008-04-23 2010-04-27 Ralink Technology Corporation Fast response phase-locked loop charge-pump driven by low voltage input
US7944257B2 (en) * 2009-05-14 2011-05-17 Ralink Technology (Singapore) Corporation Method and system of optimizing a control system using low voltage and high-speed switching
EP2288031A1 (de) * 2009-07-28 2011-02-23 Nxp B.V. Frequenzteiler
US9110875B2 (en) * 2010-02-11 2015-08-18 International Business Machines Corporation XML post-processing hardware acceleration
US8710879B2 (en) * 2012-07-06 2014-04-29 Silicon Integrated System Corp. Apparatus and method for multiplying frequency of a clock signal
JP7367616B2 (ja) * 2020-06-08 2023-10-24 株式会社デンソー 噴射制御装置
CN114726367B (zh) * 2022-06-02 2022-08-23 上海泰矽微电子有限公司 一种基于门控的低抖动时钟分频电路及控制方法

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US6181213B1 (en) * 1999-06-14 2001-01-30 Realtek Semiconductor Corp. Phase-locked loop having a multi-phase voltage controlled oscillator
AU2100301A (en) 1999-12-14 2001-06-25 Broadcom Corporation Frequency division/multiplication with jitter minimization

Also Published As

Publication number Publication date
AU2100301A (en) 2001-06-25
US20030058009A1 (en) 2003-03-27
US6930519B2 (en) 2005-08-16
EP1254517B1 (de) 2005-06-08
EP1254517A1 (de) 2002-11-06
US20020027459A1 (en) 2002-03-07
US7005899B2 (en) 2006-02-28
DE60020742T2 (de) 2006-03-16
EP1254517B2 (de) 2009-02-11
US6441655B1 (en) 2002-08-27
ATE297607T1 (de) 2005-06-15
US20040169534A1 (en) 2004-09-02
US20050140411A1 (en) 2005-06-30
US6714056B2 (en) 2004-03-30
DE60020742T3 (de) 2009-09-17
WO2001045263A1 (en) 2001-06-21

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Legal Events

Date Code Title Description
8363 Opposition against the patent
8328 Change in the person/name/address of the agent

Representative=s name: BOSCH JEHLE PATENTANWALTSGESELLSCHAFT MBH, 80639 M