DE3527112A1 - Hearing aid - Google Patents

Abstract

The invention relates to hearing aids with wireless remote control of at least some of their adjustable functions. In these devices, at least extensively reliable and interference-free transmission of the control signals from the transmitter (30) to the receiver (2) is required. For this purpose, the invention provides for the control signals to be transmitted as words comprising a bit pattern which contains coding bits, information bits and parity bits. The invention is particularly suitable for remote control of the functions of miniature hearing aids. <IMAGE>

Description

The invention relates to hearing aids according to the preamble of claim 1. Devices of this type are entwa known from DE-OS 19 38 381.

It is well known that hearing aids should be as small as possible to accommodate them to be able to wear it inconspicuously. This has led to miniature hearing aids that are worn on the head, in particular those that can be inserted into the ear canal. Also at These types of devices should at least control the volume be operationally changeable. Adjustment devices are required for this, which are accessible while that Device in contact with the wearer is in operation. also the handling area should be manageable when setting be.

This is achieved, for example, in a hearing aid device according to DE-OS 19 38 381 mentioned above. For this purpose, the components are distributed over two housings, one of which contains a transmitter that is wirelessly connected to the other, in which the actual hearing aid is located together with a receiver tuned to the transmitter. However, the volume of the housing, which contains both the hearing aid and the receiver, offers very little volume. In particular, the so-called "in-the-ear devices" that are worn in the ear canal only have a few 100 m ^{3 of} free space for the installation of a remote control receiver. For this it is desirable to get by with a receiver which, in contrast to the known solution, does not require an additional sensor, antenna or the like.

According to our earlier registration P 35 31 584.5, a Hearing aid with remote control proposed in which as a receiving element for the control signals The hearing aid microphone is used with and that as Medium for transmitting the control signals such energy is used that the microphone of the hearing aid in electrical Can convert signals that are separated from the rest of the signals be brought into effect on control organs. To transmit the control signals is in one preferred embodiment of inaudible sound, in particular Ultrasound, is used. The latter is said to be in one Control device can be generated in the case of a keyboard the control signals are generated and via a loudspeaker are delivered and the derivation in the hearing aid device The signals picked up by the microphone are split into two branches is, of which one in the hearing aid and the other via all signals except the ultrasonic signals, blocking filter to the control part of the hearing aid device leads.

The invention has set itself the task for a Hearing aid of the type mentioned at the outset a remote control indicate with which a more secure and as far as possible trouble-free operation of the device can be achieved. According to the invention, this object is achieved by the characteristics of claim 1 specified measures solved. The subjects of the subclaims are advantageous Further training.

The invention is based on the assumption that remote control of the following functions in particular is desirable in hearing aids:
Changes in volume,
two switching functions,
Mono and stereo operation,
Fixed addresses for the assignment of remote control commands.

In this context, the following scope of commands results for mono operation:
- Volume up
- Quieter
- Switching function 1 (e.g. microphone / telephone switching)
- Switching function 2 (e.g. high-pass switching)

The following range of commands results for stereo operation:
- Louder left
- Louder to the right
- Quieter left
- Quieter on the right
- Loud on both sides
- Quieter on both sides
- Switching function 1 on both sides
- Switching function 2 on both sides

The commands may only be sent by the hearing aid being addressed are processed.

In the case of switching functions, per control is in mono operation one word and stereo mode two words are sent. The left and once the right hearing aid is addressed.

When the volume changes, words become so long sent out as the corresponding control is maintained is. In stereo mode, the Volume change alternately the left and the right hearing aid addressed. This creates a uniform Change in volume of both hearing aids achieved. The volume changes when activated on both sides half as fast as with one-sided control.

For transmission, it has proven to be useful to define the commands in individual words. The words are pulse-length modulated. The combination of a word from 6 bits results in sufficient possibilities and also provides a secure command transmission with the necessary economical effort. The individual bits have the following meaning:
Bit 0: address bit 0; Addressing of the left (bit 0 = 0) or right (bit 0 = 1) hearing aid in stereo mode
Bit 1: address bit 1
Bit 2: address bit 2
Bit 3: data bit 0
Bit 4: data bit 1
Bit 5: parity bit

The address bits address the receiver belonging to the sender. A receiver only processes a word if the address bits set on the receiver (bits 0, 1 and 2) match the ones received. Bit 0 is used to address the left or right hearing aid in stereo mode. In this remote control operating mode, address bits 1 and 2 must be set the same on both receivers. 8 addresses can be defined per remote control unit in mono operation and 4 addresses in stereo operation. This ensures that two hearing aids operated spatially next to one another do not necessarily interfere with one another. Experience has shown that 8 hearing aid addresses are sufficient for practical use. The data bits (bits 3 and 4) carry the useful information. It is coded as follows:

This protocol enables the functions described above realize.

Bit 5 serves as a parity bit and increases reliability the transfer procedure. The parity bit is depending on the logical values of the address and data bits, so generated by the sender that there is an odd Parity results. This ensures that each Word, due to the pulse length modulation, short and contains long pulses. A periodic interfering signal with the characteristics of the transmission protocol cannot cause a malfunction.

The individual bits encoded by pulse length modulation. The logical zero is through a short impulse, the logical one through represented a long pulse. Form six impulses one word at a time.

The signal forms can be clearly described by five times, the transmission parameters:
T 0 : short pulse duration (logical 0)
T 1 : long pulse duration (logical 1)
TB : time frame for one bit
TW : Timeframe for a word
TF : period of a carrier frequency oscillation

The signal form shown here corresponds to switching function 1 in stereo mode with address bits A 1 = 1 and A 2 = 0. A pause can be seen between two impulses. The pause is used to process the information and for the recipient to reliably recognize a new word.

The time frame of a word determines the frequency of the Volume changes. It is therefore useful to give each individual pulse no matter if short or long, a fixed time frame assign. This results in one of the set Address bit independent change frequency. in the Stereo operation is the frequency of change for bilateral Volume changes half as high as with one-sided Volume change, as left or right alternately Hearing aid is addressed.

With the "hard sampling" of the carrier frequency used here, which can be in the order of magnitude f _TF = 25 kHz when using ultrasound as a carrier, relatively wide sidebands arise to the left and right of the carrier frequency, which decay according to the sin (x ) / x function . With a bit frame length of 20 ms, a basic frequency of 50 Hz results. This means that maxima are formed in the frequency range at a 50 Hz distance from one another, to the left and right of the carrier frequency. Because of the low data transmission rate, the required frequency band is sufficiently narrow despite the binary modulation.

Further details and advantages of the invention are provided below on the basis of the exemplary embodiments shown in the figures explained.

In Fig. 1, a hearing aid constructed according to the invention is shown schematically,

in FIG. 2 the schematic block diagram of a transmitter to be used to control the device according to FIG. 1,

in Fig. 3 a tolerance scheme for bit recognition,

in Fig. 4 is a block diagram of a receiver used to control the device according to Fig. 1,

in Fig. 5 the state diagram of the receiver,

in Fig. 6 a timing diagram for pulse shaper and

in FIG. 7 is a timing diagram for synchronous monoflop.

In Fig. 1, a hearing aid device is drawn, which comprises a hearing device part 1 and a receiver 2 of the remote control part. The hearing aid part 1 begins in the usual way with the input transducers, ie a microphone 3 and an induction pickup coil 4 , which can be alternately connected to the hearing aid circuit by means of a toggle switch 5. The signal recorded in 3 and / or 4 then passes via an adjustable amplifier 6 , which serves as a presetting for the amplification, via a sound screen 7 to a potentiometer 8 , from which it then passes to a driver stage including output stage amplifier 10 . Finally, the amplified signal is converted back into sound in an end transmitter 11 , ie a listener, which can be fed to the ear of the hearing impaired. The receiver 2 of the remote control of the device has a connection 12 to the microphone 3 . Control takes place from the receiver 2 via connections 13, 14, 15 and 16 to the switch 5 , to the sound screen 7 and to the potentiometer 8 .

The transmitter 30 provided for the control 20 of the hearing aid and shown in FIG. 2 is divided into seven functional blocks:
Control 20
Shift register 21
Input interface 22
Encoder 23
Address and Parity Encoder 24
Pulse generator 25
Amplifier 26

The control commands are entered by means of function keys 19 or keys 19.1 on the transmitter 30 . The input interface 22 reads the respective keystroke TIn, stores it and locks all other function keys. By means of the signals T 1 to T 12 , it forwards the command that has been read to the encoder 23 and to the controller 20 . The START signal tells the controller 20 that a key press has been accepted.

If no more buttons 29 or 19.1 are pressed, the START signal is inactive. The control 20 then brings the started word to the end, so that a complete command is sent and then unlocks the input interface 22 by END. This will delete the stored key press in the input interface and a new command can be received.

The keystrokes are saved in order to convert the command into a correctly coded signal even if the corresponding key 19 or 19.1 is released during the transmission time. The two data bits (B 3 and B 4 ) are generated in the encoder 23 from the commands that have been read. With function keys 19 or 19.1 , which correspond to the mono operating mode, the address bit A 0 (bit B 0 ) is also generated from the stored key press Tn. In stereo mode, the controller 20 sets the address signal STAO alternately to logic zero and one. The encoder 23 recognizes this operating mode through the signal SM (stereo / mono) and in this case encodes the signal STAO coming from the controller 20.

The address and parity encoder 24 adds the address bits A 1 and A 2 and the parity bit to the bits B 0 , B 3 and B 4 already generated. The parity bit is set depending on the switch position in such a way that the set, ie even (even) or odd (odd), parity results. At the output of the address and parity encoder 24 , the data word has already been completely generated. It is applied in parallel and must be converted into a signal that corresponds to the transmission protocol. For this purpose, the function of the controller 20 will first be described.

A pressed function key 19 or 19.1 signals the input interface 22 to the controller 20 by pressing START. The controller 20 classifies the command according to the signal sequence to be transmitted:
- Mono operation, switching function, send out a word
- Mono operation, volume change, transmission as long as the button is pressed
- Stereo operation, switching function, send out two words
- Stereo operation, volume change, transmission as long as the button is pressed

Before each signal sent, the controller 20 resets the shift register 21 with the RESR signal (reset shift register) and then starts it with STSR (start shift register 21 ). This process is repeated periodically for the corresponding commands and each time initiates the output of a word. The transmission frequency of the words is thus determined by the clock generator TW of the controller 20 .

The shift register 21 is initialized in such a way that the first shift register cell is set and all other cells are reset. With the signal STSR, the set one passes through the shift register at the frequency of the clock generator TB . In doing so, zeros are always reloaded into the first cell. The shift register BV 0 to BV 5 (bit valid) set in each case indicates to the pulse generator 25 which bit is to be converted into a pulse. The clock generator TB of the shift register 21 thus specifies the time frame for one bit.

The pulse generator 25 links the outputs BV 0 to BV 5 of the shift register 21 with the signals B 0 to B 5 and uses them to obtain the trigger pulses for the two monostable multivibrators T 0 and T 1 . In the case of a logic zero, a monoflop T 0 (short pulse) is triggered, and in the case of a one, a monoflop T 1 (long pulse). RC elements on the monoflops determine the pulse lengths.

By linking the two monoflops, the pulse generator 25 gains the signal shape in the baseband. The carrier frequency generator TF is thus activated and emits the required, modulated signal form at its output. This signal SIG controls the following amplifier stage 26 with square-wave pulses. The amplifier stage works in the overdrive range (switching mode).

The transducer can be controlled with a square wave signal because it is a resonance oscillator and thus acts as a bandpass filter. The harmonics present in the control signal are filtered out by this property of the ultrasonic transmitter 27.

The transmitter 30 can for the most part be constructed from SSI standard CMOS modules of the 4000 series. Some passive and active components complete the circuit. The CMOS components can be found on a circuit board in double European format. The RC elements for setting the transmission parameters and the amplifier stage are located on an additional circuit board. The transmitter can be supplied with a 9V block battery. The current consumption is 0.5 mA in standby and 10 mA in transmit mode.

The digital part consists of combinational circuits and asynchronous switching mechanisms. The individual functional units work completely asynchronously with one another because a time-determining element is assigned to each switching mechanism. The pulse lengths are determined by adjustable monoflops. Due to the asynchronous design with the distributed clock generators, the transmission parameters T 0 , T 1 , TB , TW and TF can be set independently of one another.

The receiver 2 is to receive and decode signals. This assumes that the receiver 2 can reliably differentiate between valid and invalid signals. Interfering noises as well as disturbed, weak or noisy signals must not cause any malfunction of the hearing aid. On the other hand, the reception method should tolerate interference in the signal such as occur in normal use. E.g. echoes caused by objects in the vicinity.

The reception method should not require a fixed frequency relationship between the transmitted signal and the clock of the receiver, so that no synchronization is necessary. As a result, the clock can be generated in the receiver 2 with relatively large tolerances on the receiver chip or can be derived from a simple, external RC element. The receiver 2 is designed so that the circuit can be integrated as far as possible on a chip. This chip can also contain the electronic potentiometer 8. If many functions of the receiver are implemented digitally, the power consumption can be reduced considerably if no signal is received (standby mode). In addition, digital circuits can be integrated particularly easily.

The microphone voltage is present at the input of receiver 2. It represents the sound waves in the transmission range of the microphone 2 . This voltage must be amplified and the frequency components in the audio frequency range must be filtered out in order to generate control signals. The signal is then digitized. This results in individual pulses, each of which corresponds to an oscillation of the modulation frequency.

This gives packets of modulation pulses which, depending on their number, correspond to either a long or a short pulse in the baseband. The individual pulses of these packets are therefore counted and the length of a binary pulse (coded bit) is obtained. The receiver 2 can now distinguish between a logical 0 and 1 or cannot assign a logical value to the received signal. In the latter case, an interference signal can be detected, which causes the receiver to abort signal detection. Otherwise, the bit recognized and found to be good is saved.

In Fig. 3:
n : number of modulation pulses
a : lower pulse limit
b : boundary between logical 0 and 1
c : impulse upper limit

The tolerance scheme shown in FIG. 3 shows three limits a , b and c . If a signal or pulse packet 32 has fewer than a single pulses, it is recognized as too short. A pulse packet 33 which contains more than c individual pulses is also recognized as an invalid signal. On the other hand, if more than a and less than c modulation oscillations can be counted for a binary pulse as in packets 34 and 35 , it is assumed to be a valid binary pulse. At the boundary b , a distinction is then made between the logical zero indicated by 34 and the logical one indicated by 35.

However, it is not enough to just count the modulation oscillations. Rather, the receiver 2 must also recognize the beginning and end of a pulse packet.

After the receiver 2 has recognized the end of a pulse and has assigned a logical value to the pulse, it waits for a period of time in which echoes can occur. This suppresses possible echoes. Only when the waiting time (echo lock), in which echoes can occur, has expired, the receiver 2 is ready to receive the next binary pulse.

This process is repeated until all six bits of a word have been read. Then the address bits of the word read in are compared with the address set on receiver 2 and the parity is checked. If the receiver 2 recognizes the read-in word, the useful information is decoded and the hearing aid is activated. Then the receiver 2 returns to its initial state and waits for the next data word.

Because modulation oscillations of the signal are counted and the length of a binary pulse does not need to be compared with a time generated in the receiver 2 , the receiver clock frequency can fluctuate over a very large range. Since the carrier frequency signal is analyzed directly by counting the modulation pulses, demodulation can be dispensed with.

All signals that occur in the block diagram of FIG. 4 of the receiver 2 and connect the individual function blocks with one another are listed in alphabetical order below and their function is briefly explained.

A 1 , A 2 : Fixed addresses of recipient 2 (address bits 1, 2 ). They can be set on a chip by wiring with V _DD or V _SS or using fuseable links.

BC: output of the bit counter 55 (B it ounter c). This signal goes high when the bit counter 55 is at six. It indicates to the control unit 43 that all bits of a word have been read.

B 0 to B 5. The B its 0 to 5 illustrate the content of the shift register 48 is was a received word completely read, they represent the information content.

CEN: C lock en able activates the clock generator 52 when SIN is present or the monoflop 46 is triggered.

CK1 ... CK4: Preparatory inputs for the JK flip-flops in CJ1 ... CJ4 work register 54 . The control unit combination 53 links the data relevant to the sequence control and sends the result to the preparatory inputs of the flip-flops.

CQ1 ... CQ4: Q outputs of the flip-flops in control unit register 54 ( C ontrol- Q output 1 ... 4 ).

CS0 to CS 15: C ontrol s tate 0 ... 15 ); decoded control unit state; these signals represent the logic state of the control unit 43 . They control the individual function blocks and thus control the functional sequence in the digital part 41 .

DIN: D ata In put; Result of the demodulation of a binary pulse. This bit is read in by the shift register 48; provided that a logical value could be assigned to the pulse.

DS, DSI: D ata S Trobe, D ata S Trobe I nverted; Flag signal for sequence control.

D 0 to D 3 : D atabit 0 to D atabit 3 ; decoded data bits of a command that has been read. They are valid in connection with the data strobe signal STB. As output signals from the receiver 2, they control the hearing aid.

FS: False signal indicates to the control unit 43 that a status of the modulation counter 47 was not recognized as a valid bit. This signal is always active when the counter is too high or too low.

LR: Fixed address (left / right, address bit 0) of receiver 2 forms with A 1 and A 2 the complete address of receiver 2 .

MPIN: modulation pulse input; per modulation oscillation, a pulse is generated synchronous to the clock of the receiver 2 with the length of one clock period. These pulses increment the modulation counter 47 .

SC: Signal Count is always activated when a Ultrasonic signal is received. With this Signal is the beginning and end of a binary Impulse detected. It determines by that the period in which modulation pulses for a binary pulse can be counted.

SIN: Signal In is the binary signal from the analog part 40 and represents the input signal for the digital part 41. The length of the pulses depends on the amplitude and frequency of the received signal.

SM: Set Monoflop 46 sets the monoflop with every input pulse (SIN).

STB: The strobe declares data bits D 0 to D 3 at the output of receiver 2 to be valid.

TD, TDI: Time Delay, Time Delay inverted is a flag signal for the sequence control and indicates to the control unit 43 that the echo lock has been carried out.

T 0 to T 3 : The outputs T 0 to T 3 of the timer 56 inform the control unit 43 about the expiry of times (e.g. duration of the echo lock).

WOK: Word ok reports to control unit 43 that a received word is valid. The address of the command read in corresponds to that of receiver 2 and the data word has an odd parity.

The recipient is divided into three functional groups:
- Analog part 40
- Digital part 41 with function switching unit 42 and control unit 43

The analog part 40 amplifies signals recorded in a microphone 3 and filters out the audio frequency components of the spectrum. The remaining signal escapes from the ultrasonic control signal received by the microphone 3 and is converted by a Schmitt trigger 44 into a binary, anisochronous signal SIN. For each modulation oscillation, a digital pulse is created, the length of which depends on the amplitude and frequency of the received signal, if the gain and trigger threshold are assumed to be constant. The analog part 40 works completely independently of the digital part 41 and controls it with the signal SIN.

The digital part 41 is divided into two functional groups:
The function switching unit 42 processes the signal SIN and thus evaluates and processes the received signal.
- The control unit 43 specifies the temporal and functional sequence of the signal detection.

The functional switching mechanism 42 has six functional blocks:
- pulse shaper 45
- monoflop 46
- Modulation counter 47
- shift register 48
- Address and parity comparator 49
- data decoder 50

The pulse shaper 45 generates clock-synchronous individual pulses with the length of one period from the signal SIN. These pulses MPIN one of the modulation counter 47th In addition, the pulse shaper 45 generates the signal SM for triggering the monoflop 46 . As will be shown in detail later, the pulse shaper 45 operates as a monoflop stage.

The monoflop 46 recognizes the beginning and end of the pulse packets (binary pulses). It is designed as a synchronous switching mechanism and can be retriggered. The first modulation pulse of a pulse packet loads the monoflop 46 and all subsequent pulses retrigger it. The output signal CS shows the control that a pulse packet is present and therefore modulation pulses must be counted. The pulse width of the monoflop 46 is greater than the period of the carrier frequency signal. This ensures that a pulse packet is recognized as a whole even if some modulation oscillations are canceled out by interference, for example. If the monoflop 46 falls back into the stable state because no signals arrive during its pulse width, the end of a pulse packet is recognized (CS = 0).

In addition, the monoflop 46 activates the system clock with the signal CEN. The clock generator of the digital part 41 consisting of 42 and 43 is namely stopped when a command has been completely evaluated and no further signal is received. This considerably reduces the power consumption in standby with the CMOS circuit technology used. In standby practically only the analog part 40 consumes power. As already mentioned, the modulation counter 47 counts the individual oscillations of a binary pulse. If the counting process is ended, then the modulation counter 47 delivers two signals: SF shows the control that the received burst could not be identified (SF = 1) or that the count represents a valid binary pulse. In the latter case, the DIN signal is valid. The modulation counter 47 is reset by the control unit states CS1 and CS9 and counts the pulses MPIN in the state CS2.

The bits (signal DIN) recognized by the modulation counter 47 are read into the shift register 48. With each read-in bit, the entire content of the shift register 48 is shifted by one place. After all bits of a data word have been processed, the shift register 48 represents its information content. The shift register 48 is reset in the state CS1 and clocked with CS3.

The address and parity comparator 49 checks the entire contents of the shift register 48 for odd parity and compares the received address ( B 0 to B 2 ) with the address set on the receiver. If both tests are positive, the WOK signal is activated.

The control unit 43 also consists of six function blocks:
- flags 51
Clock generator 52
- Control unit combinations 53
- Control unit register 54
- bit counter 55
- timer 56

The flags 51 are used for the correct processing of the control unit sequences. They are set and reset by the control unit register 54 and read out by the control unit combinatorics 53.

The clock generator 52 generates the system clock of the receiver 2 . The receiver 2 is constructed as a synchronous switching mechanism, so that all signal and state changes in the digital part 41 take place synchronously with this clock.

The control unit combinatorics 53 processes all signals necessary for the functional sequence of the receiver. These can be generated by the function switching unit, represent states of the control unit 53 or be signals from other function blocks of the control unit 3 . The control unit combinatorics 3 supplies the preparation inputs of the flip-flops in the control unit register 54 .

The control unit register 54 stores the current operating state in which the receiver 2 is located. The state is represented encoded by the signals CQ1 to CQ4 and decoded by the signals CS0 to CS15.

The bit counter 55 counts the pulse packets recognized as correct per word. It is reset in parallel with the shift register 48 (CS1) and it is incremented when a bit is loaded into the shift register 48. If the bit counter 55 has been incremented six times, which means that a word has been completely read in, the signal BC is activated.

The timer 56 generates times for the correct timing of the signal detection. It is managed by the control unit register 54 and forwards its output signals to the control unit combinatorics 53 .

The analog part 40 amplifies and filters the microphone signal and digitizes the signal obtained by a Schmitt trigger 44 into the anisochronous output signal SIN. The analog part 40 is composed of several filter stages 65, 66 and 67 as well as amplifier stages 68 and 69 . The three filter stages 65 to 67 are dimensioned so that they together form a Chebyshev high-pass filter of the fifth order with 3 dB ripple in the pass band. As a rule, only high-pass filtering is necessary, since the microphone 4 used in small hearing aids already acts as a low-pass filter. The first filter stage 65 of this high-pass filter is a first-order filter and prevents a first amplifier stage 68 from being overdriven by high amplitudes of low-frequency signals. The first amplifier stage 68 amplifies the filtered signal by a constant 32 dB in order to provide the following filter stages 65 to 67 with a sufficient signal amplitude.

The two following filter stages 65 to 67 are designed as active RC filters with an internal gain of zero.

The gain of the second amplifier stage 69 can be set between 21 dB and 35 dB. As a result, the optimal gain for controlling the Schmitt trigger 44 can be determined experimentally.

The cut trigger 44 works with fixed switch-on and switch-off levels and supplies the output signal SIN.

The signal SIN generated by the analog part 40 is processed by the digital part 41. The digital part 41 thus directly analyzes the modulated signal, so that demodulation in the conventional sense can be dispensed with. The digital part 41 must recognize whether a received signal corresponds to a transmitted signal sequence and, if necessary, controls the hearing aid.

The state diagram of the receiver 2 shown in FIG. 5 serves as the basis for designing the control unit combinatorics 53 . With state diagrams, synchronous processes, and thus also synchronous switching mechanisms, can be modeled very well. Since it reflects the temporal and functional sequence of signal detection, the state diagram should be described separately. This also makes the interaction of the individual function blocks 45 to 54 with one another transparent and the signal detection is made more concrete.

After applying the supply voltage, the power-on reset brings the receiver 2 into the CS0 state. Receiver 2 is now in standby and waits for an input signal SIN. The system clock of receiver 2 is switched off. In this state, the digital part 41 consumes practically no power when using CMOS technology. If no ultrasonic signal is received, which is the case for most of the operating time, only the analog part 40 consumes a significant amount of power. If an input signal SIN is present, the monoflop 46 activates the clock generator 52 and brings the receiver to the state CS1 with the signal SC. This state resets the modulation counter 47 and bit counter 55 as well as the two flags 51 DS and TD. The receiver 2 is thus prepared for the evaluation of a data word. The control unit 43 now switches to CS2. In this state, modulation pulses are counted as long as the monoflop 46 is switched on (SC = 1).

If the monoflop 46 falls back, then the receiver 2 jumps, depending on the status of the modulation counter 47 , to the state CS3 or CS4. If the status of the modulation counter 47 can be assigned a logical value (FS = 0), CS 3 is selected. For the state CS3, the recognized data bit is shifted into the shift register 48 and the bit counter 55 is incremented. The control unit 43 then switches to the state CS4.

If, on the other hand, a signal that is too short or too long was received (FS = 1), the system goes directly to CS4. Since a wrong signal was received, the receiver 2 cancels the signal detection. After CS4, where the timer 56 is reset, the control unit 43 goes into the state CS7 (FS = 1). Here the time T 2 is awaited and the receiver 2 then goes to CS0 and tries to recognize a data word with the next signal.

If, on the other hand, a bit could be identified, reception is continued. As long as not all six bits of a data word have been read (BC = 0), the reception of the next bit is prepared. For this purpose, the delay time T 0 is awaited in the state CS5, during which echoes from the received signal are to be expected. This time delay thus acts as an echo blocker. The TD flag is set in the CS5 state. After the echo lock has expired, the control unit 43 returns to CS4, where the timer 56 is reset again. Since the TD flag is now set (TD FS BC = 1), the control unit 43 switches to the CS6 state. Here the receiver 2 waits for the time T 1 in which it expects a further binary pulse of the transmission signal.

If no SIN signal arrives during time T 1 , receiver 2 cancels signal detection and returns to standby (CS0).

If, on the other hand, a new signal SIN arrives during the waiting time T 1 , the control unit 43 , activated by SC, switches to CS9. In CS9, the modulation counter 47 and the TD flag are reset. The receiver 2 is thus prepared for the decoding of a further bit and the control unit 43 jumps to the state CS2. The receiver 2 now analyzes a binary pulse again, as described above. This process is repeated until all six bits of a data word have been read.

If the word has been read in completely, the control unit 43 is in CS4 and the bit counter 55 has reached its maximum value (signal BC = 1). Depending on the result of the address and parity comparison in 49 , the status CS7 or CS8 is now started. If the result of the comparison is negative, a jump is made directly to CS7. After the delay time T 2 , the receiver 2 then returns to standby.

If, on the other hand, WOK is high, the received data is transferred to the hearing aid in the loop via state CS8. The duration of the handover is determined by T 3 . In state CS8, the flag DS is set and the control unit 43 goes to CS4 after the transfer time T 3 has elapsed. When the flag DS is set, BC · DS becomes true and the receiver 2 is again in standby at CS0 after the delay time T 2 (CS7). This completes the reception of a data word.

The system clock is now switched off and the receiver 2 waits for a new input signal.

The function switching mechanism 42 consists of the six function blocks:
- pulse shaper 45
- monoflop 46
- Modulation counter 47
- shift register 48
- Address and parity comparator 49
- data decoder 50

The pulse shaper 45 converts the anisochronous modulation pulses SIN from the Schmitt trigger 44 into two signals:
- An isochronous single pulse with the length of one clock period is generated for each modulation pulse. These pulses MPIN are counted by the modulation counter 47.
The modulation pulses are lengthened by the pulse shaper 45 by at least one clock period. This signal SM triggers the monoflop.

The pulse shaper 45 works independently of the control unit 43 . Its flip-flops are reset by the power-on reset (RESET) and clocked by the system clock CLK. The pulse shaper 45 is only controlled by SIN and processes all individual pulses equally regardless of their length. Very short impulses are also recorded. Flip-flop 1 is set asynchronously by SIN and remains high as long as SIN is present. If SIN is low, then a zero is reloaded into flip-flop 1 with the next clock edge. With long input pulses, flip-flop 2 remains high; short pulses make it high. In the following clock period, the AND link for MPIN is true and the isochronous single pulse is generated. During this time, however, no further SIN may be received. The OR link SM is always high when at least one flip-flop is set. This means that the input pulses are lengthened by one to two clock periods.

The monoflop 46 reports the beginning and the end of pulse packets to the controller by means of the signal SC. It activates the system clock with the CEN signal.

The monoflop 46 works like the pulse shaper 45 independently of the control unit 43 and is triggered by the signal SM. The monoflop 46 is reset with the power-on-rest (RESET).

The OR link between SIN and SC ensures that the system clock is independent of the length and temporal position of the input pulse SIN is safely started.

This synchronous, retriggerable monoflop 46 was developed from a shift register circuit. The individual flip-flops are set in parallel by the signal SM via the OR gate and retriggered in the same way. As described in the previous section for the pulse shaper 45 , the input pulses SM are always longer than one clock period, so that the signal SM can always be loaded into the monoflop 46 with the rising edge of the clock CLK. If the signal SM is low over a number of clock periods, the shift register 44 is emptied by one memory cell from left to right with each rising clock edge. The switch-on duration after which the monoflop 46 drops out can be set between 3 and 7 clock periods using the coding switch DILS.

The function of the monoflop 46 is also shown in the timing diagram in FIG. This representation clearly shows the adjustable switch-on duration and the effect of signal pauses on the output signal. The switch-on duration of the monostable multivibrator 46 can be set so that up to two missing modulation oscillations of a pulse packet are bridged. The optimal switch-on time of the monoflop can thus be determined. This synchronous monoflop 46 could also be a counter circuit. In the transmitter 30 , however, a decoder would then be required to set the switch-on time and the circuit would not be as transparent as the shift register variant used.

The modulation counter 47 counts the pulses MPIN, each of which represents a modulation oscillation. Based on the counting result, it differentiates between valid and invalid binary pulses and the logical zero and one. The modulation counter 47 is reset by RESET, CS1 and CS9 and is prepared for the counting of modulation oscillations of a binary pulse with each reset.

The modulation counter 47 is divided into two sub-circuits:
- Counter 47.1
- Decoder 47.2

The counter 47.1 consists of three partial counters connected in series. The first partial counter counts the pulses MPIN and the following partial counters count the overflow of the previous one. Each partial counter counts up to 2 ⁴ -1, so that the modulation counter 47 can count up to 2 ^{12 -1 in total.} The counter counts in state CS2 and is clocked by the system clock CLK.

All partial counters have the same structure. Just the last one Level has no overflow logic. The partial counters are as synchronous counters with JK flip-flops known as T flip-flops are connected. The preparatory inputs of a flip-flop go high when all of the previous ones Flip-flop outputs and the input of the partial counter are high. The corresponding flip-flop then flips with the next rising clock edge. The overflow of a partial counter goes high when all flip-flop outputs of the Partial counter and the input signal are high. With the next rising edge of CLK will all flip-flops of the partial counter low and the following partial counter counts the carryover. The carry is made by an AND link, to which the De Morgan theorem applied once was realized.

The second sub-circuit of the modulation counter 47 , the decoder 47.2 , decodes the count. This is necessary to determine the length of the received pulse packet.

The outputs of the flip-flops can be switched to any of the three AND gates of the decoder 47.2 . This means that the limits for signal detection can be changed as required. The RS flip-flops register a count that has passed through.

An integrated circuit can be provided, which decodes the lower limit of a valid binary pulse and one for the upper limit. The OR Linking the two associated flip-flops results the signal FS (false signal). FS indicates that the received Pulse packet is either too short or too long. The output of another flip-flop (signal DIN) decides whether the received pulse packet is a zero or a one is assigned. The signal DIN is only then evaluated if FS = 0 applies (see status diagram). The The counter reading does not have to be completely decoded, because repeated triggering of an RS flip-flop changes its state no longer changed.

In the configuration drawn in the circuit diagram all pulse packets with less than 63 modulation oscillations than too short and all impulse packages with more than 312 Modulation waves classified as too long. All binary pulses between 63 and 187 modulation oscillations are considered logical zero and all binary pulses between 188 and 312 modulation oscillations are recognized as logical one.

The shift register 48 serves as a buffer store for the bits that have been read.

It is reset by the power-on reset (RESET) or by CS1. The bit (signal DIN) recognized by the modulation counter 47 is read into the shift register 48 with the positive edge of CS3. The entire content of the shift register 48 is shifted one place to the left due to the synchronous clock edge. If the receiver 2 has read a bit into the shift register 48 six times in succession, the information content of a data word is stored.

The address and parity comparator 49 and the data decoder 50 read out the shift register 48 in parallel (signals B 0 to B 5 ).

The address and parity comparator 49 compares the address set on the receiver 2 with that of the received data word. The logical connection to this is: This equation can be converted by applying the De Morgan theorem: The parity check is carried out by EXORing all outputs B 0 to B 5 of the shift register 48 . The following link applies to the parity comparison:

Y _P = B 0 ⊕ B 1 ⊕ B 2 ⊕ B 3 ⊕ B 4 ⊕ B 5 ⊕

Y _p becomes one for odd parity and zero for even parity. The order (brackets) in which the individual links are carried out is irrelevant. The AND operation of Y _A and Y _p supplies the output signal WOK of the address and parity comparator 49 .

The data decoder 50 decodes the data bits B 3 and B 4 of the shift register 48 . The following logical links are to be carried out:

D 0 = UDF <4,, 100.5.1 ° KB ° k4 =
D 1 = B 3 * =
D 2 = · B 4 =
D 3 = B 3 · B 4 = the data decoder 50 forwards the result of the link to the hearing aid. The decoded data are only valid in connection with the data strobe STB. The signal STB is the control unit state CS8, in which the data transfer is carried out. The control unit 43 realizes the temporal and functional sequence of the signal recognition, as specified by the state diagram. The following function blocks are available for this purpose:
Clock generator 52
- flags 51
- bit counter 55
- timer 56
- Control unit combinations 53
Control unit register 54 The clock generator 52 generates the system clock for the receiver. The two output signals CLK are identical. An inverter supplies the function switching unit 42 and another inverter supplies the control unit 43 with the clock CLK. The digital part 41 of the receiver 2 is completely constructed as a synchronous switching unit, so that all changes in signal states occur synchronously with the rising edge of CLK. The pulse shaper 45 and monoflop 46 function blocks controlled by the SIN signal are an exception. These assemblies synchronize the input signal SIN. The clock generator 52 consists of an enable logic and a multivibrator. The enable logic is an OR link between the undecoded control unit states CQ1 to CQ4 and the clock enable signal CEN. If there is no input signal (CEN = 0) and the receiver is in standby (CS = 0), the OR link is not fulfilled. The multivibrator has stopped because the NAND link cannot be fulfilled by a gate provided for it. If a signal is received, CEN becomes high and the clock generator 52 can start. As a result of the further processing of SIN, control unit 43 switches to state CS1 with the next rising clock edge. The clock generator 52 now remains active until the control unit state is CS0 again and no signal SIN is present. The clock generator 52 thus runs until the signal detection is complete and the receiver 2 is again in standby. The system clock is therefore switched off in standby and the power consumption is greatly reduced when using CMOS circuit technology. The multivibrator consists of two inverter circuits that are fed back via an RC element. This RC element is located between two gate outputs, which are always in the opposite state. The capacitor is stored up to half the operating voltage. Then the first gate moves to the bend in its transfer characteristic and controls the second gate. This control creates a positive feedback. Both gates change their state, the capacitor is charged in the other direction and the process is repeated. The characteristic frequency of the multivibrator results in f _CLK = (2.2 · R · C ) ^-1 . The flags 51 enable the correct processing of sequences of the control unit in which a state is assigned several times. The time delay flag TD is responsible for the loop of the echo suppressor CS4-CS5-CS4-CS6. If TD is reset, the receiver jumps from CS4 to CS5 if UDF <4,, 100,5,1 FS applies. After the TD flag has been set in CS5, the receiver controls from CS4 to CS5. The TD flag is reset by RESET, CS1 and CS9. With the aid of the data strobe flag DS, the loop CS4-CS8-CS4-CS7 can be run through for data transfer. After a data word has been received completely and correctly, BC · WOK ·· DSI applies and the control unit changes from CS4 to CS8. The flag is set in CS8 and after the data transfer time T 3 the control unit jumps from CS4 to CS7. The valid data was then transferred to the hearing aid. The DS flag is reset by RESET and in CS1. The bit counter 55 counts the bits of a received data word. Since a data word is six bits long, the output signal BC is high when the bit counter 55 is at six. The bit counter 55 is then incremented when the receiver 2 has recognized a valid bit. It thus counts the passes from state CS3 in which a data bit is loaded into shift register 48. The bit counter is clocked with CLK. It is reset by RESET or by CS1. The bit counter 55 is constructed as a dual counter from JK flip-flops which are connected as T flip-flops. A flip-flop always flips when all previous flip-flops and the input signal CS3 are high. The outputs of second higher-order flip-flops "2 ² " and "2 ¹ " deliver the output signal BC through the AND operation. The timer 56 generates four times for the sequence control of the Signal detection. These four different times are:
- T 0 : echo lock in CS5
- T 1 : waiting time in CS6
- T 2 : delay time in CS7
- T 3 : Data transfer time in CS8 The timer 56 consists of a counter 56.1 and a decoder 56.2 . The timer 56 counts the clock pulses CLK in the states CS5, CS6, CS7 and CS8 until the corresponding count is reached. The times generated by the timer 56 are therefore derived from the system clock CLK. The timer 56 is reset by the power-on reset (RESET) or by CS4. The counter 56.1 consists of three partial counters constructed as dual counters. Since it is constructed in the same way as the counter of the modulation counter 47 , its function need not be explained any more. The decoder 56.2 differs from that of the modulation counter 47, however . For each time interval T 0 to T 3 , an AND gate links any counter reading with four inputs. The counter reading does not have to be saved because the control unit 43 changes its state immediately after the time limit has been reached. Since the system clock, derived from a simple RC element, is subject to large tolerances, decoding with four flip-flop outputs can be regarded as sufficiently accurate. In the circuit diagram and with a clock frequency f _CLK = 80 kHz, the following times result:
- T 0 = 5 ms
- T 1 = 25.6 ms
- T 2 = 16.8 ms
- T 3 = 16.8 ms The control unit combinatorics 53 links the signals from the block diagram to control the control unit register 54 . For this purpose, four flip-flops are provided, which are controlled by signals CJ and CK. The control unit 43 can possibly get into an undefined state due to spikes or malfunctions. In order to avoid deadlocks when the control unit 43 is in an undefined state, the combinatorial system 53 is reset for all undefined states in the last flip-flop. As a result, the control unit 43 returns to one of the defined states CS2 to CS7. The control unit register 54 stores the control unit status and thus the operating status of the receiver. The control unit register 54 outputs the state encoded by the signals CQ1 to CQ4 and decoded by the signals CS0 to CS15. The control unit 43 consists of four clocked JK flip-flops and a 1 out of 16 decoder. The flip-flops are reset by the power-on reset (RESET). This means that the receiver is in standby (CS0) after the supply voltage is applied. The flip-flops are clocked by the system clock CLK. The preparation inputs of the flip-flops are controlled by the signals from the control unit combination 53 . The control is designed in such a way that edge-controlled RS flip-flops can also be used instead of the FK flip-flops. The decoder is always enabled. By wiring the decoder, the flip-flops are assigned the following value:
FF1 = 2 ⁰ ; FF2 = 2 ¹ ; FF3 = 2 ² ; FF4 = 2 ³ This allows the signals CQ1 to CQ4 to be converted into the control unit states CS0 to CS15. The digital part 41 described as an example is designed in such a way that integration is possible. In order to achieve this, the design rules for semi-custom ICs must be applied. In addition, the digital part 41 is completely constructed as a synchronous switching mechanism, with no component-specific properties, such as gate delay times, having to be used. This makes the behavior of the circuit largely independent of the technology used. The use of SSI modules makes the application sufficiently transparent so that the functions used can easily be replaced by cells from a cell catalog for integrated circuits.

Claims (11)

1. Hearing aid with wireless remote control of at least parts of its controllable functions, both the elements of the hearing aid as well as those for controlling its functions and a receiver for signals for remote control of these functions are housed in a portable on the head housing, characterized in that the signals Words are made up of a bit pattern containing coding bits, information bits and parity bits. 2. Hearing aid device according to claim 1, characterized in that that every word has three coding Bits, two information bits and one parity bit. 3. Hearing aid device according to claim 1, characterized in that that the identifier is different Bits is caused by pulse width modulation. 4. Hearing aid device according to claim 2, characterized in that that to transfer the bits short and long pulse packets are provided, respectively contain a certain number of individual pulses. 5. Hearing aid device according to claim 4, characterized in that that for receiving the carrier pulses digital monoflops are provided. 6. Hearing aid according to claim 2, characterized in that that for the transmission of the Pulse packages are provided for the same time periods, regardless of whether the packets are short or long (fixed time frame). 7. Hearing aid device according to claim 2, characterized in that that after finishing a Bits to the duration of the period in which echoes are expected the recording of signals is blocked. 8. Hearing aid device according to claim 2, characterized in that that the receiver only has pulse packets assumes that longer than a minimum time and shorter than are a maximum time. 9. Hearing aid device according to claim 8, characterized in that that the arythmetic means between the maximum time and the minimum time the end of the bit for the logical zero from the beginning of the bit for the logical one separates. 10. Hearing aid according to claim 9, characterized in that when using a carrier frequency of 25 kHz the short pulse packets between 63 and 187 contain modulation waves, while the long packages between 188 and 312 modulation oscillations include. 11. Hearing aid according to claim 10, characterized characterized in that the medium is for transmission the control signals is ultrasound and that that Receiving element for the control signals, the microphone of the Hearing aid is.