DE3430185A1 - Method and device for generating a digital signal - Google Patents

Abstract

A circuit which generates a digital signal (S1, S2 or S3) which is cyclic and has accurate timing over a long period of time is needed especially in medical ultrasonics. As a rule, the digital signal changes only at a few times within the cycle time (T). A method is specified in an illustrative embodiment, in which the times within a cycle (T) in which a change in the digital signal is desired are written into a memory section (13a). The desired change in the digital signal is written into another memory section (13b). By means of a time comparison between the time written in and the status of a current clock time counter (21), it is determined whether the output signal (S1, S2, S3) is to be changed. The advantage of the method is that the storage space requirement is much lower than if the associated digital signal value had to be stored for each clock time. <IMAGE>

Description

Method and device for generating a digital

Signals The invention relates to a method for programmable Generation of a periodically repeating digital signal, in particular for Use in medical ultrasound technology. The invention also relates to a device for carrying out the method.

In signal processing in a digital system or in the Controlling a digital circuit is often faced with the task of a to generate a digital signal cyclically over a large period of time, this Signal within the cycle with exact timing, e.g.

must be synchronous with a clock signal with a high clock frequency and wherein this signal usually changes only rarely within the cycle time. Occasionally There is also the task of sending two or more such signals that are time-synchronized a single clock signal to provide. This can also be Problem arise, instead of a digital signal, a corresponding analog time-dependent signal To generate a function with a specified cycle time. Such a time-dependent function is, for example, the control signal for the individual transducer elements of an ultrasonic array, which is used for image display in the medical field.

A previously used standard solution for generating a time-dependent Function consists of an address counter and a signal memory controlled by this.

The clock signal is present at the input of the address counter and the output of the address counter is connected to the input of the Signal memory connected, wherein the signal memory is the desired digital output signal or a code gives for it. For each clock cycle there is a memory location in the signal memory in a predetermined manner assigned whose information (value 0 or 1) the desired state of the signal at relevant clock included within the cycle.

The disadvantage of this standard solution is that it takes up storage space with the length of the cycle time and the number within the cycle time of clock pulses ("fine subdivision") increases. The state RAM may be to be dimensioned very large, although the information content contained in it is relative is low. In other words, with time-dependent signals that have a long period (Cycle time) and / or have a fine subdivision, is until now a signal memory high capacity has been required. If, for example, the cycle time is 1 ms and the clock frequency 1 MHz, the signal memory should be able to contain 1000 signal bits. Here can It may be possible that the desired signal only has relevant information in two places exists, i.e. if the signal changes from 0 to 1 only once within the cycle time and then jumps back from 1 to 0. Are e.g. three signals with two relevant each To generate information at the same time, the signal memory would have to be 3 x 1000 = 3000 Signal bits can contain relevant information, although only in a total of 6 places are present.

With a variety of signals, such as those used in medical Ultrasound technology is required, so the standard solution can lead to a high storage requirement to lead.

From an economic point of view, the storage space requirement is unfavorable Relation to the desired information.

A data processing device for medical ultrasound diagnosis is known, for example, from U.S. Patent 4,356,731.

The object of the invention is therefore to provide a method and a device to carry out this, in which the storage space requirement is significantly reduced is.

This object is achieved in that the in the Data written into memory contains the points in time during the course of a period the change in the desired signal or those lying in the course of a period Time spans between two successive changes to the desired signal and the values or changes assigned to the points in time or the time periods of the desired signal.

According to a first development it is provided that the point in time a change in the desired digital signal over the period of the signal is written into the digital memory as a program that also the dem Change of the desired digital signal assigned to the time or the value itself is written into the memory that then successively a comparison between the respective count of a continuously clocked cycle time counter the times written in the memory is carried out, and that at each Agreement a change of an output signal takes place, which thereby the desired digital signal.

According to a second development it is provided that the successive Time span between two successive changes to the desired digital Signal is written into a digital memory as a program that also the change in the desired digital signal associated with the respective time period or the value itself is written into the memory that afterwards by a continuously clocked cycle counter each time the period is measured is, and that after this period of time a change in an output signal takes place, which thereby corresponds to the desired signal.

A device for carrying out the method according to the first development is characterized by the fact that a comparator, an address counter, the memory and the cycle counters are operatively linked to each other.

An apparatus for carrying out the method according to the second Further development is characterized in that a differential time counter with the memory and an address counter is operatively connected.

The advantage of the method mentioned is that in each case only the value or change of the signal and the time of this change or the Period of time between changes are inscribed. In the memory there are assigned to each point in time or each time span, either the new signal in each case after this point in time or after the expiry of the period or the difference between the new and the old signal. So it does not have to be for every measure within the Cycle memory locations are occupied, but only if with the respective cycle also a change in the signal is associated. So the space requirement is here closely linked to the amount of relevant information in the digital signal. With little The information content of the signal is reduced with this method, the memory expenditure considerably. In addition, the signal can easily be shifted within the cycle time. For this purpose, only the point in time or the period of time needs to be changed.

The described method can therefore be used with particular advantage the generation of a signal with time insert critical edges, little information is available per cycle time.

Further refinements and advantages of the invention emerge from the drawings in conjunction with the subclaims. They show: Fig. 1 the typical Temporal progression of a number of desired digital signals, FIG. 2 a Table assigned to the signals, FIG. 3 shows the principle diagram of a known standard solution for generating a periodic signal, FIG. 4 shows the basic circuit diagram of a preferred one first embodiment of the method according to the invention and FIG. 5 shows the basic circuit diagram a second preferred embodiment of the method according to the invention.

Figure 1 shows three periodic digital signal curves S1, 52, S3, as they are typical in one of the digital systems considered here. E.g. the signal curve S1 for an ultrasonic array with 40 ultrasonic transducers or Transducer antennas 40 times with a time delay in a medical examination device Image display. The signal curve S1 contains only two relevant ones Information within a period or cycle time T. The signal jumps S1 once from 0 to 1 or from L to H and a few bars later back from 1 to 0 or from H to L. The same applies to signal curve 52. This is where the relevant information, however, later. The waveform 53 also has only two relevant pieces of information: it is this is the jump from 1 to 0 after approx. 1/4 of the cycle time T and the jump back from 0 to 1 after approx. 2/3 the cycle time T. The cycle time T is the time after which the Repeat signal curves S1, S2, 53. For example, it can be used in the field of ultrasound Have a value of about 1 ms. The cycle time T is a clock signal C, whose Clock frequency could then be around 1 MHz in the example. This is in the last timing diagram of Fig. 1 indicated by 1024 small square pulses. Compared to the other charts the last time diagram in Figure 1 is thus shown spread.

The penultimate diagram of Fig. 1 contains the time course of the individual Information expressed by the assigned measure number within the cycle time T.

The table of FIG. 2 shows the information content of the signal profiles S1, S2, S3 again depending on the time t, which is indicated here by the cycle number is expressed within the cycle time T is shown. It is e.g.

It can be seen that the signal S1 is within the clock pulses 50 to 98 H-signal, the signal S2 is an L-signal and the signal S3 is an H-signal. With certain Applications, the signal S1 is not a total of (98-50) = 48 clocks, but E.g. only 1, 2 or 3 bars long. For the sake of clarity, but the much higher value of 48 clocks in FIGS. 1 and 2 was chosen.

These signal profiles S1, S2, S3 can be seen in FIG. 2 as a result words 101, 001, 000, 001, 011 and 001.

Figure 3 shows a previous standard solution with which the signal curves S1, S2, S3 from Figure 1 can be realized. A clock 7 works to an address counter 9 with (according to the example of Fig. 1 e.g.

1024) Addresses that are incremented by 1 with each cycle of the clock signal C will. On the output side, the address counter 9 is connected to a signal memory 11, in which for each address (from 0 to 1023) the associated values of the signal curves S1, S2, S3 are stored. The storage option is indicated by an arrow 12. The desired signal sequence S1, S2, S3 on. With the mentioned cycle time of 1 ms and a clock rate of 1 MHz, the Signal memory 11 accordingly for the 3 signals S1, S2, S3 3 x 1024 = 3072 signal bits can contain, i.e. one signal bit per cycle for the signal course S1, 52 and S3. So this means 3072 required storage spaces, although a total of seen only at six relevant points (bars 50, 98, 250, 650, 900, 948) information is available. With extensive signal processing or signal generation systems the amount of memory required is so large compared to the information it contains that the The profitability of this standard solution is in question.

In Fig. 4, the reference numeral 13 denotes a signal memory, which is divided into two partial memories 13a and 13b. In the first partial memory 13a all times within a period or cycle time T are written, in which there is a change in the signal curves S1, S2, S3. Im drawn Example according to Figure 1 are six points in time, namely at clocks 50, 98, 250, 650, 900 and 948. In the second partial memory 13b are the times which are written in the partial memory 13a, associated signal values of the signal curves S1, S2, S3 inscribed. In the example in FIG. 1, this would be at the time of the cycle 50 the signal sequence 101, at the cycle time 98 the signal sequence 001, at the cycle time 250 the signal sequence 000, at the cycle time 650 the signal sequence 001, at the cycle time 900 the signal sequence 011 and at clock time 948 the signal sequence 001. These signal values are numbered from 1 to 6 in the last column of FIG. The memory overhead of the signal memory 13 thus amounts to 3 x 1 bit for each signal change three signals S1, 52, S3 plus 10 bits for writing in the time of the signal change into the partial memory 13a. So this is 13 bits per signal change. When shown Example with six signal changes result in 78-bit.

On the other hand, there is the significantly higher memory requirement of 3072 bit according to the known standard solution according to FIG. 3.

The output of the partial memory 13a is connected to the first input 15 of a digital comparator 17 placed. To the second input 19 of the comparator 17 a cycle time counter 21 is connected. The cycle time counter 21 is from the clock 7 receives the clock signal C and counts one cycle from 0 to 1023, then switches to 0 and starts counting a cycle from 0 to 1023 again. Of the Comparator 17 compares the current count (value 0 to 1023) of the cycle time counter 21 with the time pending at its first input 15, expressed by one of the desired cycle times 50, 98, 250, 650, 900 and 948. Are both correct Values match, an enable signal 23 is sent to both a register 25 and given to an address counter 27.

In principle, the register 25 can be dispensed with if the Signals of the partial memories 13a and 13b offset from one another by one memory location are stored. The signals S1, S2, S3 would then be at the output of the partial memory 13b tapped directly.

The address counter 27 is connected to the signal memory 13. When counting on The signal memory 13 places the information of the next address by one address to its outputs. So are at the two outputs of the partial memory 13a, 13b both the clock time of the next change in a signal and that after this next change required signal. As soon as the release signal 23 on the register 25 acts, the register 25 opens its input 29 and lets the signal data from The output of the partial memory 13b enters the register 25. At output 31 of the register 25 thus results in the signal sequence S1, S2, S3, as it is the desired signal sequence was written into the signal memory 13 as a program.

With this method, not only can the storage space requirements be considerable be lowered, but it is also possible to easily set a predetermined one To shift the signal in time. This happens, for example, simply by the fact that the time the signal change in the partial memory 13a is changed. To shift the time sequence a programming input 33 is provided, for example connected to a microprocessor (not shown) connected is. Another programming input is used to change the shape of the curve 35 is provided on the partial memory 13b, which is also under the control of a microprocessor can stand. The signal memory 13 can in particular be a RAM.

FIG. 5 shows a variant in which there is also a reduction the storage space requirement. The signal memory 13 again consists of two partial memories 13a, 13b. In the partial memory 13a as desired values inscribed the periods of time between between two signal changes lie. Using the example of FIG. 1, this would be the cycle time spans (98-50) = 48 Bars, 152 bars, 400 bars, 350 bars, 48 bars and 126 bars.

The signals are written into the partial memory 13b as desired values, how they should be in the respective time span. The output of the partial memory 13a is connected to the input 41 of a time difference counter 43. The difference time counter 43 takes over the value of the period of time that is present at its input 41, if a Release signal 53 is present. A release signal 53 is always present when the difference time counter 43 assumes the value zero. The difference time counter 43 is designed so that it counts down by 1 with every measure. So he counts them the period of time written in by the partial memory 13a gradually to the value zero and, like the comparator 15 in FIG. 4, fulfills a comparison function. Then the release signal 53 occurs, which in turn is sent to the address counter 27 and acts on register 25. The address counter 27 counts when the enable signal is present 53 by one address, whereby at the outputs of the partial memories 13a and 13b the next time span and the associated signal value are applied.

The register 25 takes over when activated by the release signal 53 the signal value already present at its input 29. The one already attached The signal value is that value when the previous release signal appeared 53 was applied to the output of the partial memory 13b. At the output of register 25 the signal curves S1, S2, S3 result simultaneously.

This variant also has the advantage that the storage space requirement is low. Here, too, a predetermined signal S1, S2 or S3 can be generated in a simple manner be shifted within the clock cycle T. Leave programming inputs 33 and 35 Here too, free programming of the desired signal curves is possible.

It should also be mentioned that the register 25 is a digital-to-analog converter (not shown) can be connected downstream if the signal curves S1, S2, S3 together as a sequence of binary words, each composed of three binary digits (e.g. 101 001, 000, 001, etc. according to Fig. 2). Also should be highlighted be that, for example, the signal S1 can be used to generate a transmit pulse generator to trigger that control one or more ultrasonic elements. The signal S1 can also, after the required amplification, directly control the ultrasonic element be used. It is also possible to use one of the signals S1, S2, S3 or a combination these signals S1, S2, S3 to control other functions of an ultrasound device to be used, e.g. to control the image memory, to adjust the receiving focus, Etc.

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Claims (9)

Claims P A method for the programmable generation of a self periodically repeating digital signal (S1, S2 or S3), especially for use in medical ultrasound technology, whereby the desired signal is appropriate Data that are written as a program in a digital memory (13) for Formation of the periodically repeating digital signal are used, d a d u r c h e k e n n n z e i c h n e t that the written into the memory (13) Data a) the points in time of the change in the course of a period (T) desired signal or the time spans in the course of a period (T) between two successive changes to the desired signal and b) the values or changes of the desired signal. 2. The method according to claim 1, d a d u r c h g e -k e n n z e i c h n e t that the point in time of a change in the desired digital signal in the course of the period (T) of the signal is written in the digital memory (13) as a program is that also the change associated with the point in time of the desired digital Signal or the value itself is written into the memory (13) that afterwards successively a comparison between the respective counter reading of a continuous clocked cycle time counter (21) with the in memory (13) enrolled Times is carried out, and that with each match a change is made Output signal, which is then converted to the desired digital signal (S1, S2 or S3) corresponds to (Fig. 4). 3. The method of claim 1, d a d u r c h g e -k e n n z e i c h n e t that successive time span between two successive changes the desired digital signal in a digital memory (13) as a program is written that also the change associated with the respective time period of the desired digital signal or the value itself is written into the memory (13) is that then by a continuously clocked clock counter (43) each the Period of time is measured, and that after this period of time there is a change in a Output signal takes place, which thereby corresponds to the desired signal (S1, S2, S3) (Fig. 5). 4. The method according to claim 2, d a d u r c h g e -k e n n z e i c h n e t that the correspondence between the current count and the stored one Time there is a numerical correspondence between the counter reading and the numerical one specified value of the point in time. 5. The method of claim 3, d a d u r c h g e -k e n n z e i c h n e t that the period of time after counting down the clock counter (41) at the value Zero is given where the clock counter (43) generates an enable signal (53). 6. Apparatus for performing the method according to claim 2, d a u r c h g e k e n n n z e i c h n e t that a comparator (15), an address counter (27), the memory (13) and the cycle time counter (21) are operatively connected to one another are (Fig. 4). 7. Apparatus for performing the method according to claim 3, d a d u r c h g e k e n n z e i c h -n e t that a difference time counter (43) with the memory (13) and an address counter (27) is operatively connected (Fig. 5). 8. Apparatus according to claim 5, 6 or 7, d a d u r c h g e k e n It should be noted that the memory (13) is a RAM. 9. The method according to claim 2 or 3, d a d u r.c h g e k e n n z e i c h n e t that the cycle time counter (21) can be reset periodically (FIG. 4).