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DE3485705D1 - GRAPHIC VIDEO DISPLAY SYSTEM WITH LARGE RESOLUTION. - Google Patents

GRAPHIC VIDEO DISPLAY SYSTEM WITH LARGE RESOLUTION.

Info

Publication number
DE3485705D1
DE3485705D1 DE8484307409T DE3485705T DE3485705D1 DE 3485705 D1 DE3485705 D1 DE 3485705D1 DE 8484307409 T DE8484307409 T DE 8484307409T DE 3485705 T DE3485705 T DE 3485705T DE 3485705 D1 DE3485705 D1 DE 3485705D1
Authority
DE
Germany
Prior art keywords
video
memory
addresses
bus
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484307409T
Other languages
German (de)
Inventor
Paul Schreiber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AST Research Inc
Original Assignee
Tandy Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tandy Corp filed Critical Tandy Corp
Application granted granted Critical
Publication of DE3485705D1 publication Critical patent/DE3485705D1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G09G5/06—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using colour palettes, e.g. look-up tables

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
  • Transforming Electric Information Into Light Information (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

A high resolution video graphics system for use with a processor and characterized by improved memory expandability particularly in connection with color display. The high resolution video graphics system includes a video memory which is preferably comprised of a plurality of video memory planes and video counter means for providing display timing. There are basically four buses that are used with the system including a control bus, a read bus, a write bus, and an address bus. A multiplexer means is provided for receiving either video counter addresses or direct addresses from the processor. There is associated with the video memory means for converting to serial output data which the preferred embodiment includes a series of shift registers corresponding to the number of separate memory planes employed. In the preferred embodiment the system has three memory planes, each of 16K by 16 capacity. The shift register output is coupled to a high speed static palette RAM with the shift register outputs being the addresses thereto. The data outputs of the palette RAM couple to guns on a color monitor or to the back plane in connection with black and white graphics.
DE8484307409T 1983-11-29 1984-10-26 GRAPHIC VIDEO DISPLAY SYSTEM WITH LARGE RESOLUTION. Expired - Lifetime DE3485705D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US55617883A 1983-11-29 1983-11-29

Publications (1)

Publication Number Publication Date
DE3485705D1 true DE3485705D1 (en) 1992-06-11

Family

ID=24220224

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484307409T Expired - Lifetime DE3485705D1 (en) 1983-11-29 1984-10-26 GRAPHIC VIDEO DISPLAY SYSTEM WITH LARGE RESOLUTION.

Country Status (5)

Country Link
EP (1) EP0148564B1 (en)
AT (1) ATE75872T1 (en)
AU (1) AU3475184A (en)
CA (1) CA1237207A (en)
DE (1) DE3485705D1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4771275A (en) * 1983-11-16 1988-09-13 Eugene Sanders Method and apparatus for assigning color values to bit map memory display locations
JP2526857B2 (en) * 1984-12-27 1996-08-21 ソニー株式会社 Image signal conversion method
EP0221926B1 (en) * 1985-04-12 1991-10-23 Ampex Corporation A recirculating special effects video framestore
US4783652A (en) * 1986-08-25 1988-11-08 International Business Machines Corporation Raster display controller with variable spatial resolution and pixel data depth
AU602213B2 (en) * 1987-05-28 1990-10-04 Digital Equipment Corporation Computer work station including video update arrangement
US4851826A (en) * 1987-05-29 1989-07-25 Commodore Business Machines, Inc. Computer video demultiplexer
US5091721A (en) * 1988-12-22 1992-02-25 Hughes Aircraft Company Acoustic display generator

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS559742B2 (en) * 1974-06-20 1980-03-12
US4092728A (en) * 1976-11-29 1978-05-30 Rca Corporation Parallel access memory system
US4342029A (en) * 1979-01-31 1982-07-27 Grumman Aerospace Corporation Color graphics display terminal
FR2463555A1 (en) * 1979-08-14 1981-02-20 Option Sa Digital graphic information display using telephone line - uses memory storing full TV screen image with access inhibited during sweep portion to enable display
JPS5716487A (en) * 1980-04-11 1982-01-27 Ampex Computer graphic system
GB2090506B (en) * 1980-11-12 1984-07-18 British Broadcasting Corp Video colour graphics apparatus
GB2112256B (en) * 1981-11-18 1985-11-06 Texas Instruments Ltd Memory apparatus
GB2116004A (en) * 1982-01-13 1983-09-14 Europ Systems Improvements in or relating to video display systems
JPS5960488A (en) * 1982-09-29 1984-04-06 フアナツク株式会社 Data writing unit for color graphic memory

Also Published As

Publication number Publication date
AU3475184A (en) 1985-06-06
EP0148564B1 (en) 1992-05-06
CA1237207A (en) 1988-05-24
ATE75872T1 (en) 1992-05-15
EP0148564A3 (en) 1988-02-10
EP0148564A2 (en) 1985-07-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: AST RESEARCH, INC., IRVINE, CALIF., US

8328 Change in the person/name/address of the agent

Free format text: TAUCHNER, P., DIPL.-CHEM. DR.RER.NAT. HEUNEMANN, D., DIPL.-PHYS. DR.RER.NAT. RAUH, P., DIPL.-CHEM. DR.RER.NAT. HERMANN, G., DIPL.-PHYS. DR.RER.NAT. SCHMIDT, J., DIPL.-ING. JAENICHEN, H., DIPL.-BIOL. DR.RER.NAT. VON UEXKUELL-GUELDENBAND-MENZEL, A., DR.PHIL. (PH.D.) WEINBERGER, R., DIPL.-CHEM.UNIV. DR.RER.NAT. BUBLAK, W., DIPL.-CHEM. UNIV., PAT.-ANWAELTE TREMMEL, H., RECHTSANW., 81675 MUENCHEN

8339 Ceased/non-payment of the annual fee