DE3228518A1 - Circuit arrangement for preparing PCM systems for switching purposes - Google Patents

Abstract

Using very fast ECL logic chips, switching networks with a simple structure can be built up even for large time-division multiplex exchanges. To be able to connect PCM systems of any and different order to such switching networks with a high multiplexing factor and to be able to use this both in synchronous and in plesiochronous networks, the PCM systems must be prepared. For this purpose, a circuit arrangement (Figure 2) is used which has units containing for each incoming PCM system a register for S/P conversion, devices for clock recovery and for synchronisation signal detection, a time slot counter and buffer for content and address of a time slot, and a control system. A common priority control determines which time slot is to be selected from which incoming PCM system and is to be forwarded to the switching network. <IMAGE>

Description

Circuit arrangement for processing PCM systems

for the purpose of switching. The invention relates to a circuit arrangement for processing any PCM systems, especially different ones Order for the purpose of mediation in space and time levels of a coupling network high degree of multiplex.

Coupling networks can be created with very fast ECL logic modules simple structure also for large time division multiplex exchanges. Such Coupling networks work at bit rates of up to 280 Mbit / s with a multiplex factor of up to 4352 (time steps for 4352 time slots), have a low number of steps (e.g. three-stage) and can have over 16,000 connections simultaneously with combined switching ". This corresponds to an offer of around 16 kErl for a relative load of 95%, with the supply skew approx. 20% and the inner Blocking is about 0.1 z. An expansion in the switching network of 4224/4160 = 1.015 can be achieved by removing those not needed within the exchange PCM synchronization time slots (64) also used for switching through voice channels will.

An important aspect with exchanges is the degree of attainable Modularity, i.e. the possibility of adapting the degree of expansion to the intended use, both during commissioning and when expansions are required later.

The ideal case is that the bundles are in different directions are calculated according to traffic theory rules and the coupling network for the corresponding Number of lines is dimensioned or expanded. The same applies to connection new subscriber groups at local exchanges. In PCM technology, this is the case Ideally, however, not achievable as the smallest bundle unit with the PCM 32 system to 30 voice channels = lines is specified. An even further coarsening the "expansion grid" must be avoided for economic reasons, i. H. a bundle with 150 lines is made up of either five PCM 32 systems or made up of a PCM 132 and a PCM 32 system, under no circumstances from two PCMs 132 systems, only a quarter of which is used.

The object of the invention is based on future PCM systems for the purpose of switching to such coupling networks so that - PCM systems of any, different order - on Roppel networks of any degree of multiplexing are to be connected and - the coupling network in both synchronous and plesiochronous Nets is to be used.

According to the invention, a circuit arrangement with the characterizing features of claim 1 proposed.

Preferred embodiments of the invention are defined by the claims 2 to 9 marked. These and some backgrounds of the invention are presented below closer purifies.

The basic idea behind this system is as follows: The The frame structure of PCM systems is only required to display the time slot numbers during certain times (e.g.

the transfer) not to have to provide. This structure is a kind of 11 syntax "which allows the amount of information to be transmitted (time slot content and time slot number) to almost half (time slot content and some sync words including the frame sync word). The disadvantage that all time slots must be in a strictly ordered sequence is on transmission links irrelevant, since there is no access to the individual time slots. In the coupling network however, there is access to each individual time slot for the purpose of mediation from any PCM system. For this purpose, all framework structures are completely dissolved and time slots mixed from different PCM systems. Only be at the output of the coupling network resulting in new PCM systems with a fixed frame structure.

It is therefore superfluous for everyone to be frame-synchronic before the switching network PCM systems, as they are resolved immediately afterwards. Instead of this the information contained in the "SyntaxX" (= time location number) is to be recovered and to be explicitly stated and made available for the mediation.

The time slot number is displayed together with the associated time slot content mediated by the coupling network, or

is there as setting information for the crosspoints and memory cells, which the time slot content runs through, available and is used for calling this setting information. At the output of the switching network there is a time slot in the Usually a new address, since the content of the time slot is conveyed in terms of time and space will. The time slots leave the coupling network in the correct order and frame structure for further transmission.

The complete dissolution of the frame structure of the PCM systems brings on Coupling networks with a multiplex factor higher than 32 have another advantage: they can now the time slots from several PCM systems, also of different order, combined become groups whose number of time slots is less than or equal to the multiplex factor of the Coupling network is. About the uniqueness of all time slot numbers within a group To ensure that all time slot numbers can be specific to each PCM system Base number can be added. When connecting an additional PCM system in the group the newly added time slots are then given a number that is derived from their Time slot number in the PCM system and the base number = number of those previously connected Time places composed. The time switch memory of this group is to expand the number of cells that corresponds to the number of newly added time slots. In the case of larger expansions, a new group must be created.

The solution according to the invention and its preferred embodiments still offer the advantage of using coupling networks of the type mentioned at the beginning in plesiochronous To be able to use networks that no additional transmission errors arise except for those that are inevitable due to plesiochronism. For this it is necessary Time slots from PCM systems whose transmission currently advise is high, to be given preferential treatment when passing it on to the switching network. on the other hand time slots from PCM systems whose transmission rate is currently lower must Give priority to time slots from faster PCM systems. Leave that way Fluctuations in the transmission rates in the PCM system group are largely on average compensate, which is why only a very small buffer memory is required for each PCM system is where time slots can wait to be passed on.

In the drawing are schematically to further explain the invention and their embodiments, the following details are shown: In FIG. 1: a diagram for group formation from PCM systems; Fig. 2: a block diagram for a circuit arrangement for processing PCM systems for switching purposes (if the units same for incoming PCM systems, only one unit is shown); Fig. 3: the state graphs ZG 1, ZG 2 and ZG 3 of a control of a unit according to FIG. 4: a switching mechanism for the state graph ZG 1; Fig. 5: a switching mechanism for the state graph ZG 2; 6: a switchgear for the status graph ZG 3; Fig. 7: a circuit for the priority control; 8: a circuit for a priority encoder PE and FIG. 9: a diagram for the division of a walking group in PCM systems.

Fig. 1 shows an example of a coupling network with a Multiplex factor 4352 and a working frequency of 280 Mbit / s, in which way PCM systems are grouped together. There should be 3 PCM systems - a PCM 132, a PCM 537 and a PCM 2176 - can be combined to form the HW k group. Since the multiplex factor of the switching network is 4352, the group is 2845 connected time slots not fully developed. High-speed systems like the PCM 2176, deliver far more often than other systems with lower transfer rates their time slots to the coupling network. The time slots of the incoming PCM systems can forwarded to the switching network according to their arrival and the bit rate of their systems will. Instead of the arrival, the fill level of the input buffer can also be used will.

There may be gaps in the combined time slot stream if there is no time slot to be forwarded at the moment. You let yourself go by a nonexistent Mark the time slot number for the inserters in the coupling network.

From Fig. 2, the block diagram, the following can be seen: The Time slots of a group of PCM systems PS are serialized on a data bus 280 Mbit / s to the coupling network KN. They are in register 1 ZP, an S / P converter, received and can be passed on from there to the first stage of the switching network will. In parallel, the internal Time slot numbers (ZPI, ZP number + base number), also called ZP addresses, are also available serial with 280 Mbit / s, but in two parts (bits 1-8 and bits 9-13, bits 14-16 without Meaning) to the coupling network KN. Bit-parallel transmission at 35 Mbit / s is in principle possible, but requires many cables.

The equipment used for processing for a PCM system PS are only shown for one of these systems. In addition, there is the common priority control indicated, which determines the collection order of the time slots of a group. the Devices for a PCM system unit consist of those for clock recovery and synchronous detection (start of frame) for the PCM system in question, two in parallel working buffers for ZP content and ZP address, the register 1ZP for S / P conversion and a ZP counter, as well as the controller, the various reading and reading cycles and generates signals for mode switching of the registers in the buffers it reports readout requests ANr and additional requests ZA to the priority control.

An incoming time is read serially into the first S / P register. The recovered clock is divided by eight at a time for 8-bit PCM words.

After reading in, the ZPI counter is incremented. He generates directly the ZP addresses by starting the frame with the base address of the relevant PCM system is loaded Immediately before the counting up, the parallel took place Transfer of the ZP content to register A of the tP buffer and the ZP address register A of the address buffer. The address buffer consists of two parts, da the address is formed from 13 bits (4352 time slots / group). All operations in Address buffers run exactly parallel to those in the ZP buffer.

As soon as register B in the ZP buffer is free, the ZP content is accepted in parallel. Further processing is carried out by reading out register B in series Register C. Reading begins with the selection cycle AWT and takes place at the working speed of the coupling network, in the chosen example with 280 Mbit / s.

The selection cycle AWT is based on the internal time cycle of the coupling network derived and shifted against this in phase so that the transmitted over the bus Time slots at a time that is favorable for further processing in the coupling network arrive there.

If register C is empty, the time location is changed from register B to register C normally transferred serially at the beginning of the selection cycle AWT, whereby the control send a request ANF to the priority control with the beginning of the next The time slot can then transfer the selection clock AWT from register C to the data bus to the coupling network be transmitted serially, if selected by the priority control, i.e. a selection signal AW is sent out to the unit of the PCM system PS concerned will. Otherwise a time slot from another PCM system had higher priority If there is already a time slot in register C and also in register B, then the time slot in register C, as soon as it is selected, with the start of the selection cycle Transfer AWT serially on the bus to the coupling network. At the same time, the time slot becomes in register B "redrawn". The controller sends an additional request to this unit ZA to the priority control. If now after transferring the first time slot No requests from other PCM systems at the beginning of the next selection cycle AWT in the Priority control are present, it selects this additional requirement off (another cannot be available).

The time slot that has been moved will also be immediately afterwards transmitted to the coupling network, thus the desired flexible handling of PCM systems is reached with a bit rate that is currently too high. On the other hand, lie from other PCM systems Requirements, the additional requirement is ignored. She will subsequently converted into a normal requirement.

The ZP buffer thus serves a total of three purposes: - Production the bit and time slot synchronicity between the time slots of the PCM systems and the time cycle of the coupling network, - the transformation of the speed and - the provision of time slots to ensure flexible handling of the transfer to the coupling network when used in plesiochronous networks.

The main functions of controlling a unit for an incoming PCM system PS have already been described above. The table shows a compilation the possible states of the controller and their designation.

Tabel Graph state label 1 Reg. A empty / Reg. A released Load ZG 1 2 Reg. A in parallel Reg. A occupied 5 5 Reg. B empty / Reg. B to the parallel 1 Prepare loading / Reg. Release B. Load ZG 2 4 6 Reg. B in parallel t Continuation table ZG 2 7 7 Reg. B occupied / Reg. B to serial Prepare to read 4 Read Reg. B serially 8 Read Reg. C serially 9 Load Reg. C serially ZG 3 10 Reg. C empty / Reg. C release 11 Reg. C occupied 12 Read Reg. C serially and at the same time Load tig from Reg.B serially To reduce the number of states, the overall state graph was divided into three sub-graphs ZG 1, ZG 2 and ZG 3, which are assigned to registers A, B and C of the buffers. The possible transitions between the states, the transition conditions and the signals and clocks to be generated in the states can be seen from FIG. All status transitions take place synchronously with the central clock of the coupling network, whereby the bit synchronicity is established. The speed transformation takes place when the time slot is read out from register B (state 4), which, apart from a phase shift, also establishes the time slot synchronicity, since all further actions take place synchronously with the selection cycle AWT.

The implementation of the control of a unit for an incoming PCM system PS can with low speed requirements, so with small to medium multiplex factor of the coupling network, through a micro-programmable Control unit take place. With high requirements it is necessary to have a synchronous control unit from shift registers in ECL technology (F 100K), as shown in FIG. 4 to 6 for the state graphs ZG 1 to ZG 3 is shown. The for Measures necessary to initialize the control unit are not shown. Be it but it should be noted that there are certain states in the various graphs are mutually exclusive (e.g. 6 and 2, 8 and 4, 11 and 4) while others are entirely or must occur partially at the same time (e.g. 6 and 3, 9 and 4, 12 and 4).

The priority control shown in Fig. 7 has the task of turning off to select the next person on the bus from the upcoming time slots must be forwarded to the coupling network KN. This selection is made, for example, according to the specifications the arrival of the time slots and the bit rate of the PCM systems from which they originate, that is, the frequency with which the time slots arrive.

Set the time of arrival and the frequency of arrival thus determines the priority that is assigned to a time slot. The priority control then selects the one with the highest priority.

The criterion of the frequency of occurrence had for the determination the priority is being very overweight. In normal operation it outweighs the second Criterion, the time of arrival, almost entirely. It is under normal operation to understand the state of the group of PCM systems in which the deviations from the target bit rate of the PCM systems (within the permissible tolerances) are so that the mean value of the total bit rate of the exchange bit rate largely comes close. The bit rate of the exchange can, however, also differ from the target bit rate differ. This ensures that there are deviations in a PCM system during normal operation its target bit rate has no effect on other PCM systems. Under abnormal Operating conditions, if the mean value of the total bit rate is in the lower tolerance range or clearly is below the bit rate of the exchange, however, time slots of a PCM system can Passed on to the switching matrix at a bit rate that is too high due to additional requirements if the other PCM systems are not making any requests at the same time. This becomes all the more likely due to the too low mean value of the total bit rate, the longer this state lasts.

The operating characteristics described are a consequence of the definition the "time of arrival" as "arrival in the C register of the buffer". These Operating mode is generally to be used when high-stability clock generators for the PCM systems are available and a group of many PCM systems consists. The timing accuracy should be in accordance with CCITT Orange Book: Volume III-2, line transmission.

Geneva: ITU, 1977. ISBN 92-61-Oo351-6 (Rec. G811) when used in plesiochronous Nets are 1 x 10.

This leads to an error rate of a maximum of 2 x 10 11 or a time slot error per 64 kbit / s channel in 70 days. This error rate is the one described above Operating mode slightly reduced, but never increased.

A modified operating mode is based on the "time of arrival" to be defined as "arrival in the A register of the buffer". It must then be small Queues for the (up to three) pending requests per PCM system the priority control are formed. In addition to the frequency of the Received the number of pending requests at the prioritization consider. This operating mode regulates the fill level of the buffers. However two PCM systems with a bit rate that is too high can now mutually support each other in normal operation influence. This means that a time slot error caused by the clock accuracy it is prevented in one PCM system, but precisely this is prevented in the other PCM system Error also occurs if this is also urgently waiting to be picked up. This disadvantage is largely insignificant because in this case Operating mode, the deviations in the bit rate are better compensated for on average. this is advantageous if a group consists of only a few PCM systems. Through this there is an overall reduction in the error rate, albeit the probability for (short) cluster errors grows somewhat. Instead of reducing the error rate however, the required clock accuracy can also be reduced.

The circuit for the priority control of the first described Behavior is a little easier. A few more special features are shown in this example explained. The priority control chooses from all between two selection clocks AWT, the requirements ANF present with the highest urgency and reports this to the AW with a signal on the associated "Selection" line Control of the unit of the PCM system PS concerned. Since the selection signal AW must be present for the time until the next selection clock AWT, it is stored in a buffer Latch 1 through k held. The selection itself is made in one or more priority encoders PE (see Fig. 8), from its request signals ANF at the input the signal HP highest priority is formed. With the next Selection cycle AWT the HP signal is transferred to the buffer. If there is no requirement ANF before, with the signal no request "KAN the evaluation of the additional requests ZA released in the priority encoder PE. There is always only one additional requirement this is selected. If there is also no additional requirement, none of the lines carries an HP signal and KAW is not selected. The signal KAW can be used directly to add a nonexistent address to the coupling network forward (e.g. 8191 = thirteen ones, see Fig. 2 above).

If a group consists of more than eight PCM systems, it is advantageous to evaluate the requirements ANF in subgroups to determine the number of gate inputs in the priority encoders PE not to be too high. Every encoder has PE then an additional input GHP, via which it is blocked if there are requests are in subgroups of higher priority.

The signals GHP i are generated in a two-stage gate network (5. Fig. 7, left), likewise the signal KAN.

The order in which the requirements ANF on the inputs of the Priority control are to be connected, results as follows: The requirements of the PCM system with the highest bit rate in the group is assigned number 1, the the system with the lowest bit rate has the highest number. PCM systems with the same Bit rate get neighboring numbers. So all PCM systems are sorted according to the Bit rate, starting with the highest and numbered in ascending order. The numbering can also have gaps in order to be able to connect PCM systems there that are used by a later expansion should be added len. You don't need to renumber then. This is possible because the selection is made according to relative characteristics, i.e. higher / lower Bit rate, earlier / later arrival.

9 shows how the time slots are at the outputs of the switching network KN of the groups are usually divided again into PCM systems. Since there is no need is that the outgoing PCM systems are synchronized with each other, there are none other problems. The time slots just have to be in such an order leave the switching network that the necessary speed transformation for the (slower) PCM systems are carried out with a simple change buffer can without having to buffer the time slots longer than necessary. The chronological order or assignment of the internal coupling network time slots to the PCM system time slots not unambiguous in all cases. Then an assignment list can be used instead of a formula can be used for mapping.

Claims (9)

Circuit arrangement for processing PCM systems of any order, in particular also of different order, for the purpose of mediation in space and time stages of a coupling network with a high degree of multiplexing by - units for each incoming PCM system (PS) with one register each (1 ZP) for serial / parallel conversion, facilities for clock recovery and for recognizing synchronization characters, one time location counter (ZPI counter), two buffers working in parallel (ZP buffers, address buffers) for the content and address of a Time location and a controller for the unit in question, and through - a common one Priority control with priority encoders (PE) and intermediate storage (latch 1 .... k) for each unit7 with which it is determined between two selection cycles (AWT) which Time slot from which incoming PCM system (PS) for the requests (ANF) to the Read out are available, must be selected for forwarding to the coupling network (KN) and receives a corresponding signal (AW). 2. Circuit arrangement according to claim 1, characterized by a Combination of incoming PCM systems (PS) into groups in which the sum of the Time slots less than or equal to the value of the multiplex factor of the coupling network (KN) is. 3. Circuit arrangement according to claim 2, characterized in that that an expansion in the switching network (KN) is achieved by adding time slots for synchronization characters in the PCM systems that are not required during the exchange for the Switching through voice channels can be used. 4. Circuit arrangement according to one of claims 1 to 3, characterized in that that with about eight or more incoming PCM systems for processing requests (ANF) For reading out sub-groups for the evaluation of the requirements (ANF) are formed. 5. Circuit arrangement according to one of claims 1 to 4, characterized in that that addresses are formed in the time slot counters (ZPI counter) for the individual time slots from the number of the time slot in the relevant incoming PCM system (PS) and a specific base number for each of these PCM systems (PS) will. 6. Circuit arrangement according to one of claims 1 to 5, characterized in that that buffers for the address of a time slot (address buffer) are divided into two parts for bits 1 to 8 or 9 to 13 of a 13-bit address. 7. Circuit arrangement according to one of claims 1 to 6, characterized in that that as a criterion for the priority control the arrival of a time slot an incoming PCM system (PS) is evaluated. 8. Circuit arrangement according to one of claims 1 to 6, characterized in that that as a criterion for the priority control the level of the buffer for the The content of time slots (ZP buffer) is evaluated. 9. Circuit arrangement according to one of claims 1 to 8, characterized in that that time slots from PCM systems (PS) whose transmission rate is currently too high, preferred by the priority control with regard to the forwarding to the switching network (KN) to be selected.