DE3202095A1 - Frame structure suitable for multiplexing signals of very different bit rate - Google Patents

Abstract

To multiplex a fast signal with a bit sequence of 68734.375 to 68750 kbit/s with a slow signal with a bit sequence of 2048 kbit/s to form a multiplex bit stream of 71040 kbit/s, 33 bits of the fast signal are in each case combined with one bit each of the slow signal to form a sector which is repeated 248 times in the frame. The frame is preceded by 12 additional bits for signalling clock adaptations carried out and for alarm signals and after 124 sectors 12 additional bits are inserted for frame alignment so that the frame contains a total of 8456 bits with a frame period of 119.03 mu s. Of the 12 additional bits at the beginning of the frame, 5 bits are in each case used for signalling the clock adaptation for the fast and, respectively, slow signal so that the following different code words are obtained with bit interleaving of the two signalling bit groups: AO, BO: quasi-synchronous state of both signals, AO, B+: fast signal quasi synchronous, clock adaptation for slow signal, A+, BO: clock adaptation for fast signal, slow signal quasi synchronous, A+, B+: clock adaptation for both signals. <IMAGE>

Description

Application: When connecting participants via fiber optic cables (LWL) at control centers or network nodes, television and Donrundfunkprogrnme, video telephony signals, Telephone and data signals are transmitted in a common multiplex bit stream. The invention seeks to provide a time division multiplexed framework for the present one Case of a plesiochronously operated digital network in which the telephone and data signals neither synchronous with the image signals transmitted by the television services, nor to the video telephony signals.

Purpose: With such multiplex bit streams, the possible tolerance is areas for the clocks of the signal flows to be transmitted with the help of clock adjustment methods to compensate so that a trouble-free operation is made possible in each case.

Several such signal flows can then be synchronized in one Multiplexers are combined and transmitted to the subscriber via SWL.

State of the art: In previously known multiplexing methods several (n) normally equally high signal flows to a bit stream approximately n-fold Clock speed combined with a few additional bits for transmission of synchronization and timing adjustment signals can be inserted. This multiplex method relate to input signals with the same bit rate and clock accuracy. The number the input signal n is constant for each multiplex system and amounts to 3 to 30 in multiplexing for standardized systems. The timing adjustment methods are positive, positive-negative or positive-zero-negative clock adjustment into consideration.

DE-PS 25 27 481 is a frame structure for a non-hierarchical Multiplexer known, which is used to combine plesiochronously operated digital time division multiplex subsystems with different, not by dividing one- other derivable Bitrate is supposed to serve. For this purpose, the distance is independent of the bit rate of the subsystems 8 k bit is always chosen between two synchronous words with 16 bits each, with in the middle of the frame formed in this way after 4 'k bits a time channel of 8 bits for recognition the clock adjustment information from a maximum of two subsystems with comparatively high bit rate is kept free, and when wired with subsystems different and / or lower bit rate are 6 more at equidistant intervals of k bit each Time channels with different depending on the number of subsystems to be merged Number of bits provided.

With an output bit rate of approx. 69,000 kbit / s and a frame length from 8. k = 8,368 bits can either be 8 subsystems, each with 8 448 kbit / s or 4 subsystems with 8 448 kbit / s and one subsystem with 34 368 kbit / s or 2 subsystems with 34 368 kbit / s each to form a secondary time division multiplex system be united. The bit rates of the signals to be combined are in the worst case Fall in a ratio of 34 to 8, so from a little over 4. In the invention on the other hand, the bit rates of the signals to be combined differ by about Factor 68 to 2, i.e. about 34, as shown in the following task of Invention emerges. Such a large ratio of bit rates to be merged can only be achieved inadequately with the known frame structure. In addition comes that the signals to be combined not only have a different bit rate, but also have a very different clock tolerance, task: the invention is based on the task of transmitting two signals with very different bit rates (with approx. 68 736 kbit / s and 2 048 kbit / s) with different relative clock tolerance (t 1 . 6 at 68 736 kbit / s or + 65 '10-6 at 2 048 kbit / s) to a multiplex signal summarize.

The input signal with a clock speed of 68,736 kbit / s should either a television program or 2 audio broadcast multiplex signals of 34 768 kbit / s each, which are synchronous with each other and therefore also synchronous can be nested.

The clock frequency of the multiplex signal resulting from the above Input bit rates should nominally correspond to a value of 71,040 kbit / s. The permissible clock deviation must be determined.

Solution = This task is given by the one specified in claim 1 Frame structure solved. The solution presented above in claim 1 Task is derived from the following considerations: Structure of the impulse frame: The The pulse frame should be chosen so that both the number of additional bits and also the number of bits originating from the input signals by one if possible low integer divisors (m = 2, 3 or 4) without a remainder to divide to the Structure of the device still available in Schottky transistor transistor logic (STTL) to be able to use integrated circuits.

For clock adjustment, a method should be used that, if necessary the sending-side insertion of bits without meaning (dummy or stuffing bits) with secured Signaling of this insertion to the receiving end (demultiplexer) provides (positive Clock adjustment).

The invention is explained with reference to FIGS.

The figures show: FIG. 1 the frame structure, FIG. 2 an exemplary embodiment for the use of the additional bits Fig. 3 the position of the possible dummy bits Fig, 4 shows a circuit arrangement for clock recovery in the demultiplexer In Fig. 1 is the structure of the pulse frame for a multiplex signal consisting of the Input currents of 68,736 and 2,048 kbit / s are shown. One frame contains 8,456 bit and repeats after 119.03 bs, i.e. the frame frequency is 8.401 kHz.

Use of the additional bits: To synchronize the demultiplexer 12 additional bits inserted in the multiplexer are used in each frame.

A preceding group of 12 additional bits is used for signaling executed clock adjustments and used for the transmission of alarms. In detail clock adjustments are made for the 68 736 kbit / s signal (A) and for the 2 048 kbit / s signal (B) signaled to the demultiplexer with 5 bits each, the remaining 2 bits are used for alarm signaling. About the effect of cluster errors on clock adjustment signaling to reduce, the two different signaling bit groups become bit-wise nested, with 4 different code words of 10 bits each. Designated the word for signaling a clock adjustment for the 68,736 kbit / s signal with A + and the quasi-synchronous state with AO and the word for signaling a Clock adjustment for the 2 048 kbit / s signal with B + and the quasi-synchronous state with 30, the states A0, B0; AO, B +; A +, BO and A +, Bh to be distinguished. Because these 4 code words are at the same time The distance between how the synchro word is sent must always be a clear difference (Hamming distance) sought between each of the 4 code words and the sync word will. The two for alarm transmission can also be included in this view free bits are included.

In Fig. 2 is an embodiment for the occupancy of the total 24 additional bits shown.

Distribution of the bits from the 2 input signals in the frame: From Fig. 1 it can be seen that a sequence of 33 bits originating in the 68,736 kbit / s signal and a bit that supplies the 2048 kbit / s signal represents a sector, which is based on those described in the previous section and can be seen from FIG 12 additional bits are connected and, repeated 248 times per frame, the entire pulse frame form. After the 124th sector, those needed for frame synchronization are used 12 bit sent.

The positions of the possible dummy bits are shown in FIG. As can also be seen from Fig. 3, for the slow signal sequence (2 048 kbit / s) 248 places, for the fast signal sequence (68 736 kbit / s) 8 184 places per frame intended. However, at the nominal frequencies of the signal sequences mentioned, from the slow series only has 243,777 places on average, and the fast series only 8 181,751 places are occupied on average. If one assumes that in the framework for both A dummy bit (see FIG. 3) can only be inserted if necessary should, there is an overcapacity for the slow sequence of 4 bits and for the fast sequence 2 bits per frame. I. E. overall results within the multiplex frame at the desired frequency of the multiplex clock one free and additional one for the transmission Usable data bit rate of approx. 50.4 kbit / s.

These 6 bits free per pulse frame should be as evenly as possible over be distributed over the entire frame duration.

Clock tolerance for the multiplex clock: At the target frequency of all involved Clocks results for the average rate in which dummy bits in the 68,736 kbit / s signal (i.e. bits of no importance to prevent idle input buffers) insert a value of 0.249; d. H. in about every 4th frame is on average to transmit a dummy bit. A limit value then results from the assumption that the television signal sequence by a maximum of 1. 10 6 or 69 Hz above the mentioned Setpoint is and the multiplex clock deviates downwards by so much that there is no space there is more for inserting dummy bits. This is the case with a multiplex frequency of 71 037.912 kHz. With a tolerance specified above for the clock frequency of the TV signal of + 1 S 10'6 must therefore have a tolerance value for the multiplex frequency of + 29.38. 10 6 are complied with. A control calculation shows that the conversely, gives a rate of 0.497 for inserting dummy bits, i.e. H. A blind bit would then have to be inserted in every 2nd frame.

Clock recovery in the demultiplexer: Fig. 4 shows a block circuit for clock recovery for the original signals in the demultiplexer from the multiplex clock transmitted with the aid of the in the clock adjustment signals; Information for the television signal (CF +) and the telephone (or data) signal (CD +).

4 shows a circuit arrangement for clock recovery in the demultiplexer in the event that the clock frequency of the high-speed bit sequence is 68,736 kHz. Of the Multiplex clock with a clock frequency of 71,040 kHz is in three consecutive Divider levels divided by 2, 7 and 151. In a first phase comparator PK is this clock compared with a clock that is divided by four divider levels (2/1, 3/1, 11/1 and 31/1) from a first voltage-controlled oscillator VCO with a clock frequency of 68 754.9 kHz is obtained, the first phase comparator PK is followed by a low-pass filter, via which the first voltage-controlled oscillator is set Output available clock frequency has nominally one due to this control circuit Value of 68 754.9 kHz, but has a fixed frequency ratio to the multiplex clock of 71 040 kHz and also follows its clock deviations.

The clock frequency of 68 754.9 kHz generated in this way is used by a first pulse adapter PA supplied, with the help of which individual clock pulses are faded out at regular intervals will.

The fade-out of the clock pulses is fixed with the one recognized on the receiving side Pulse frame coupled and occurs 2 times in each frame, i.e. H. with a repetition rate of 16.8 kHz (in Fig. 4, these correction commands are denoted by CR).

The process of regularly fading out two clock pulses per frame is necessary because otherwise the required frequency of 68 738.1 kHz is only available via one Divisor of 4 091 (prime) compared with the frequency of the multiplex clock divided by 2 could be, but this divider is very difficult to implement in circuit technology were. The clock reduced in this way to a frequency of 68,738.1 kHz is fed to a second pulse adapter, at the second input of which a correction signal is then sent CF + is present when a clock adjustment carried out in the multiplexer on the receiving side is reversible. In these cases the clock rate is 68,738.1 kHz respectively an impulse faded out.

Since the clock adjustments are on average with a repetition frequency of 2.1 kHz take place, leave this second pulse adapter already the required number of Pulses per unit of time are due to the manipulation carried out with provided individual stoops. This pulse sequence is fed to a second phase comparator for smoothing PE supplied, at the second input of which from a second voltage-controlled Oscillator VCO's incoming clock is 68 736 kHz. The output voltage of this phase comparator controls the frequency of the second voltage-controlled oscillator via a low-pass filter, at its output the clock frequency necessary for the further function of the demultiplexer the fast bit sequence is available.

For the clock recovery of the slow bit stream, the first Phase comparator applied clock continues to be fed to a third phase comparator PE, at its second input the clock divided by 61 from a third voltage-controlled clock Oscillator, which oscillates at 2 049.9 kllz, This third phase-locked loop consists of the third phase comparator PK, a third low-pass filter, the third voltage controlled oscillator VCO for 2 049.9 kHz and the clock divider 61/1 in the return. At the output of the third voltage controlled oscillator VCO sets a clock rate of 2,049.9 kHz, which is also in a fixed frequency ratio to the multiplex clock of 71 040 kHz and its clock deviations follows. Similar as for the fast bit stream, a fourth phase-locked loop is used with the help of the correction signals CD + the one necessary for further processing in the demultiplexer Clock for the slow bit stream of 2 048 kHz recovered. A third pulse adapter PA, a fourth phase comparator PK, a fourth low-pass filter and a fourth voltage controlled oscillator VCO that oscillates at 2 048 kH.

Changes in the clock frequency for the television signal: simplifications in the implementation, both in the multiplexer and in the demultiplexer, when the clock frequency for the television signal to be multiplexed is increased to 68,750 kHz will. The 8 184 places in the pulse frame can then be occupied in the multiplexer be, d. H. there is no decoding for 2 bits in the frame. In the demultiplexer can the effort for the regular removal of two impulses (input CR and PA in Fig. 4) from the recovered clock are omitted, those from the first oscillator (Fig. 4) incoming clock frequency then serves as the basis for obtaining the output bit rate of 68 750 kbit / s. It only needs the clock frequency of the 2, phase-locked loop the new value can be changed.

At the nominal frequency of the clocks involved, this results for the middle one Rate at which dummy bits are to be inserted into the 68 750 kbit / s signal, a value of 0.582; d. H. In about 6 out of 10 frames, on average, blind bits are to be transmitted. A The limit value then results from the assumption that the television signal sequence is around 69 Hz is below the specified target value and the multiplex clock deviates as far upwards, that a dummy bit must be inserted in each pulse frame. This is true for one Multiplex frequency of 71 043.556 kHz. At the relative tolerance specified above -6 of +1 10 6 for the clock frequency of the television signal is thus for the relative The tolerance of the multiplex signal must be kept to a value of + 50.06 '10'6. In the other Case when the clock of the television signal is extremely high, especially the clock of the multiplexer are low, the result is a clock adjustment rate of 0.164; d. H.

A blind bit must be inserted in approx. every 6th frame.

Only minor changes to the clock recovery described with reference to FIG. 4 result when the clock frequency of the television signal drops to a value of 68 734.375 kHz is decreased. In FIG. 4, only the value of the clock frequency then changes in the second voltage controlled oscillator.

At nominal frequency, bits become irrelevant at a rate of 0.442 transferred, d. H. A dummy bit must be inserted in about 4 out of 9 frames. With the above conditions for the tolerance of the television signal clock results For the multiplex clock there is a relative clock tolerance of + 53.03 10 6 d. H. a Tolerance range of + 3.767 kHz.

Assuming this accuracy of the multiplex clock, the result is a maximum clock adjustment rate of 0.884, i.e. H. in about 9 out of 10 frames a clock adjustment is necessary.

Achievable Advantages: With the aid of the invention, two signals interleave with very different bit rates and clock accuracy without the two signals to each other and to the clock of the multiplex bit rate in a rigid frequency relationship have to stand.

With the help of the invention, depending on the choice of the television signal clock an additional transmission capacity of up to 50.4 kbit / s can be made available.

Furthermore, a national long-distance network can be set up and operated without having to solve the synchronization problems.

Claims (4)

For multiplexing signals with very different bit rates Suitable frame structure (4) Patent Claims Oil For multiplexing signals frame structure suitable for very different bit rates, with one for synchronization and for signaling of clock discrepancies serving additional information for a positive clock adjustment, characterized in that a) for multiplexing a fast signal with a bit sequence of 68 734.375 to 68 750 kbit / s with a slow signal with a bit sequence of 2 048 kbit / s to a multiplex bit stream from 71 040 kbit / s 57 bits of the fast signal each with 1 bit of the slow one Signals are combined to form a sector which is repeated 248 times in the frame, b) that the frame 12 additional bits for the signaling of executed clock adjustments and for alarms and 12 additional bits for frame synchronization after 124 sectors are inserted so that the frame has a total of 8 456 bits with a frame duration of 119.03 As ps contains (Fig. 1), c) that of the 12 additional bits at the start of each frame 5 bit for signaling the clock adjustment for the fast (A) or slow Signal (B) can be used, so that with bit-wise interleaving of the two signaling bit groups the following 4 different code words result: AO, B0: quasi-synchronous state Both signals AO, B +: fast signal quasi-synchronous, clock adjustment for slow one Signal A +, B0: clock adjustment for fast signal, slow signal quasi-synchronous Al, B +: clock adjustment for both signals (Fig. 2). 2. Frame structure according to claim 1, characterized in that with a clock speed of 68 736 kbit / s and a permissible clock deviation von- + 1 i016 for the fast bit sequence is the relative clock deviation of the multiplex signal + 29.38. 10 6 may be. 3. Frame structure according to claim 1, characterized in that if the clock speed is increased to 68,750 kbit / s and a permissible Clock deviation of + 1 0'6 for the fast bit sequence is the relative clock deviation of the multiplex signal j 50.06 e 10 6 may be. 4. Frame structure according to claim 1, characterized in that when the clock speed is reduced to 68 734.375 kbit / s and a permissible Clock deviation of +1 10-6 for the fast bit sequence the relative clock deviation of the multiplex signal + 53.06. May be 10-6,