DE2808298C2 - Arrangement for the digital control of an m-phase pulse width controlled thyristor DC converter - Google Patents

Description

with a control generator for generating a pulse train of constant frequency,
to the output of which a clock pulse counter is connected, the outputs of which are used on the one hand to generate undelayed pulses offset according to the number of phases, which are fed to the main thyristors or extinguishing thyristors of the controller and, on the other hand, to generate the number of times offset and delayed pulses with an equal number of as Matrices are connected to realized decoders,

- The decoder also having a control pulse counter designed as a reversing counter are connected,

which a control unit writes a digital numerical value representing the amount of the delay,
so that the decoders generate delayed pulses if the two pulse patterns supplied to them are the same, which are supplied to the clearing or main thyristors of the controller,

characterized in that

the clock pulse counter consists of only one counter (3), which is used to generate the un-

delayed, according to phase - T offset import

pulse is followed by a decoder (20)
and at the outputs of which all decoders (4 and 7) for the delayed pulses are in parallel, so that the control pulse counter also consists of only one reversing counter (24), the outputs of which are parallel to all decoders (4, 5, 6, 7) for the delayed, among themselves ever

Phase by - T applied pulses offset

are,

whereby the phased offset of the delayed pulses by - Fin the individual De- " m "

encode by corresponding linking of the matrices (62 and 85, 150 to 173).

60

The invention relates to an arrangement for the digital control of an m-phase pulse width control Thyristor DC converter of the type described in the preamble of the patent claim, from SU-PS 24 290 known art.

/ ur digital control of the thyristors of thyristor DC converters, as used in electric vehicles and industrial drives, must be supplied to the thyristors of the DC chopper with undelayed and delayed control pulse trains will. It is necessary to reduce the current pulsations in the supply source at the same time Generation of the temporally re-educated and delayed Pulse trains the use of each subsequent phase of the polyphase DC chopper in relation to the

previous phase to postpone - Γ, in which

m is the number of phases of the thyristor DC converter and T is the switching time of the thyristors of the DC converter.

In the arrangement known from SU-PS 4 24 290, the delayed and undelayed Pulse trains in the control pulse counter several reversing counters and in the clock pulse counter several clock pulse counters can be used, the number of which corresponds to the number of phases of the DC converter. As a result, with the known arrangement, the operational reliability is relatively low. Dimensions and costs relatively high and the quality of the control because of the Scatter of the characteristic values of the pulse counters used unsatisfactory. The variation in the parameters of the pulse counters is also disadvantageous in terms of the accuracy of the time shift of the pulses, which causes current pulsations occur and the proportion of harmonic components in the feed stream is relatively high is.

Furthermore, from »Work of the Dnepropetrovsk Institute für Eisenbahningenieure «, 1971, No. 106. Pages 66 to 70, an arrangement for the digital control of a multiphase thyristor DC chopper known that only a clock and a reversing counter that on a decoder are connected, a switch and a clock contains. Here is the duty cycle discreetly changeable; the value of discretion; d. i.e. the minimum step width by which the duty cycle is variable, depends on the number of flip-flops in the counters.

The known arrangement, however, has a large number of formwork elements, which increases operational reliability and the dimensions and costs of the arrangement are relatively large.

The invention is based on the object of developing the generic arrangement so that at The reduced number of circuit elements increases their accuracy and reliability.

According to the invention, this object is achieved by the characterizing features of the patent claim.

Since, according to the invention, the clock pulse counter and the control pulse counter each only off consist of a binary counter, the operational reliability and accuracy of the arrangement according to the invention increases while the dimensions, cost and power requirements of the assembly are reduced.

The exemplary embodiments of the arrangement according to the invention shown in the drawing are described below explained. It shows:

1 shows the circuit diagram of an arrangement for the digital control of a four-phase thyristor DC converter,

Fi g. 2 the circuit diagram of a decoder was delayed Pulse trains connected to the second phase of the DC chopper and

F i g. 3 shows the circuit diagram of a decoder for delayed

Pulse trains associated with the first phase of the DC chopper connected is.

The arrangement 1 (Fig. 1) for the digital control of a four-phase thyristor DC converter comprises a control generator 2, the output of which is connected to the input of a clock pulse counter. The clock pulse counter consists of a clock pulse counter 3 with η digits (flip-flops).

The clock pulse counter 3 is connected with its logical outputs, the number of which is twice the number of digits of the clock pulse counter 3, to the first logical inputs of decoders 4,5,6,7 for delayed pulse trains. The logic outputs of the clock pulse counter 3, which correspond to a temporal shift in the use of each phase 8, 9, 10, 11 of the thyristor DC converter by - T = - T corresponding Zürn 4
determine the status are at the same time to a decoder

20 for non- delayed pulse trains, where T is the switching time or period of the thyristors 12, 13, 14, 15, 16, 17, 18, 19 of the DC chopper and m = 4 is the number of its phases 8, 9, 10, Ii. The summation output 22 and the subtraction output 23 of a control unit

21 are connected upstream of the summation or subtraction input of a control pulse counter. the the latter is designed as a reversing counter 24, the number of digits of which is the same as that of the clock pulse counter 3. Of the Reversing counter 24 is with its logical outputs to the other logical inputs of each of the decoders 4,5,6.7 connected for delayed pulse trains. Of the Decoder 20 for non-delayed pulse trains has outputs 25,26,27,28 which are connected to the main thyristors 12, 13.14 and 15 of phase 8, 9, 10 and 11 of the four-phase Thyristor DC chopper are placed. The quenching thyristors 16, 17, 18, 19 of phases 8, 9, 10, 11 are present with the outputs of the decoders 4,5,6 and 7 for delayed Pulse trains in connection. Phases 8, 9, 10, 11 of the thyristor converter also have commutation capacitors 29,30,31,32, those with the main thyristors 12,13,14,15 and the quenching thyristors 16, 17,18,19 connected, and motors 33,34,35, 36 connected to windings 37,38,39,40 and are bridged by free-wheeling diodes 41, 42, 43, 44, the latter with the negative pole of a feed -15 source 45 are connected. In parallel with the quenching thyristor 16.17,18 or 19, an oscillating circuit is connected, the each of a reversing throttle 46, 47, 48 or 49 and a reversing diode lying in series with this 50, 51, 52 and 53 respectively.

The thyristors 12 to 19 can also be connected to the control arrangement 1 in a different manner. The main thyristors 12, 13, 14, 15 can be connected to the outputs of the decoders 4, 5, 6, 7, and the clearing thyristors 16,17,18,19 to the outputs 25,26,27,28 des Decoding 20 for non-delayed pulse trains can be connected.

The decoder 5 (Fig. 2) for delayed pulse trains connected to the thyristor 17 of the second phase 9 has output rails 54 to 61 corresponding to the number 2 ″, which are connected via matrices, here Diodenmatri - /. En 62 to 85 with the outputs of the flip Flops 86, 87, 88 of the clock pulse counter 3. At clic I lip hops 89, 90, 91 of the reversing counter 24, the output rails 54 to 61 of the decoder 5 for delayed pulse trains are placed via diode matrices 92 to 115. The circuit arrangement shown in FIG Diode matrices 62 to 85, 92 to 115 ensure a time shift in the use of the quenching thyristor 17 of the second phase 9 by 0.25 T compared to the use of the quenching thyristor 16 in the first phase 8 of the direct current divider and 92 to 115 au the output rails 54 to 61 of the decoder 5 corresponding to different operating states of the flip-flops 86, 87, 88 of the clock pulse counter 3 and d of the flip-flops 89, 90, 91 of the reversing counter 24, which are given in Table 1 for three-digit (n = 3) pulse counters 3.24.

Table 1 State number

Flip-flops of the clock and reversing counter 3 and 24

86.89

87.90

88.91

0 O 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 I. 0 1 1 1 1 1 0 0 0

So the output rail 54 of the decoder 5 is connected to the clock pulse counter 3 via the diode matrices 62,63. 64 connected in accordance with the third state of the flip-flop 86, 87, 88 of the clock pulse counter 3.

The remaining output rails 56 to 61 of the decoder 5 for delayed pulse trains are connected to the clock pulse counter 3 in a similar manner corresponding to the subsequent state of the flip-flops 86, 87, 88 of the Counter 3 in connection.

The output rail 54 of the decoder 5 is connected to the reversing counter 24 via the diode matrices 92, 93, 94 connected according to the first state of the flip-flops 89, 90, 94 of the revising counter 24. The exit rail Si of the decoder 5 is correspondingly connected to the reversing counter 24 via the diode matrices 95, 96, 97 the second state of the flip-flops 89, 90, 91 of the reversing counter 24 is placed. The Exit Rail 56 of the decoder 5 is connected to the reversing counter 24 via the diode matrices 98, 99, 100 corresponding to the third State of the flip-flops 89,90,91 of the reversing pulse counter 24 led. The next output rails 57 to 61 of the decoder 5 are corresponding to the fourth, fifth, sixth, seventh and eighth state of the flip-flops 89, 90, 91 of the reversing counter 24 are switched.

The output rails 54 to 61 of the decoder 5 door delayed pulse trains are ORed 116 connected. The output of the OR gate 116 forms the output of the decoder 5. The output rails 54 to 61 are located directly on the positive pole of a supply source 117.

The output rails 54 to 61 can be connected to the supply source 117 via resistors, the parameters of which are selected on the basis of the required level of the output signal of the decoder 5.

With phase 8 of the thyristor DC converter, the decoder 4 (FIG. 3) stands for delayed pulse trains in connection, the execution of which is a time shift of the grain from the output of the decoder 4

menile impulses by - T { —7 ") compared to the

-4 \ m J

Output of decoder 5 for delayed pulse trains removed pulses guaranteed. The decoder 4 has output rails 118 to 125 which are similar to at the decoder 5 door delayed pulse trains via diode matrices 126 to 149 to the flip-flops 89,90,91 of the reversing counter 24 are connected.

The output rail 118 of the decoder 4 for shifted pulse trains is connected to the flip-flops 89,90, 91 of the reversing counter 24 via diode matrices 126, 127, 128 according to the first state (Table 1) of the flip-flop 89, 90, 91 in connection. The output rail 119 of the decoder 5 is connected to the flip-flops 89, 90, 91 of the reversing counter 24 via diode matrices 129, 130, 131 in accordance with the second state the flip-flops 81, 82, 83 led. The output rail 120 of the decoder S is connected to the flip-flops 89, 90, 91 of the reversing counter 24 via diode matrices 132, 133, 134 corresponding to the third state of FIG Flip-flops 89,90,91 placed. The remaining output rails 121 to 125 of the decoder 5 are connected to the flip-flops 89,90,91 of the reversing counter 24 via diode matrices 135 to 149 in accordance with the subsequent states of the flip-flops 89,90,91 of the counter 24 are connected.

The output rails 118 to 125 of the decoder 4 are connected to the clock pulse counter 3 via Diodenmatri- / cn 150 to 173 in connection, which in the same order as with the diode matrices 92 to 115 (Fig. 2) of the Decoder 5 are composed.

The output rail 118 of the decoder 5 is connected to the flip-flops 86, 87, 88 of the clock pulse counter 3 via the Diode matrices 150,151,152 corresponding to the first state of flip-flops 86,87,88. The exit rail 119 of the decoder 5 is connected to the flip-flops 86, 87, 88 of the counter 3 via the diode matrices 153, 154, 155 corresponding to the / wide state of the flip-flops 86, 87, 88. The output rail 120 is connected to the Flip-flops 86, 87, 88 of the clock pulse counter 3 via the Diüdenmatri / cn 156, 157, 158 in accordance with connected to the third state of the flip-flop 86, 87, 88. The remaining output rails 121 to 125 stand with the flip-fiops 86,87,88 of the clock pulse counter in connection.

The output rails 118-125 of the decoder 4 for shifted pulse trains are also connected to the OR gate 174 connected, the output of which represents the output of the decoder 4.

The output rails 118 to 125 are placed directly in the supply source 117.

The Diudenmatrizen the other decoder 6, 7 for delayed pulse sequences such as the decoder 4, 5 are constructed by the same principle, so that the temporal displacement of the insert of the phases environmentally T

is secured against the preceding decoder.

The arrangement works as follows.

For applying the voltage from the supply source 117 to the motors 33,34,35,36 and the excitation windings 37,38,39.40 become the main thyristors 12,13,14,15

open with a time shift of - T. During this time (pulse period) the current in the motors 33, 34, 35, 36 increases from the selected minimum value to the maximum. After expiration of the required duration of the blocking of the main thyristors 12,13, 14,15 serving pulse, the thyristors 16 to 19 with a time shift by - T

switched through. When the quenching thyristors 16, 17, 18, 19 are switched through, the main thyristors are 12. 13. 14,15 the reverse voltage of the commutation capacitors 29, 30, 31, 32 is supplied. Within the break will the current in the motors 33,34,35,36 and the excitation windings 37, 38, 39, 40 by the within the pulse period in the inductances of the motors 33, 34, 35, 36 stored electromagnetic energy is maintained, the current through the freewheeling diodes 41, 42, 43, 44 and the windings 37, 38, 39, 40 are called.

To increase the voltage on the motors 33, 34, 35, 36, the pulse duration is lengthened, i. H. it happens a time delay for the ignition of the Lüsciithyristoren 16, 17, 18, 19 with respect to the ignition timing of the respective main thyristors 12, 13. 14. 15. After the time period T has elapsed, the work cycle is repeated.

The generation of the thyristors of the DC chopper supplied pulses goes on as follows.

When a control signal arrives from the control unit via its summation output At the summation input of the reversing counter 24, the flip-flops 89, 90, 91 are in state 1 (after Table 1). According to the state of the flip-flops 89,90,91 of the reversing counter 24 are on the decoders 4, 5, 6, 7 given for delayed pulse trains binary codes.

From the control generator 2 clock pulses come uninterrupted to the input of the clock pulse counter 3. In the extent to which the pulses arrive at the clock pulse counter 3, the flip-flops 86, 87, 88 change their states. From the logic outputs of the counter 3, the binary codes reach the decoder 20 for non-delayed ones Pulse trains and to the decoders 4, 5,6,7 for delayed pulse trains.

A pulse appears at the output 25 of the decoder 20 as soon as the first pulse from the control generator 2 is on Clock pulse counter 3 arrives. At the output 26 there is a pulse when the Taklimpulszähler 3 of

(- + 1 Vth pulse supplied by control generator 2 \ m)

will. A pulse appears at output 27 when the (2 ■ I-1 Yth pulse at counter 3. Am

\ m J
A pulse appears at output 28 when the

3 · Hl Vth pulse on counter 3.

m J
So the control impulses reach the main lhy-

ristors 12,13,14,15 with a time shift

rArlionanilane

If the first state of the flip-flops 86,87,88 des Clock pulse counter 3 with the first state of the flip-flops 98, 90, 91 of the reversing counter 24, then a control pulse is delivered at the output of the decoder 4. This control pulse is opposite to that from Output 25 of the decoder 20 for non-delayed pulse trains coming impuis temporally by an amount offset, the discreteness for the quantization of the switching period of the controller, i.e. the frequency of the Control generator 2 corresponds to that much larger than

the pulse rate - is.

When the first state of the flip-flops 89, 90, 91 of the reversing counter 24 matches the

(- + 1 \ t ^cn state of the flip-flops 86,87,88 of the clock

pulse / counter3, a control pulse appears at the output of the decoder 5. This pulse is also a> Delayed amount equal to the discretion for the Is quantization of the switching period of the controller.

Finally, when the state collapses, the flip-flops 89, 90, 91 of the reversing counter 24 are included the (3 · - + l \ th state of the flip-flops 86, 87, 88

\ m J

of the clock pulse counter 3, a pulse at the output of the decoder 7 is supplied. This impulse is opposite to that from the output 28 of the decoder 20 for non-delayed pulse trains also by one pulse _ Amount offset, which is the discretion for the quantization of the switching time of the thyristors of the thyristor pulse converter is equivalent to.

This will open the main thyristors 12, 13, 14, 15 of phases 8,9,10,11 over the period, which equals the discreteness for the quantization of the switching time of the thyristors of the thyristor pulse converter is, with a time shift to

- T secured.

As soon as the second pulse from the control unit 21 via the summation input 22 on the reversing counter 24 arrives, the flip-flops 89,90,91 of the reversing counter 24 is set to the second state shown in Table 1.

If the second state of the flip-flops 86, 87, 88 of the clock counter 3 is correct with the second state of the flip-flops 89, 90, 91 of the reversing counter 24 match, a pulse appears at the output of the decoder 4 which temporally compared to that coming from the output 25 of the decoder 20 for non-delayed pulse trains Pulse offset by twice the amount of discretion for the quantization of the switching period of the controller. By the same amount the output of the decoder 5 for delayed pulse trains pulses coming from the output 26 of the decoder 20 for non-delayed pulse trains incoming pulses, the pulses coming from the output of the decoder 6 for delayed pulse trains compared to the pulses taken from the output 27 of the decoder 20 for non-delayed pulse trains and the pulses coming from the output of the decoder 7 for delayed pulse trains compared to the Output 28 of the decoder 20 removed pulses offset.

to the same extent as the impulses from the outing of the country 22 of the control unit 21 arrive at the reversing counter 24, the time shift increases. The maximal The time shift corresponds to the switching period of the actuator. If a shortening of the pulse duration is necessary is, the pulses from the control unit 21 to the reversing counter 24 via the subtraction input 23 supplied. In this case, the pulse duration is shortened in reverse order.

60

For this purpose 3 sheets of drawings

Claims (1)

Claim: Arrangement for the digital control of an / n-phase (m = any whole number) pulse-width controlled thyristor DC converter with time-shift - T (T = pulse period of the individual direct current controller) staggered control of the individual phases