DE2858826C2 - Receiver tuner permitting channel searching - Google Patents

Abstract

The TV tuner has an oscillator whose frequency is controlled by a binary number N applied to a control loop from a processing circuit to which coded data are applied. The control loop has frequency dividers delivering a first signal which is a function of the number N. The first signal is compared with a reference signal for delivering a third signal used for tuning.Digital data allocated to the channels is stored. Devices automatically or by hand scan the store step-by-step. Signal generators are used to derive the number N from the stored data. The processing circuit generates a first series of N numbers depending on a first coded input signal, the numbers corresponding to all receivable according to a given standard channels. It is switched forward by one step on reception of a second coded input signal

Description

The invention relates to a circuit arrangement according to the preamble of claim 1. Such a circuit arrangement is from the US Magazine "Electronics", 1977, September, pages 46 to 48 and 50 known.

In a known television signal receiver with a PLL tuning system (US-Z "Electronics" a.a.O.) a fine tuning is provided to the Standard receive frequencies in the sense of a detuning by hand to be able to change. Such fine tuning is required, for example, at Reception via a community antenna system. The load impedance of such Systems depends on the number of TVs currently switched on signal receiver and therefore changes constantly, what corresponding changes which results in reception frequencies. Furthermore, at community antenna systems the frequency bands in a different frequency range sets, for which often, especially in older systems, no frequency stable Quartz oscillator is used. Due to the temper dependence of the set oscillators, there are also variations in the receive frequencies. Another reason for the need for fine-tuning is daily temporal changes in wave propagation.

However, it has been shown that teletext reception is very critical Detuning of the standard reception frequencies reacts, and even when the picture and sound are acceptable. The reason for this is that the digital teletext signals only have parity error protection, which is already a relatively small degradation is overloaded, with the result that the digital The reception suddenly stops. In contrast, the analogue deteriorate Image and sound signals continuously without the reception abruptly interrupting. On Another disadvantage of fine-tuning shows up during an automatic  "Fine grid search", such as that from the magazine "Funk-Technik", 1977, No. 16, R & D, pages 270, 272, 281, 282 and 284. Around To be able to receive stations whose frequency does not comply with the CCIR standard, the raster frequency is gradually increased in this automatic search on both sides up to the channel boundary. If there is no transmitter found, the voting system jumps to the after a search command next channel frequency. If you previously fine-tuned, you cannot standard receiving frequencies are shifted to a frequency position which the search stops. If there is a change in fine tuning, the Reception of a station tuned in this way deteriorates or is disturbed. Finally, there are television signal receivers that have been fine-tuned save and carry out again automatically when the channel is selected again. To that User a way to quickly reset his recipient in the Many remote controls have one to enable the standard state so-called "grandma" button. However, pressing the "Grandma" button does not only removes the upset, but also all other operating parameters, such as brightness, color saturation and volume, to the factory settings Deferred values. However, pressing the "Grandma" key requires that the user knows that detuning has occurred through fine tuning Has. With multiple users of a television signal receiver, e.g. B. in one Family, this knowledge is often not available, so that they are Users are surprised by a sudden bad reception caused by the carried out fine tuning have no knowledge.

From the magazine "Electronic World", April 1968, pp. 34-36, 64-67 and December 1967, p. 16 is a tuning aid for television signal receivers known, where two vertical bars are shown on the screen of which one bar is fixed and the other bar is through Change the vote on the screen is slidable. After done Choosing a TV channel shows the filing of the sliding bar from the fixed bars indicate the relative size of a mismatch.  

By manual re-tuning, both bars can be made to coincide, with which an optimal coordination is achieved. At the displayed Mismatch, however, is an undesirable deviation from the selected channel frequency due to the inaccuracies of the time Oscillators in the TV tuners. Since the introduction of frequency-accurate Quartz oscillators have become obsolete. The known signal only signals to the user when the channel is selected Eliminate mismatch that has occurred by keeping the vote as long is changed until both bars are congruent. A firm, wanted Mismatch can be seen with the television signal receivers at the time anyway do not adjust. Even if you have the technically outdated mis-vote Use the display in modern television signal receivers with quartz oscillators would, this measure would make little sense, since the displayed filing of the sliding bar from the fixed bar no numerical and reproducible information about the absolute size of the misalignment can be removed.

In contrast, the object of the invention is to provide every user of the TV signal receiver on the exact extent of a made To inform fine-tuning, especially with automatic Station search a reliable setting of non-standard frequencies guarantee.

This object is achieved by the characterizing features of Claim 1 solved.

Advantageous refinements and developments of the invention Circuit arrangement result from the subclaims.

The invention is based on the consideration by the microprocessor Tuning circuit a quantifiable indication of the size of the manual fine tuning made visible on a display device do. Especially before a search command for an automatic Channel search, in which all reception frequencies are searched in frequency steps that correspond to a fraction of the distance between two adjacent channels,  the user can fine-tune accordingly based on the display correct.

The invention is illustrated below with reference to one in the drawings Embodiment explained in more detail. It shows:

Fig. 1 is a block diagram of the circuit arrangement according to the invention for tuning a television signal receiver;

Fig. 2 is a block diagram of details of the circuit arrangement of FIG. 1 and

Fig. 3 to 10 are flowcharts of the essential functions of the circuit arrangement of FIG. 1 and 2.

In particular, FIG. 1 shows the drawing, a receiver antenna 1 is connected to an constructed using varactor diodes tuner 2, at the transition from a converted to an intermediate frequency IF output signal is available.

The tuner 2 is constructed in a known manner and consists essentially of a selective amplifier stage, a mixer stage and an internal oscillator circuit. One of the outputs of the internal oscillator circuit is connected to a first frequency divider circuit which divides by a fixed number N1 and is referred to below as the first divider 3 . The first divider has an output which is connected to the signal input of a second divider 4 as a frequency counter, which divides by a variable number N as a function of 12-bit instructions, this number N being any number between 1 and 2 12 . The output of the second divider 4 is connected to the first input of a phase-frequency comparator circuit 5 , the second input of which is supplied via a third divider 7 with a reference signal which is generated by a quartz generator 6 . The output of the comparator circuit 5 is connected via an amplifier and filter circuit 8 to the control input for the capacitance diode voltage of the tuner 2 .

A control unit 10 is connected to a number of inputs of a processing unit 11 . A group of input / output terminals of the processing unit 11 is connected to a memory circuit 12, during a first group of Ausgabeanschlüs sen the processing unit 11 is connected to a display system 9, a second group and of twelve output terminals to the programming inputs of the second divider. 4 Two further output connections U + B are connected to corresponding control inputs of tuner 2 .

The function of the circuit according to FIG. 1 will be explained in more detail below with reference to FIG. 2, where the circuits 9 , 10 , 11 and 12 are shown in more detail.

As shown in Fig. 2, the control unit 10 is a keypad with ten numeric keys (0 to 9), with six auxiliary keys I, D, M, R₁, R₂ and R₃ as well as with additional control keys, two of which with "+" or " - "are designated. In addition, there are other buttons that are not shown in the drawing, for example an on / off switch, a silent button for temporarily interrupting the acoustic playback, a data display button, etc.

The display system 9 comprises four alphanumeric LEDs, while the processing unit 11 has two 8-bit output circuits PA and PB. The eight outputs of the first output circuit and four outputs of the second output circuit together form the programming signal for the second divider 4 , while the band change signals U and B are fed to the tuner 2 via two further outputs of the second output circuit PB.

The memory circuit 12 is intended for the storage of 8-bit words or bytes and consists of three blocks RAM1, RAM2 and ROM.

The first block RAM1 is a read-write memory with permanent information storage, which registers K0 to K9,  S0 to S9, RA and RB has. The second block RAM2 is on Read-write memory with the registers MO, K, S, C, F, RX, INT and T.

The third block ROM is a read-only memory, which serves as a program memory and contains, in coded form, the sequence of the basic logic functions to be carried out by the processing unit 11 .

The circuit works as follows:
The circuits 3 , 4 , 5 and 8 together with the internal voltage-controlled oscillator of the tuner 2 containing the capacitance diodes form a phase-locked loop which is controlled by the reference signal which is generated by the quartz generator 6 and which, in a known manner, by the third Divider 7 is divided down.

The function of the first divider 3 is to divide the relevant frequencies down to easier-to-process frequencies, while the programmable second divider 4 enables the frequency feedback to be influenced at different frequencies of the internal oscillator by creating a frequency synthesis circuit.

Specifically, the comparator circuit 5 , when a divisor N is selected for the second divider 4 , supplies a voltage to the tuner 2 via the amplifier and filter circuit 8 , which brings about the following condition:

or

f₂ = P × N (2)

where f₂ = frequency of the internal tuner oscillator; F6 = frequency of the quartz generator 6 ; N₂, N₁ and N = divisors or divider ratios of the divider 3 , 6 or 4 ; and where

namely changing the frequency of the internal Oscillator when changing the number N.

The receiver must be tunable to transmitting stations work according to specified transmission standards, for example according to the CCIR / B-G standard, according to which the channels correspond to the European Broadcasting Conference of Stockholm (1961) where the frequency spacing between adjacent transmitters the VHF bands I and II is 7 MHz and the UHF bands IV and V at 8 MHz and where the video signal bandwidth is 5 MHz is.

The stations for which the conditions specified above apply, are in the range of television channels 2 to 69 (video carrier frequencies of 48, 25 MHz and 855.25 MHz) with a Intermediate frequency IF of 38.9 MHz. The internal oscillator of the Tuners must therefore have frequencies between 87.15 and 894.15 MHz can generate.

The step width P for the internal oscillator frequency was chosen with 0.25 MHz, so that equation (2) for the two the above channels gives the following results:

Calculate by changing the number N between the above The tuning of every television channel in the VHF or UHF band with a maximum error of 125 kHz.

Since the use of this frequency range is imperfect, the tuner 2 has two band switching inputs for supplying band change signals U (UHF / VHF) and B (BIII / BI), which ensures that only the required bands are detected.

The first divider 3 is a high speed divider of the ECL type which divides by 64 (type SP8750). The second divider 4 is a programmable divider of the TTL type, which can work with frequencies up to approximately 15 MHz (3 × SN746S191). The circuits 5, 6 and 7 consist of an integrated circuit of the type SP8760 with a 250-kHz quartz and a divisor N₂ = 64, so that the comparator circuit 5 operates at a frequency of 3906.25 Hz, which corresponds to a quarter of the line frequency .

The amplifier and filter circuit 8 serves to raise the output level of the comparator circuit 5 (max. 5 V) to the level required by the tuner 2 (max. 30 V) and for optimum filtering and for optimal conditions with regard to the speed of the guide phase locked loop.

The purpose of the circuits 11 and 12 is to generate the divisor N and the band change signals U, B for tuning to certain television broadcasting stations based on the data indicating which signals should be tuned to and which are either entered by an operator on the keypad of control unit 10 or retrieved from memory circuit 12 .

As FIG. 2 shows, the memory block RAM2 contains registers K, S, C and F. For the tuning to a predetermined station, the following data, as will be described below, are stored in the registers: channel number in register K, tuning correction in register S, constant correction in register C and multiplication factor in register F, the multiplication factor being dependent on the step width between two adjacent channels.

The number N now results from the following equation:

N = (K × F + C) × 4 + S (5)

where K, F, C and S in this equation are the contents of the be relevant register or channel number K, the tuning corrections tur S, the constant correction C and the multiplication factor F are. In the calculation according to equation (3), the data in the registers of the second block RAM2, the arithmetic operations as a result of elementary operations  (Additions and shifts) are performed using the computing circuits (ALU) of processing unit (CPU) according to the programmed commands in block ROM.

The constant correction (C) and the multiplication factor (F) only depend on the selected band. Furthermore, K is the channel number according to the mentioned standardization, while S has a constant initial value S _c , which can be changed for fine tuning corrections (in contrast to nominal value tuning), namely to bring about small changes in the frequency of the internal oscillator compared to the video bandwidth. The following table applies:

Table 1

If you take channel 69 as an example, then guide the values of table 1 in connection with equation (3) to the following result:

N = (69 × 8 + 338) × 4 + 16 = 3576 (6)

which is a frequency of 894 MHz for the internal oscillator (Equation (2)) corresponds or the optimal match to the Channel 69 with a slight shift towards the Video carrier.

By simply changing the channel number (K) in the register K er you only keep all the frequencies that are far away correspond to visual channels, d. H. an 8 MHz spacing in the UHF band and a 7 MHz spacing in the VHF band. This follows from the equations above.

Based on the selected channel number will be automatically of the data that can be stored in the memory block ROM are stored, predetermined additional data F and C selected, as well as the band switching signals U and B, and according to Table 1.  

The tuning correction S, on the other hand, can be changed between a minimum value of 0 and a maximum value of 31, in accordance with a detuning of roughly ± 4 MHz compared to the nominal value. In this way, minor tuning corrections are made possible, which in some cases are necessary to compensate for distortions on the transmission channels and for tuning to transmitters that do not transmit at a standard frequency. The calculation according to equation (3) takes place in a purely binary form, a number of auxiliary registers also being used for partial results RX. The value for N obtained on the basis of the calculation is given together with the results for the signals U and B (14 bits in total) to the connections of the output circuits, the eight bits of lower value of the value N being transmitted to the output circuit PA while the four higher order bit of value N and the binary signals U and B are applied to the outputs of the second output circuit PB. The channel number K, which is contained in the relevant register K, is displayed by the display system 9 in two digits. The content of the channel register K and the tuning register S is also stored in two cells RA and RB of the block RAM2, so that when the television is switched on again it can be automatically tuned to the channel last switched on.

Using suitable control buttons on the control unit 10 , it is possible to tune to a transmitter in five different ways. In addition, the tuning corrections and other data can be saved for ten preferred stations.

Typically, processing unit 11 executes a main keypad reader program (a sequence of instructions stored in block ROM) to determine the presence and type of input data.

If one of the additional control buttons I, D, R₁, R₂ or R₃ is pressed, then the corresponding coded input data are stored in the register MO, which identifies the operating mode. In each of these operating modes, the data entered on the control unit 10 via the numeric keys are processed in accordance with a predetermined subroutine. The subroutine called by pressing the control key I is that data from registers K _i and S _{i are transferred} to the channel register K and the tuning register S, respectively. The command is executed after one of the numeric keys 0 to 9 has been pressed by the calculations are carried out in accordance with equation (3) and by taking into account the tuning correction S _i, the tuning to the transmitter which corresponds to the channel number K _i takes place.

The display system shows in addition to the two digits, which the Form channel number, also the numbers of the pressed button and a symbol (I), which corresponds to the respective operating mode speaks.

The above-described operating mode, in which the contents of the memory cells are scanned, is referred to as indirect tuning and corresponds to the selection of one of ten preferred channels, the data of which are stored in block 1 RAM1, as will become clear below.

The control key D enables a direct storage of a Program data via the keypad into the register K, the coded input data directly into this register be transmitted.

The command (given by a control key) is always then executed when a number key is subsequently pressed. The tuning to a selected channel takes place only when the numbers for the tens digit and the ones digit for the channel number entered in this order (if necessary the zeros must also be entered) by the usual Calculations with the contents of registers K, S, C and F by  be performed. As with the operating mode explained first, a symbol (D) is displayed again in addition to the channel number, which in this case is the "Direct tuning corresponds.

With direct voting, there is an immediate vote to a station by following the The channel number of the relevant standard mentioned at the beginning enter the TV channel using the keypad.

In the two operating modes described above (indi correct and direct vote) can correct the Ab tuning to + or - by repeatedly pressing the + button or button can be brought about.

If an operation of the + or - button is detected, then this causes an increase in each case via a subroutine or reducing the content of the register S for the fine mood, whereupon the usual computer program again is performed.

The correction of the vote is done in succession steps of 250 kHz, up to a maximum Detuning of ± 4 MHz. A tuning correction affects normally the current operating mode is not (Re gister MO), so that later the vote on new stations can be done while maintaining the same operating mode.

Regardless of the question of whether tuning corrections have been made or not, the data can be saved at the  two modes of operation "direct voting" and "indirect Ab mood.

Pressing the control key M transfers the data from the registers K and S to the registers K _i and S _i . This command is executed after pressing one of the number keys (i = 0 to 9). The operating mode is not affected by this and there is no change in the output data (N, U, B) or the data transmitted to the display system.

In the way described it is possible to get the data from ten save preferred stations, which are later in the Be drive mode "indirect voting" can be easily called can.

If the control key R₁ is pressed, then it generates a coded input signal, which causes the data in the K _i and S _i registers to be transferred in pairs automatically and in succession to the corresponding registers K and S, whereupon the usual computer programs are executed.

The function of the circuit according to the invention is in this Case very similar to the "indirect voting" mode. Pressing the number keys is replaced by the fact that the content of one of the RX registers is automatically increased by 0 to 9 is increased. The scanning speed is one Timer register T determines which is programmed that there is a delay of about 2 seconds.

The operating mode explained above is called "more indirect  Search ".

An additional feature in this case is that special data are entered in a switching register INT, so that the automatic search when you press the + - or - button is automatically interrupted. In addition, the + Key and the - key operated to the contents of the register RX to increase or decrease, which is already for the automatic search was used. The functions of Control buttons I, D, M, R₂ and R₃ remain unchanged and interrupt the search by changing the operating mode and restoration of the contents of the switching register INT.

It is therefore in the "indirect search" mode possible to scan the preferred stations guide whose data is stored and the search to break when the desired transmission appears, after If desired, there is the option of manually searching in on upward or downward direction. By pressing the control key R₂ becomes a coded input signal that automatically generates the content of register K increased, whereupon the usual computer program takes place.

The function of the circuit is similar to that of the direct one Voting - the operating mode under consideration is called "more direct Search run "- but in the case under consideration one first sequence of numbers N is generated automatically, which the Correspond to channels to which, according to standardization Voting can take place, the search of which is just set channel goes out and only on the actually  occupied bands extends (2 to 4, 5 to 12, 21 to 69 etc.).

As with indirect search, it is possible to use automatic to interrupt the direct search and advance from To bring about by hand (suitable code to register INT). In this case the search speed selected is about 1 second per channel and is pre-selected by the T register give.

As for the last key to be explained, namely the control key R₃, so this generates a coded input signal indicating an increase in the content of the register S for results in fine tuning to the maximum value of 31. For each increase in the content of the register S, a rake is made program carried out until finally when this maximum value is reached, the content of register K increases (2 to 12, 21 to 69) and the content of register S at the beginning value is reset.

In this way a second sequence of all numbers N is generated and a complete search for all receivable Frequency bands with a step size of 250 kHz and with a speed of 4 seconds per channel (programming of the register T).

In this case too, as in the previous cases, the automatic search is interrupted and the search of Hand resume (+ and - buttons) using these buttons in the case considered have the same effect as an Ab voice correction.  

The mode of operation described above is called "continuous liche search "or as" search according to the norm speaking transmitters ".

After each type of search is in the invention Circuit a storage of the corresponding data in the previously described possible.

The various operating modes are now described below the circuit according to the invention in connection with a possible application of the same when using a micropro cessors and with reference to flowcharts showing the Specify basic functions, are explained in more detail.

In particular, Fig. 3 explains a possibility for the implementation of the introductory logic functions when switching on the circuit for checking the selection and implementation of the above-described modes.

Specifically, when switching on, a signal "ON" is first transmitted to a block 100 which determines the input or output function of the programmable input / output connections of the processing unit 11 , which is accommodated in a microprocessor unit, for example.

In other words, with the help of block 100, those connections are established which run in FIG. 1 from the processing unit 11 to the circuits 2 , 4 and 9 and which are thus output connections, while the connections between the processing unit 11 and the control unit 10 represent input connections with respect to the processing unit.

Another function of block 100 is to provide circuit 107 with a direct output connection to block 108 when the circuit begins to operate.

From the output of block 100 , blocks 102 to 103 are then activated, which, when the receiver is switched on, enable automatic tuning of the same to the channel last set, ie, switched on before switching off, while maintaining the previously selected tuning conditions.

In particular, block 101 corresponds to the deletion of the internal registers which are required for the subsequent calculations. According to block 102 , the channel number K and the tuning correction S for the station last switched on before the receiver was switched off are retrieved from the cells RA and RB which enable permanent storage and transferred to the registers K and S, respectively. Finally, according to block 103 , which is used to carry out the logical and arithmetic operations, starting from the data for K and S, the signals B and U are received, whereupon N is calculated using equation (3) and to the output connections of the output circuits PA , PB is placed while the number K is fed to the display unit 9 , which all happens according to a program which will be explained in more detail below.

The output program of the arithmetic and output block 103 starts a programmable timer according to block 104 , which in turn supplies an input signal RT1 for block 105 . According to this, the keypad of the control unit 100 is monitored and the key which may be pressed is identified, whereupon a corresponding code is generated which is stored in the register RX and is also displayed.

The output signal of block 105 is fed to a second switching block 106 , which has two outputs, one of which is connected to the input of block 105 for the input signal RT1, while the other is connected to the input of the first switching block 107 .

A test input of block 106 is connected to the second input of block 104 , so that the switch for block 107 is only set when block 104 delivers a signal "end of counting process", ie after a predetermined time interval of, for example, 0, 25 seconds. Accordingly, block 105 continues to "read" the keypad and waits for input signals, while block 107 and the blocks following it are activated only once every quarter of a second. In this case, block 107 , which was previously set by block 100 , supplies a signal to block 108 which checks whether the last key pressed was one of the number keys.

The signals from the yes output of the test block 108 are fed to the set input of the block 111 , while the signals from the no output of the block 108 activate a storage block 109 which fetches the data from the register MO and transfers it to the register RX1 and also saves the code assigned to the last key pressed into the MO register.

The output signals of block 109 activate block 110 , which is similar to block 108 and which checks whether the last key pressed is the + key or the - key.

If there is an output signal at the yes output of block 110 , a signal FINET is transmitted to the blocks to be described later, while output signals are transmitted from the no output to the set input of block 111 .

The blocks 111 to 113 form a chain for checking whether the register MO contains a code which corresponds to the "direct voting" or "indirect voting" or "data recording" mode.

Signals DIRET, INDIR or MEMOR are emitted to blocks to be described later via the yes outputs of these blocks, while the following block is activated via the no outputs of blocks 111 and 112 and an input via the no output of block 113 RICER signal is generated.

According to the diagram shown in Fig. 3, the function of the blocks in question essentially consists in establishing initial conditions for the system when the receiver is switched on, by tuning to the station last switched on, while the keypad is read out and a check is carried out to determine which operating mode was selected what is done with a given frequency to initiate tuning.

Fig. 4 shows schematically one of the ways to implement the types of operation, which were referred to above as "direct" or "indirect".

3 in detail, the signal produced diret FIG. Fed to the block 120, which is set thereby. According to block 120 , the initial data, in this case the number 16, are now entered into the register S ( FIG. 2), while according to block 121 the number corresponding to the last two digits pressed in the BCD code, ie as a binary-coded decimal number in the Register K is entered. In addition, following blocks 120 and 121 , block 122 is also activated, which delivers a code corresponding to the letter d to the display unit, which now indicates that one of the direct operating modes is present.

The INDIR signal, on the other hand, activates blocks 124 through 126 in a corresponding manner. These store the code of the last keyed number in the register RX2 and also send it to the display unit (block 124 ). They also transfer the data from registers K _N and S _N , identified by the content of register RX2, to registers K and S (block 125 ). Finally, the blocks mentioned ensure that the code corresponding to the letter I, which indicates the presence of an indirect mode of operation, is transmitted to the display unit (block 126 ).

The output of block 122 and the output of block 126 are both connected to the input of arithmetic and output block 123 , which has the same function as block 103 and supplies an output signal RT1 to block 105 .

FIG. 5 serves to explain one of the possibilities for storing the data of a channel on which a tuning was carried out.

In particular, the MEMOR signal generated in accordance with FIG. 3 sets the block 130 , according to which the code corresponding to the last key pressed is stored in the register RX2, and the block 131 , which checks whether this key is the one Key assigned to the storage process.

A signal from the no output of block 131 sets block 132 , which then stores the contents of registers K, S and RX11 in registers K _N , S _N and MO, respectively. A signal at the yes output of block 131 , on the other hand, sets block 133 , which checks whether the content of register RX1 corresponds to the code of the M key. A signal from the no output of block 133 sets a block 134 through which the content of register RX1 is re-stored in register RX11. The yes output of block 133 and the outputs of blocks 132 and 134 are combined and are used to generate the signal RT1 for block 105 .

In other words, when switching from an operating mode to the "data storage" mode (131 = yes, 133 = no), the information about the previous operating mode from the blocks shown in FIG. 5 is stored in the register RX11 when a numeric key is pressed (131 = no), the data for the channel that is currently being tuned to (channel number K, tuning correction S) are stored in the register pair K _N and S _N , which is identified by the number of the key pressed, while a switch back to the previously activated operating mode (RX11 → MO) is provided at the same time.

Fig. 6 is used to explain one of the possibilities for a station search, specifically for the selection of one of the two operating modes "search", the blocks for carrying out the search, which was referred to above as "indirect search", going into more detail are explained.

3 in detail, the signal produced RICER FIG. Fed to the block 140, which thereupon registers RX3 assigns to the content of the delay an initial value of 1 and the block 141 supplies a set signal. Together with blocks 142 and 143, this forms a chain for identifying the last key pressed.

At the yes outputs of blocks 141, 142 and 143 , signals RICER1, RICER2 and RICER3 are generated depending on the actuation of one of the control keys R₁, R₂ and R₃. The signals from the no outputs of blocks 141 and 142 each activate the following block, while a signal from the no output of block 143 again forms the RT1 signal for block 105 . The RICER1 signal activates block 144 , which together with blocks 145 , 146 and 147 forms a further chain for the identification of the last pressed key.

With the help of blocks 144 to 147 it is checked whether the key concerned was the R 1 key, a numeric key or the plus key or the minus key. Signals at the no outputs of blocks 144 to 146 each activate the following block.

A signal from the yes output of block 144 sets block 148 , which in turn sets switch block 107 for the output of signal RICER1 and reduces the content of delay register RX3 by one.

The output signal of block 148 also sets block 149 , which checks whether the content of register RX3 is now 0. If this check results in a signal at the no output of block 149 , then the signal RT1 is fed to block 105 . A signal at the yes output is fed to a block 150 , which causes the content of register RX2 - a decimal number - to be increased by 1. Block 150 also provides a set signal to the block chain with blocks 151 through 153 , where:
block 151 transfers the contents of those registers K _N and S _N identified by the content of register RX2 into registers K and S, respectively;
block 152 assigns an initial value of 16 to the content of the delay register and transmits the code for the letter r (search) and the content of the register RX2 to the display unit;
block 153 , which is identical to block 123 , carries out the calculations and supplies signal 105 to block 105 .

A signal at the no output of block 149 and at the yes output of block 145 also lead to the generation of the signal RT1.

The signals from the yes output of block 146 are fed to the input of block 150 . The signals from the yes output of block 147 are fed to block 154 , which decreases the decimal number stored in register RX2 by 1 and also supplies signals to the input of block 151 . Finally, the signals from the no output of block 147 set block 157 , which sets switch block 107 , one output of which is connected to block 108 , and which also sends signal RT1 to block 105 .

The mode of operation of the blocks shown in FIG. 6 can be summarized as follows:
Blocks 141 to 143 are used to identify the type of search. If the control key R 1 was actuated for the indirect search run, then block 144 initiates an automatic search run (answer signal Yes) by blocks 148 through 150 causing the content of register RX2 to be advanced automatically, each time after a delay interval, which is specified by the time register RX3, so that all the stations whose data were previously stored in the memories are scanned one after the other.

If a number key is pressed, the automatic search is interrupted (block 144 = no, block 155 = yes) and the search is continued every 0.25 seconds (switch block 107 supplies signal RICER1). If one of the keys + or - is pressed, a search cycle is carried out manually, while if one of the operating mode selection keys is pressed, a switch back to predetermined operating mode conditions (resetting of block 157 ) takes place.

FIG. 7 serves to explain a possibility of tuning to transmitting stations using one of the operating modes described above as "direct".

The arrangement of the blocks is the arrangement of the blocks for the Signal RICER1 very similar, so that only the differences in the individual are described in detail.

The RICER2 signal activates a chain that strives for blocks 164 through 167 , which blocks determine in the same manner as blocks 144 through 147 which type of key was last pressed.

A signal from the yes output of block 164 (control key R₂ ge pressed) sets the block 168 , which in turn sets the switch block 107 in such a way that the signal RICER2 is generated at its one output, which also has an initial value of 16 for the content of the register S specifies which further reduces the content of the delay register RX3 and which finally sets the block 169 which checks whether the content of this register is 0. A signal from the yes output of block 169 successively activates block 170 , which, like block 123, performs the usual calculations, block 171 , which causes the decimal value in register K to be increased from 2 to 12 and then from 21 to 65, and so on ., and finally block 172 , which assigns the delay register the value 8 typical of this type of search and also feeds the signal RT1 to block 105 , which also has the no output of block 169 and the yes output of the block 165 (numeric key) is fed.

A signal from block 166's yes output (+ key) activates block 170 and subsequent blocks, while a signal from block 166's no output activates block 167 . A signal from the yes output of block 167 activates block 173 , while a signal from the no output of block 167 activates block 175 , which sets the output of switch block 107 connected to block 108 and generates signal RT1.

Block 174 serves to increase the decimal value in register K in the ranges from 65 to 21 and from 12 to 2 and is activated by block 173 , which is identical to block 123 and which generates the signal RT1.

The operation of the blocks according to FIG. 7 is very similar to that of the blocks according to FIG. 6 with regard to the logical decisions and the sequence of operations. The search is automatically initiated and interrupted if any key other than the R2 key is pressed. Furthermore, when the pressed key is not a mode select key, the blocks are prepared for manual advancement in both directions, in this case for advancement from one receivable standard channel to the next.

FIG. 8 serves to explain one of the possibilities for a tuning on stations using a search method, which was referred to above as "continuous". Also shown in FIG. 8, the blocks are again very similar arranged as shown in Figs. 6 and 7, so that a more detailed description is to be limited again to the differences.

The chain of blocks 184 to 187 for determining the type of the key last pressed is activated by the signal RICER3.

An output signal from the yes output of block 184 (key R₃ pressed) is fed to block 188 , which sets the output of switch block 107 , at which the signal RICER3 appears and which supplies a signal to the input of block 189 . This reduces the content of the register S by one unit, namely for the channels of the UHF band from 0 to 31 and for the channels of the VHF band from 0 to 27.

From the output of block 189 , block 190 is set, which checks whether the content of register S is zero. A signal from the yes output of block 190 activates block 191 , which causes the decimal number in register K to increase (in exactly the same way as block 171 in FIG. 7). The output of block 191 is connected to the input of block 192 which informs the display unit that the standard channel frequency (S-16) has been departed from and which activates the arithmetic and output block 193 . Block 193 is identical to block 123 and supplies the signal RT 1, which is supplied in addition to that from the yes output of block 185 (numeric key).

The yes output of block 186 (+ key) sends a signal to the input of block 189 . A signal from the yes output of block 187 (--key) successively activates block 194 , which reduces the content of register S from 31 to 0 for the UHF channels and from 27 to 0 for the VHF channels, and that Block 195 , which checks whether the content of register S is already zero.

The signals from the yes output of block 195 are fed to block 196 which causes the decimal value in register K to decrease from 65 to 21 and from 12 to 2 and applies a signal to the input of block 192 which also receives the signals from No outputs of blocks 190 and 195 are supplied. Finally, a signal from the no output of block 187 sets block 197 , which in turn sets the output of switch block 107 connected to block 108 and also supplies the signal RT1.

In this case too, the operation of the individual blocks with regard to the logical decisions and the sequence of operations is very similar to that according to FIGS. 6 and 7. Pressing the R₃ key initiates an automatic search (block 188 etc.), which is interrupted by pressing one of the other keys, which either initiates a different operating mode (output signal from block 197 ) or a manual search in both directions ( Output signal at the yes output of blocks 186 and 187 ).

Blocks 189 and 194 , which is typical of this type of search, perform a scan in steps of 250 kHz with respect to the transmission channels, at the end of which blocks 191 and 196 , which are typical of the blocks for direct search, are activated to scan all standard channels.

In this case, a manual search corresponds to one 250 kHz step width for fine tuning correction a station, but without a limitation of the deviation. With this type of search it is therefore possible to do it yourself find a station that is not at a standard frequency send and manually vote on these stations feed, it is then of course also possible to ent storing speaking data, if desired, and according to the procedure already described.

Fig. 9 is used to explain one of the possibilities for performing a tuning correction for a station to which the receiver was tuned in the course of one of the operating modes already explained above.

The FINET signal is sent to block 200 , which checks whether the pressed key is the + key. A signal from the yes output of block 200 activates block 201 , which increases the content of register S up to a maximum value of 31, while a signal from the no output of block 200 (- key pressed) activates a corresponding block 202 which reduces the content of the register S to a minimum value of zero.

The output signals of the two blocks 201 and 202 are fed to block 203 , which supplies the display unit with the data of a misalignment (S-16) related to the nominal frequency of a standard channel. Block 203 also sends a signal to arithmetic and output block 204 , which is identical to block 123 , and finally delivers signal RT1.

The blocks shown in Figure 9 operate as follows:
Pressing the + or - button repeatedly results in a detuning in steps of 250 kHz in one direction or the other, with the number of steps being displayed. It is possible to switch to one or the other operating mode by pressing the corresponding control button, for example to save the data available with an optimal coordination.

Fig. 10 shows a diagram to illustrate one of the possibilities for realizing the functions of the computing and output block, which was designated in the above-explained figures with the reference numerals 103 , 123 , 153 , 170 , 173 , 193 and 204 .

10, depending on a set signal which is received from an upstream block, block 210 is first activated from all blocks, which stores in register RA the data contained in register K, in accordance with FIG Standard television channel number for the broadcast channel on which the vote is to take place, the data from the register K also being supplied to the display unit, while the data stored in the register S are stored in the register RB.

Block 210 also supplies a signal to block 211 , with the aid of which the data contained in register K, which are encoded in the BCD code, are converted into purely binary-coded data in order to simplify processing. Block 211 sets block 212 . This selects the value for one of the constants F, C, U and B according to Table 1 in accordance with the number contained in the register K and stores the constants F and C in corresponding registers in order to then close the arithmetic processing block 213 activate, which calculates the number N according to equation (3). Block 213 in turn supplies a signal to block 214 , with the aid of which the number N and the constants U and B are transmitted to the two output circuits PA and PB. Block 214 also provides a set signal for the downstream blocks, as is clear from the figures described above.

As is clear from the above explanation, each time the blocks shown in Fig. 10 are activated, the tuner 2 is supplied with band switching signals U and B, depending on whether the selected channel to band I, band III or UHF band heard. In addition, a code corresponding to the divider factor N is fed to the second divider 4 . Furthermore, the number of channels for that channel on which the vote according to the aforementioned data follows, is displayed by the display unit 9 , while the number of channels K and the data associated with the tuning correction S are stored in the registers RA and RB of the permanent memory. This data is sufficient for the blocks of FIG. 10 to fully identify the tuning condition.

If the television receiver is switched on after a switch-off or a power interruption, it is possible, as described in connection with FIG. 3, to automatically set the tuning conditions last set again. In this connection, it was pointed out that the sequence of basic operations to be carried out by the processing unit 11 , ie the program, is stored in coded form in the ROM memory part of the memory circuit 12 .

To improve understanding of the present invention this memory circuit will now be described in more detail, which is used in connection with a microprocessor, from a central processing unit of the type MCS6502 and two connected MCS6530 / 002 units and MCS6530 / 003 is constructed.

The memory circuit under consideration essentially consists of a link matrix with a 1000 × 8 format, from input and address decoding circuits and from output buffer scarf exercises.

Each individual connection can either be open or closed and thus represents a permanent basic data unit (bit) in the form of a 1 or 0. Each group of eight compounds, which are addressed by one of a thousand address input Combinations can be controlled, also provides a basic command or a word (byte) with eight bits. By creating all permissible address-input combinations to the input can conclude all data in the ROM memory section  are stored, at the outputs in the form of one 8-bit command can be obtained.

The connection matrix can either be in the course of a masking ver driving in the manufacture of integrated circuits (ROM) be produced or with the help of a connection registered Procedure (PROM = programmable read-only memory). For the be sought embodiment of the present invention the individual compounds in Tables 2 to 10 listed summarized, which apply to a recipient who alone is intended for the reception of transmission channels in the UHF range. In tables 2 to 10 the left columns show the Addresses in hexadecimal code, while the right columns denote the State of the connections of the assigned memory cells demonstrate. A 1 corresponds to an open connection, which leads to a corresponding logic "1" at the output, while a 0 corresponds to a closed connection.

Since each memory cell consists of eight connections, its content can be represented by a sequence of eight binary numbers. For simplification, however, the hexadecimal code was given in tables 2 to 10, for example the code EA for the base 16, which corresponds to the binary code 11101100 for the base 2 and indicates that the connections 1, 2, 3 in the memory cell concerned , 5 and 6 are open while the other connections are closed.

Table 2

Table 3

Table 4

Table 5

Table 6

Table 7

Table 8

Table 9

Table 10

The preceding tables 2 to 10 contain in coded Form a possible basic program based on the block Functions explained in diagrams using the described microprocessor system, whereby the following assignment applies:

Table 2 diagram according to FIG. 3 (switching on and selection of the operating mode)
Table 3 diagram according to FIG. 6 (search selection and indirect search)
Table 4 diagram according to FIG. 7 (direct search)
Table 5 diagram according to FIG. 8 (continuous search)
Table 6 diagram according to FIG. 5 (data storage)
Table 7 diagram according to FIG. 4 (direct and indirect coordination)
Table 8 diagram according to FIG. 9 (fine-tuning)
Table 9 diagram according to FIGS. 3 to 9 (general operating functions)
Table 10 diagram according to FIG. 10 (calculation and generation of the output signals).

In other words, the tables above contain all the commands a microprocessor system needs to do all perform the functions described above for voting on a television station in the UHF band is required are, with the exception of reading the control buttons field and the control of the display unit, since this radio functions of the MCS6530 blocks.

It should be particularly noted that, in accordance with FIG. 2, the memory blocks RAM1, RAM2 and ROM are separated and called with the addresses 0000, 0020 and 0400 in order to set or release the various circuits required. In the exemplary embodiment under consideration, the memory block RAM1 is an MNOS memory which is suitable for permanent storage of the data. In certain circumstances, however, it can also be advantageous to use a CMOS memory with low power requirements in conjunction with a buffer battery. In this case, the data stored for the individual channels are also prevented from being deleted in the event of a power failure or a power failure.

It is also worth mentioning that this memory also the Register contains RA and RB, which means that when turned on the recipient automatically votes on the last one received station can take place.

It is understood that above only a preferred end management example of the invention was explained and that Expert, based on this embodiment, numerous Opportunities for changes and / or additions to bids stand without the basic idea of the invention would have to leave. For example, a special 8-bit microprocessor system with separate central unit and separate read-only memory. It can however other types of microprocessors are also advantageous are used, for example microprocessors with several internal RAM registers (usually 64) or microprocessor Ren of the so-called monochip type, which in addition to the read memory (ROM) also internal random access memory (RAM) and an internal clock generator. Can also  16-bit microprocessors can be used.

Based on the basic concept according to the invention can also additional functions can be easily implemented at for example a digital time display and a time pro Programmed switching on of transmission channels whose data is saved chert are, for this purpose corresponding additional Buttons must be provided.

In an embodiment of the invention, it can also be advantageous to provide the receiver with a remote control, wherein in this case a control keypad similar to that described is to be provided on the portable transmitter part of the remote control. Could avoid two separate control keypads also on the receiver housing a recess with electrical Contacts can be provided in which the transmitting part of the remote control could then be inserted when an operation is desired directly on the device.

In television receivers according to the invention, it can also be useful when looking at the receiver after certain manufacturing steps taken for life expectancy and reliability are important, preferably indirectly with regard to the automatic Search run checks after the data for the controllable Transmission channels are stored, with the receiver in the norma len reception state is maintained and with a video signal however, using different test patterns synchro is standardized to so-called burn-in effects (print effects) to avoid the picture tube.  

The devices according to the invention can also be used as auto Matic test instruments for testing, setting and measuring be used in the manufacture of a receiver.

Claims (38)

1. Circuit arrangement for tuning a television signal receiver using a phase-locked feedback (PLL system) with

• - An oscillator ( 2 ) variable frequency, the frequency of which is electrically controllable;
• - A frequency stable reference oscillator ( 6 ) fixed frequency;
• - A phase-frequency comparison circuit ( 5 ) for generating an elec trical error signal which is proportional to a frequency difference and the oscillator ( 2 ) is supplied with a variable frequency to control its frequency;
• - A frequency counter ( 4 ) which is programmable with a variable number N and is connected to the comparison circuit ( 5 );
• - a read-write memory ( 12 , RAM1), as a storage device which is able to store data over a long period of time;
• - An input device ( 10 ) with buttons for generating electrical control commands;
• - Means for manual fine-tuning in the sense of changing standard reception frequencies to which corresponding television channels are assigned;
• - A device ( 9 ) for displaying the channel number of the currently selected television channel and
• a microprocessor ( 11 ) which receives the electrical control commands from the input device ( 10 ) and forwards the assigned channel number to the frequency counter device ( 4 ) and makes them visible on the display device ( 9 ),

characterized in that the microprocessor ( 11 ) on the display device ( 9 ) also makes a numerical indication of the size of a desired deviation vis-à-vis a defined, standardized transmission frequency visible in addition to the channel number, the desired deviation either in a manually carried out deliberate detuning or in an automatic fine search results in which the microprocessor ( 11 ) searches all reception frequencies in frequency steps that correspond to a fraction of the distance between two adjacent channels. 2. Circuit arrangement according to claim 1, characterized in that the microprocessor in dependence on one first control command generates a first sequence of numbers to form an entire band of TV channels in steps smaller than the standard Adjacent channel spacing and that the microprocessor is dependent on one second control command can be advanced by one search step. 3. Circuit arrangement according to claim 2, characterized in that the microprocessor in dependence on one third control command generates the second sequence of numbers and that the micro processor can be controlled by a fourth control command such that it Generation of the second sequence of N numbers depending on the third Control command automatically interrupts.   4. Circuit arrangement according to claim 3, characterized in that the microprocessor by a fourth control command to generate the second sequence of numbers can be set. 5. Circuit arrangement according to one of claims 1 to 4, characterized in that the storage device is a permanent storage direction is formed. 6. Circuit arrangement according to claim 5, characterized in that the microprocessor when the Emp catches from the storage device the data that the before the Ab switch last switched on television channel are assigned from the Spei and reads out the number N for the last vote set television channel. 7. Circuit arrangement according to one of claims 1 to 6, characterized in that the microprocessor has the number N in dependence of the data assigned to the television channel to be set, and calculated depending on additional specified data. 8. Circuit arrangement according to claim 7, characterized in that the number N is calculated by the microprocessor according to the following equation: N = (K · F + C) · 4 + Sw wherein:
N the number to be calculated, K the number of television channels that can be received in accordance with the standard, F the number of steps between two standardized after-channel channels, C a constant that depends on the specified television channel standard, S a variable number that enables changes in the number N for the purpose of tuning changes, which are significantly smaller than the bandwidth of the standardized frequency channels. 9. Circuit arrangement according to claim 8, characterized in that the data that the television to be tuned are assigned to channels and in digital form in the storage device can be saved, the sizes are K and S.   10. Circuit arrangement according to one of claims 1 to 9, characterized in that the step by step can be carried out automatically Search process can be interrupted by a fifth control command whose help at the same time a gradual continuation of the search by hand running process is feasible. 11. Circuit arrangement according to one of claims 1 to 10, characterized in that with the help of the microprocessor depending from a sixth control command depending on another encoded input signal received value for the number N by an amount is changeable, which is sufficient for a change of vote, which is essential is smaller than the bandwidth of the standard television channels. 12. Circuit arrangement according to one of claims 1 to 11, characterized in that the input device has a keypad, which has at least ten number keys, auxiliary keys for selecting the Operating mode and for the activation of circuits the circuit arrangement buttons and buttons that allow access to the receiver control points. 13. Circuit arrangement according to one of claims 1 to 12, characterized in that the display means further for displaying the Operating mode of the receiver is provided. 14. Circuit arrangement according to one of claims 1 to 13, characterized in that a remote control as the input device is provided, which can be connected directly to the receiver. 15. Circuit arrangement according to one of claims 1 to 14, characterized in that the microprocessor means for Emp catch, identify and save at least one of the control commands and for activating or setting appropriate devices. 16. Circuit arrangement according to claim 15, characterized in that the microprocessor has logical function blocks:

• a) a first function block ( 100 ) for determining inputs and outputs depending on an ON signal and for selecting a first output of a first circuit ( 107 );
• b) a second function block ( 101 ) for setting the storage device to zero;
• c) a third function block for retrieving from the memory device those data relating to the television channel last set before the receiver was switched off;
• d) a fourth function block ( 103 ) for arithmetically calculating the number N, namely on the basis of the data relating to the television channel to which the tuning is to take place, and on the basis of additional predetermined data, with the aid of which channel band data signals can be generated .

17. Circuit arrangement according to claim 15 or 16, characterized in that the microprocessor further comprises the following logic function blocks:

• a) a fifth function block ( 105 ) for receiving and storing control commands;
• b) a sixth function block ( 104 ) for controlling a second circuit ( 106 ), which is provided for the transmission or blocking of the control commands from the fifth function block ( 105 ) to the other circuits of the receiver.

18. Circuit arrangement according to claim 17, characterized in that the first circuit ( 107 ) receives the control commands from the fifth function block ( 105 ) and has a number of outputs which can be selected on the basis of at least two control components. 19. Circuit arrangement according to one of claims 15 to 18, characterized in that the microprocessor further comprises the following logic function blocks:

• a) a seventh function block ( 108 , 110 ) for determining whether the control commands are assigned to the numeric keys or the auxiliary keys, a coincidence signal possibly being generated by the seventh function block or whether the control commands are assigned to the access keys;
• b) an eighth function block ( 109 ) for storing the operating mode as a function of the control commands received by the auxiliary keys and the access keys;
• c) a ninth function block ( 111 , 112 , 113 ) for performing an analysis as a function of the coincidence signal in an operating mode in which the memory content is replaced, and for activating a corresponding circuit of the circuit arrangement.

20. Circuit arrangement according to claim 19, characterized in that the ninth function block ( 111 , 112 , 113 ) has the following features:

• a) a tenth function block ( 111 ) for determining whether the selected operating mode directly affects the tuning of the receiver depending on the control commands;
• b) an eleventh function block ( 112 ) for checking whether the selected direct voting mode corresponds to the scanning of the memory cells of the memory devices;
• c) a twelfth function block ( 113 ) for checking whether the selected operating mode corresponds to the storage of the data in the storage devices which are assigned to a television channel to which the tuning has already taken place and with the aid of which circuits can be activated by which an automatic or manual station search can be carried out.

21. Circuit arrangement according to one of claims 8 to 20, characterized in that integrated storage devices of the micro processor have a tuning register in which the size S is stored is that they have a first data register into which the constant size C is stored that they have a second data register in which the  Size F is stored in that they have a channel register in which the Channel number K is stored and that it has an operating mode register have, in which a control command is stored, the operated auxiliary assigned to buttons. 22. Circuit arrangement according to claim 21, characterized in that the microprocessor has a thirteenth function block ( 121 ), with the aid of which, depending on a signal received by the tenth function block ( 111 ), a certain initial value is specified in the tuning register, with the aid of which the control commands corresponding to the actuated number keys are stored in the channel register and with the aid of which computing and logic devices for activating the arithmetic calculation are activated. 23. Circuit arrangement according to claim 21, characterized in that the processing unit has fourteenth devices ( 124 , 125 ), with the aid of which, depending on the actuated number keys and depending on the eleventh devices received signals, at least part of the content of the permanent storage device in the tuning register and the channel register can be stored and with the aid of which computing and logic devices can be activated to carry out the arithmetic calculation. 24. A circuit arrangement according to claim 21, characterized in that the processing unit has fifteenth devices ( 130 , 132 ), with the aid of which, depending on the twelfth devices ( 113 ) and the coded input signals corresponding to the actuated number keys, the content of the tuning register and the channel register sters at least in a part of the permanent storage devices storable in order to store the tuning conditions for a selected transmission channel. 25. Circuit arrangement according to claim 24, characterized in that the processing unit has sixteenth devices ( 131 to 134 ), with the aid of which the coded input signal corresponding to the previous operating mode can be re-stored after the data of a selected transmission channel have been stored in the operating mode register. 26. Circuit arrangement according to claim 21, characterized in that the processing unit has seventeenth devices ( 200 to 204 ), with the aid of which, depending on a signal from the seventh devices used for checking, and from a fifth coded input signal, the content of the tuning register is changeable to a sufficient extent to bring about a change in the tuning that is substantially smaller than the bandwidth of the transmission channels, and to activate the computing and logic devices for performing the arithmetic calculation. 27. Circuit arrangement according to one of claims 21 to 26, characterized in that the processing unit eighteenth Einrich lines ( 141 to 143 ), with the help of which it is possible to check whether the coded input signals actuation of auxiliary keys for operating mode selection for an indirect search, and by scanning the cells of the storage devices for a direct search, by generating the first sequence of N numbers corresponding to the total number of broadcast channels receivable according to the specified standard, or for a continuous search, by generating the second sequence of N numbers for scanning the entire band of receivable transmission channels. 28. Circuit arrangement according to claim 27, characterized in that the processing unit has nineteenth devices ( 144 to 147 ) which can be activated by the eighteenth devices ( 141 to 143 ) and with the aid of which it is possible to check whether the coded input signals of the "indirect" operating mode Search ", the operation of numeric keys or the operation of access keys correspond, and with the help of which a first sequence of match signals can be generated. 29. Circuit arrangement according to claim 28, characterized in that the processing unit is constructed as follows:

• a) there are twentieth devices ( 148 , 149 ) provided, with the aid of which, depending on a first match signal from the nine tenth devices, a second output can be selected from the outputs of the first switch device ( 107 ), with the aid of which the content of a delay register can be changed a unit can be reduced and with the aid of which it can be checked whether the content of the delay register deviates from zero, and with the aid of which if the content of the delay register is zero, a first enable signal can be generated;
• b) twenty-first devices ( 150 ) are provided, with the aid of which the content of a point register can be increased by one unit as a function of the first enable signal or a second match signal from the nineteenth devices;
• c) twenty-second devices ( 154 ) are provided, with the aid of which the content of the point register can be reduced by one unit as a function of a third agreement signal.

30. Circuit arrangement according to claim 29, characterized in that the processing unit comprises twenty-third devices ( 151 to 153 ) which can be activated by the twenty-first devices ( 150 ) or the twenty-second devices ( 154 ) and which in two are identified by the content of the point register To transfer cells contained in the memory devices into the tuning register or the channel register, these two registers assigning a predetermined initial value to the delay register and activating the computing and logic devices. 31. Circuit arrangement according to one of claims 14 to 30, characterized in that the processing unit has twenty-fourth devices ( 164 to 167 ) which can be activated by the nineteenth device and with the help of which it is possible to check whether the coded input signals of the "direct search" mode ", correspond to the actuation of numeric keys and the actuation of access keys, and with the help of which a second sequence of match signals can also be generated. 32. Circuit arrangement according to claim 31, characterized in that the processing unit has twenty-fifth devices ( 168 , 169 ), by means of which a third output can be selected from the outputs of the first switch devices ( 107 ) depending on a fourth match signal from the twenty-fourth devices The content of the delay register can be reduced by one unit, the tuning register can be assigned a predetermined initial value and it can be checked whether the content of the delay register deviates from zero, and in the event that the content of the delay register is zero, by the twenty-fifth devices ( 168 , 169 ) a second release signal can be generated. 33. Circuit arrangement according to claim 32, characterized in that the processing unit is constructed as follows:

• a) there are twenty-sixth devices ( 170 to 172 ) provided, with the aid of which, depending on the second enable signal or on a fifth match signal from the twenty-fourth devices, the computing and logic devices can be activated, with the aid of which the content of the channel register can be increased by one unit and with the help of which an initial value can be assigned to the delay register;
• b) there are twenty-seventh devices ( 173 , 174 ) provided, with the aid of which, depending on a match signal from the twenty-fourth devices, the computing and logic devices can be activated and the content of the channel register can be increased by one unit.

34. Circuit arrangement according to one of claims 14 to 33, characterized in that the processing unit has twenty-eighth devices ( 184 to 187 ) which can be activated by the eighteenth device and with the help of which it is possible to check whether the coded input signals of the "continuous search mode"", correspond to the actuation of numeric keys or the actuation of access keys, and with the aid of which a third set of match signals can also be generated. 35. Circuit arrangement according to claim 34, characterized in that the processing unit has twenty-ninth devices ( 194 to 196 ), with the aid of which, depending on a seventh match signal from the twenty-eighth devices, the content of the tuning register can be reduced by one unit, with the aid of which it can be checked is whether the content of the tuning register deviates from zero, and by means of which, in the event that the content of the tuning register is zero, the content of the channel register can be reduced by one unit and an eighth over-signal can be generated by which the computing and logic devices can be activated. 36. Circuit arrangement according to claim 35, characterized in that the processing unit has thirtieth devices ( 188 to 191 ), with the aid of which a fourth output can be selected from the outputs of the first switch devices as a function of a ninth agreement signal from the twenty-eighth devices. with the help of which the content of the voting register can be increased by one unit, and with the help of which the content of the voting register can be checked to determine whether it deviates from zero, and with the aid of which, in the event that the content of the voting register is zero, the content of the channel register can be increased by one unit and a tenth match signal can be generated by which the computing and logic devices can be activated. 37. Circuit arrangement according to one of claims 28 to 36, characterized in that the processing unit ( 31 ). Devices ( 175 , 157 , 197 ), with the aid of which a first output can be selected from the outputs of the first switch device ( 107 ) and a start signal can be fed to the fifth device ( 105 ).