DE2759039A1 - N-channel memory FET with floating memory gate - charged by programmed channel injection has p-zone on drain zone - Google Patents

Abstract

n-Channel memory FET ahs a floating memory gate, in which the charge is changed by programmed electron-injecting channel injection, and a control gate, with capacitive effect on the memory gate, as in DT 2445137, esp. for programmed memories of telephone systems. Improvement is that a p-doped auxiliary zone is formed on the drain zone, forming a diode in series with the source-drain section. The drain zone potential floats, the drain terminal being connected to the auxiliary zone and the entire source-drain current always flowing through the auxiliary zone to the drain terminal. Device can act as memory cell without additional selective FET and without complicated forming of both gates. Also, the application of laps to the control gate allows improvement of electrically controlled erasure.

Description

n-channel safety FET.

The invention relates to a development of the main application / in the main patent P 24 45 137.4-33 specified objects, all of which have a certain n-channel memory FETs relate to an n-channel memory FET with at least a gate, namely with a floating gate surrounded on all sides by an insulator Storage gate, in which the electrons injecting charge reload the storage gate Canal injection - d. H. Reloading through strongly accelerated in its own conducting channel and electrons that are heated up as a result, which because of their heating up by a in the source-drain direction effective electric field the energy threshold to the conductivity band of the insulator Overcome and thereby get to the storage gate - is exploited with the task of the channel injection for programming, i.e. charging the memory gate on an opposite denfq state negative potential, so that the memory- *) uncharged gate after this charging by means of its negative charge by influencing the source-drain current acts in an inhibiting manner on the source-drain path, whereby it has an additional, has a terminal having controllable control gate, which is capacitive the storage gate works.

This repeatedly programmable, i.e. rechargeable, and repeatedly, In particular, they can be erased with optical or electrical means, i.e. they can be discharged n-channel memory FET is programmed by the negative charging of its Memory gate controlled in the strongly blocking state. In doing so, he is with low Operable voltages, e.g. compared to memory FETs, which have the avalanche effect exploit for charging. After its deletion, however, it can be mostly unintentional Wise to manage his channel, especially in case his storage gate is excessively discharged, So it was positively charged instead of a still non-conductive channel to have.

To be able to allow such excessive discharges without stopping the operation a memory matrix that contains such n-channel memory FETs as memory cells, by shortfalls, formed by the conductive channels of such cells there are different possibilities.

In each memory cell in series with the channel one can add another, Attach controllable channel area, whereby the space requirement accordingly increases sharply, which is sometimes annoying - see e.g. the suggestion in the registration P 27 44 113.0-33. One can also require relatively tight tolerances, more complicated, forms for the memory gate and the control gate are correspondingly more difficult to manufacture where the memory gate only affects part of the channel - see e.g. DE-OB 25 13 207.

There is already a coupling arrangement known as the relay coils Contains matrix cells, with undesired short circuits via self-conducting coils by means of an additional diode in series with the respective coil were avoided per cell - cf. DE-AS 1 194 905. A production of such Relay arrangement in integrated technology is neither described nor intended there.

From an integrated manufactured arrangement with memory function, which contains only one diode as a cell, is known to contribute to its structure nothing but these diodes are required - see DE-OS 2 039 027. But it is here not a repeatedly erasable and programmable arrangement.

By IBM Techn. Discl. Bull. 15 (Feb. 1973) 2922-2924 is a P-channel memory FET is known, its memory gate when programming by means of the avalanche effect is charged negatively, whereby the charged FET has a conductive channel. In the drain D2 there are two, separated next to one another and as close as possible to the memory gate n-doped auxiliary zones attached which, when erasing, generate an avalanche effect serve, whereby heated free charge carriers flow to the memory gate and this unload. These auxiliary zones are not required per se in reading and writing operations, which is why the source-drain current here instead of fully via one of these two auxiliary zones at least to a considerable extent via the channel's in each cell in addition selection FET connected in series to the gate terminal Y flows. The potential of the Drain D2 does not float constantly, but drain D2 is when reading and writing Supplied with its own potential via the selection FET by the selection FET Drain area itself represents a controllable connection of the VP channel memory FET. Moreover is this memory cell, the two auxiliary zones in addition to the memory FET and the selection FET contains, quite complex and takes up quite a lot of space.

The object of the invention is those with comparatively low voltages repeatedly programmable by means of channel selection, at least optically erasable, initially and in the preamble of the main claim specified n-channel memory FET cleverly designed in integrated technology so that it can be used alone as a storage cell, without additional selection FET and without complicated shaping of its two gates, can serve. The invention should be designed so that it also allows the attachment of Flaps on the control gate to improve an electrically controlled extinguishing allows.

This object of the invention is given in the characterizing part of the main claim specified measure solved.

The invention is based on the exemplary embodiments shown in the figures explained in more detail, wherein FIG. 1 shows a longitudinal section through an embodiment of the Invention, FIG. 2 shows a memory matrix, each with a single one according to the invention n-channel memory FET and FIG. 3 shows a modification of the drain region of the invention demonstrate.

By using the same reference symbols as in the main application These figures are the main patent going through the information in the main application / in the main patent understandable. The description that follows can now So limit yourself to the special features of the invention.

The n-channel memory FET shown in Figure 1 differs from the statements described in the main application / in the main patent mainly through the structure of its drain region D. In it is namely a p-doped auxiliary zone H attached, which is separated from the substrate HT on its entire surface. Between the p-doped substrate HT and the p-doped auxiliary zone H namely the n-doped Drain area D, which nowhere has its own connection to the outside. Instead of this the drain terminal A is connected to the auxiliary zone H, which is why the source-drain current in its respective whole size over the drain area D and over the auxiliary area H flows to the drain terminal D. The potential of the drain region D can therefore float and has a partly from the channel state, partly from the potentials on the substrate HT and potential dependent on the auxiliary zone H. When the pn junction between the auxiliary zone H is permeable, the potential of the auxiliary zone H is approximately the same as the potential of the drain region D - this is mainly the case during a source-drain current flows.

Figure 2 illustrates the effect of the auxiliary zone H of each n-channel memory FET. As an example, a matrix is shown with four memory cells T1 to T4, which can be can also be of any size, i.e. with more storage cells. The auxiliary zone H, together with the drain zone D, each forms a diode DLI shown in FIG until with the polarity that the memory gate state during programming and reading is uncharged desired Source-drain current 1, see i3 in Fig. 2, through the diode, here Di3, the relevant memory cell, here T3, can flow unhindered, if corresponding read potentials to the source, the control gate and the drain terminal the relevant memory cell are applied. If the storage gate is negatively charged, then no current i flows and the potential of the drain region of this memory cell flows can then make notes.

The auxiliary zone therefore does not hinder the reading of the selected memory cell. The same is the case with programming. Then it is also a positive one Potential across the auxiliary zone and the drain region on the in its conductive state controlled channel is applied until its memory gate is negative by means of channel inspection is charged and therefore the channel becomes non-conductive or in its non-conductive State is controlled. The source-drain flow direction is during reading and programming equal, so that in both cases the relevant auxiliary zone of the driven n-channel memory FET does not prevent.

The auxiliary zone prevents reading disturbances and reduces them Faults in programming, as explained below: When reading, only the memory cell controlled via specific column and row lines, in Fig. 3, e.g., T3, can be checked for their memory status. Whether a stream of Y'1 flows to X'2 or not, so it should only depend on the storage status of T3, not but from the memory states of T1, T2, T4. But if, for example, the n-channel memory FETs happen to be are excessively erased in T1 and T2 and are therefore - in itself undesirably - conductive Have channels and if T4 is not programmed, that is deleted or excessively deleted and therefore because of its control gate potential has a conductive channel, and if no diodes Dil to Di4 were present - then a forbidden current iv would flow through T1 - T2 - T4 and the flow of one Simulate the source-drain current through the actually controlled T3. This danger The more memory cells the matrix contains, the greater the pretense. Of the Prohibited current iv can, however, because of the auxiliary zones and the diodes generated by them Dil to Di4 does not flow.

In every conceivable way in which the forbidden electricity itself in a lot larger matrices would flow, he encounters a for him impermeable diode Di, in the example shown in FIG. 3, it is the diode Di2 of the cell T2. the Auxiliary zone H applied according to the invention in the drain region D thus prevents the called pretense of a source-drain current iV, which is apparently caused by the alone controlled cell T3 flows. The measure according to the invention is even allowed excessive erasure can be permitted without disrupting storage operations.

In addition, the diodes Di in particular reduce the so-called Neighboring word disturbance when programming: When charging a memory cell, e.g. T3, the positive drain voltage is also at the drain of the memory cell T1, its Channel, while programming the memory cell T3, via X1 itself into the non-conductive State is controlled. If the memory cell T1 is already programmed for its part is, there could possibly be an undesirable avalanche effect at its blocked substrate-drain junction occur, which cause a partial discharge of the memory gate of the memory cell T1 could. The here in the forward direction claimed diode Dii reduces this partial discharge due to the voltage drop across Dii. However, if the memory cell T1 should be excessively erased while the memory gate the storage cell T3 is negatively charged, the forbidden current could also iv via unintentionally conductive channels, here the memory cells T7, *) in Switching the edge electronics of the memory matrix would be undesirably increased and thereby the programming of the memory cell T3 would be endangered. The diodes But also here when programming, i.e. not only when reading, you prevent that Occurrence of this forbidden stream iv.

M) .T2, T4, occur, whereby the voltage drop Fig. 3 shows a Further development of the invention in which the drain region is shared by two different Subregions D, D 'is formed, both of which are n-doped and which are conductive to one another are connected. The conductive connection can, for example, be a metallic line Vh are formed, see Fig. 3. The conductive connection between the two subregions D, D 'can, however, also be produced in that both subregions are placed on the p-doped Substrate surface are attached next to each other that they are n-doped Touching partial areas directly. Then there is no effectively insulating pn junction between these adjoining subregions D, D '. Only if both sub-areas do not adjoin each other, there must be a special conductive connection Vh between them can also be attached.

This dichotomy of the drain area often has the additional advantage that the auxiliary zone H can be weakly - instead of strongly - p-doped without great difficulty can if the second sub-region D 'surrounding it is only weakly n-doped is. Through these two division so achieve that one can heavily n-dop the first sub-region D adjoining the channel, e.g. with it it is of low resistance and that you can still get a weak one without great difficulty Produce p-doped auxiliary zone H in the weakly n-doped second sub-area D ' can, e.g. to improve the characteristic, especially in the blocking range, of the diode Di.

The second, weakly n-doped sub-area D 'can therefore also be used in a special window of the thick oxide you, outside the thick oxide window of the actual source-drain path. Boundaries both sub-areas directly to each other, then one saves special lines Vh; you also save space. In any case, it is not absolutely necessary to extend the storage gate to the auxiliary zone to let reach.

The distance between the auxiliary zone H and the substrate HT, see the thickness of the drain region D and D 'in FIGS. 1 and 3 can be chosen differently.

If one chooses it greater than the diffusion path length, e.g. 8 then flows through the drain connection only the respective source-drain current. The source-drain current then has comparatively tight tolerances, which is the layout of the peripheral electronics at least for small matrices.

However, if this distance is chosen to be significantly smaller than the diffusion path length, e.g. 2 #, then the three-layer structure can be auxiliary zone H / drain area D or partial area D '/ substrate act as a bipolar transistor, especially if you use the p-doping the auxiliary zone H does not make it too weak. This structure represents an amplifier, namely one at the collector, i.e. substrate, generated deten emitter follower with very low output resistance. The drain area D or the sub-area D ' acts as the base zone of this transistor. The drain connection A does not only flow the entire source-drain current in question, but the correspondingly increased emitter current this structure. Such a dimensioning is particularly suitable when the read source-drain currents weak, the effective capacity of the connected Matrix lines high, the input resistance of connected sense amplifiers right kkin or the clock frequency with respect to the successive read cycles high are. In addition, in this modification, the dimensions of the n-channel memory FET, in particular its drain area D or Ds can be selected to be particularly small and thus space-saving manufacturable.

All of these explanations showed that one especially against excessive Build up suppressive memory matrices for erasure insensitive, forbidden currents that contain only the n-channel memory FET per memory cell. One can Plenty of these are more appropriate in a single column or in a single row Memory cells, e.g. T3, T4, with a single column switch or with a single one Activate the row switch, here X'2, instead of a selection FET in each memory cell or having to install an additional controlled channel in series with the part of the channel of the n-channel memory FET influenced by the memory gate.

The invention can be made, for example, in the following way: A thick oxide layer Du is first allowed to grow on p-conductive substrate HT. Thereafter a window is etched into the thick oxide layer along its entire width and length the later, actual source-drain path S-D of the n-channel memory FET, possibly now also over the later second partial area D ', so that the substrate HT is openly accessible again everywhere there. This also changes the shape of the canal, des Source area and the drain area or first sub-area set.

A first insulating layer, namely a thin oxide layer, is then left II, arise on this entire area of the window, e.g. with a thickness of 600 i.

A first polysilicon layer is then left, e.g. according to DE-OS 24 45 030 grow up, which one endows immediately or later and which one with high permissible Etches away tolerances again in such a way that the polysilicon layer region belonging to the memory gate G1 remains, tir; d that adjacent to the memory gate G1, over the later areas S and D strongly protruding edge layers, which are not yet etched away, lag behind. So the memory gate G1 remains behind together with it for the time being adjacent edge layers, these edge layers G1 'now parts of the later The source area S and the later drain D cover and themselves no specific size must have. The mask for carrying out this etching therefore does not have to be adhere to tight tolerances. These protruding edge layers are, for example, according to DE-OS 24 45 030, only later, as will be described later, etched away to finalize the memory gate G1. With the etching you can too further parts, e.g. one that is conductively connected to the memory gate G1, for electrically controlled discharge, leave behind the rag, see e.g. DE-OS 26 13 873.

Next, leave on the leftover areas of the first Polisilicon layer as well as on the still exposed parts of the first insulating layer 11 a second thin insulating layer I2 is formed, e.g.

with the thickness 500 i.

On this second insulating layer I2 or also on the thick oxide layer You let a second polysilicon layer grow flat, from which by etching away the control gate G2 is formed by means of a mask. By taking advantage of the same You can also mask those areas of the insulating layers I1, I2 and the Etch away protruding edge layers of the first polysilicon layer, which so far the later areas of drain D and source S covered so that the memory gate G1 and the control gate G2 are now particularly precisely layered on top of one another, what the reject rate is reduced and the production of particularly short channels is permitted.

One can then use, for example by means of ion implantation of the control gate G2 and the thick oxide layer Du as a mask, the n-doping of the areas Generate G2, D and S. Instead of using ion implantation, you can now generate the n-doping of these areas by diffusion in a manner known per se, in which an n-doping of the control gate G2 can be achieved at the same time. If man using ion implantation here, it was sufficient in itself also to use the mask in question to etch away the edge layers, but at least Remnants of the first insulating layer I1, if not the entire insulating layer I1 etch away more, and the n-doping of the source region S and the drain region D or from its first partial area through these remnants of the first insulating layer I1 to be attached through in the substrate HT. If necessary, the second sub-area can be provisionally D 'cover and after generating the first partial area D this cover again remove and now -e.g. by means of diffusion, if I1 is completely removed, or by means of Ion implantation through remnants of the first insulating layer I7 - a corresponding one Generate n-doping of the second sub-area D '.

The p-doping of the auxiliary zone H can now be generated using a mask. This p-doping can e.g. by means of this mask and ion implantation through over produce parts of the first oxide layer I1 that still remain through the auxiliary zone. As a mask for this doping, one can also initially cover the entire pane Generate another oxide layer, see. Fig. 1, in which one over the to be generated Auxiliary zone H etches a window that extends to the surface of the relevant drain area extends through it or is only less deep, see Fig. 1; through such a window the auxiliary area H can be generated, e.g. by means of ion implantation.

The use of ion implantation has been known per se Each has the advantage that one can determine the doping intensity, the depth of the invention, very precisely and also maintain the width and length of the area created in this way with tight tolerances can, with one additional through insulating layers can endow.

Maintaining such tight tolerances will be of particular importance if you want to spend little space on the invention.

On the entire disc, for example in the state shown in Fig. 1, can you can still grow a first protective oxide layer, in which you can use a window Attaches contacts for areas S, D and G2. By means of a metal vapor deposition can Now the connecting lines of the module, and finally above it make a second protective oxide layer.

Claims (10)

Patent claims oil. n-channel memory FET with at least one gate, namely with a floating memory gate surrounded on all sides by an insulator, in the channel injection that injects electrons to charge the storage gate - i.e. reloading through strongly accelerated in its own conductive channel and thereby heated electrons, which because of their heating by a in the source-drain direction effective electric field the energy threshold to the conductivity band of the insulator Overcome and thereby get to the storage gate - is exploited with the task of the channel injection for programming, i.e. charging the memory gate on an opposite the uncharged state negative potential, so that the memory gate after this charging by means of its negative charge by influencing the source-drain current acts in an inhibiting manner on the source-drain path, whereby it has an additional, has a terminal having controllable control gate, which is capacitive the memory gate works, according to application / patent P 24 45 137.4-33, in particular for Program memory of telephone systems, d u r e n g e n n n a n i e n e t that a p-doped auxiliary zone (H) is attached in the drain region (D) that this auxiliary zone (H) together with the connectionless drain region (D) one in series to the source-drain path (S - D) lying diode forms that the potential of the drain zone (D) in electrical terms, floating by the drain terminal (A) for conduction a source-drain current (i) is connected to the auxiliary zone (H) and the whole Source-drain current always flows through the auxiliary zone to the drain connection. 2. n-channel memory FET according to claim 1, d a -d u r c h g e k e n n z e i c h n e t that the drain region (D; Fig. 1) by two mutually conductive (Vh) connected subregions (D, D '; Fig. 3) is formed, of which the Channel-bordering, first sub-area (D) n + -doped and the other, second sub-area (D '), in which the auxiliary zone (H) is attached, is n-doped. 3. n-channel memory FET according to claim 2, d a d u r c h g e k e n n z e i c h n e t that both subregions of the drain are immediately adjacent to one another attached to the substrate. 4. n-channel memory FET according to claim 1, 2 or 3, d a d u r c h g It is not noted that the auxiliary zone (H) is surrounded by the substrate (HT) on all sides more (6po) than the diffusion path length (3P) away. 5. n-channel memory FET according to claim 1, 2 or 3, d a d u r c h g It is not shown that the auxiliary zone (H) from the substrate (HT) at least one place less (2 #) than the diffusion path length away. 6. A method of manufacturing the n-channel memory FET according to any one of Claims 1 to 5, g e k e n n -z e i c h n e t d u r c h the sequence of the following process steps: a. On a p-conducting silicon wafer as a substrate (HT), a relatively thick Oxide layer (Du) applied, in which a window extending to the substrate (HT), in which later the source-drain path (S-D) is to lie, is etched; b. a relatively thin first insulating layer (I1) is produced in the window; c. on a first polysilicon layer is deposited over the entire pane, which additionally, is preferably doped as part of process steps c or d; d. the first Polisiliziuischicht is formed by etching away so that essentially the area of the memory gate (G1) - and possibly one that is conductively connected to the memory gate, for discharging the storage gate serving lobe - remains, but adjacent to the memory gate (G1) initially still a protruding edge layer in over the later source region (S) and over the later drain region (D) regions reaches in; e. on the first polysilicon layer is a relatively thin second Insulating layer (12) produced; f. a second layer of polysilicon is applied over the entire wafer deposited, which in addition, preferably in the context of process step i, is doped; G. the second polysilicon layer is etched away by means of a mask shaped so as to leave the area of the control gate (G2); this second polysilicon layer can also be endowed now; H. with that for forming the second polysilicon layer The mask used in step g of the method is the mask over the later source region (S) and the later ren drain region (D) extending into the edge layers of the first Polisilicon layer and the parts of the first and second insulating layer that are not required (11, I2) etched away; i. an n-doping of the substrate (HT) on it exposed surfaces for producing the source region (S) and the drain region (D) is attached; k. the p-doping of the auxiliary area is determined by means of a mask appropriate; 1. a first protective oxide layer is created over the entire pane, in the contact window and contacts for the source (S), the drain (D) and the control gate (G2) are generated; the necessary connecting lines are created by means of metal vapor deposition manufactured; A second protective oxide layer is produced over the entire pane. 7. The method according to claim 2 and 6, g e k e n n -z e i c h n e t by the following modification of process steps h and i: h. Before or after this etching away is the second partial area (D '; Fig. 3) the drain area covered; i. here this n-doping represents the doping of the first sub-area; the coverage of the later second sub-area (D ') the drain is finally removed and the second sub-region is n-doped. 8. The method according to claim 6 or 7, g e k e n n -z e i c h n e t by the following modification of process steps h and i: h. With the same Mask the relevant edge layers are etched away, but at least remnants the first insulating layer (I1) are no longer etched away; i. through the remains of the first insulating layer (11) is carried out by means of ion implantation the n-doping of the source region (S) and the drain region (D) or its first Partial area attached. 9. The method according to claim 7 and 8, g e k e n n -z e i c h n e t by the following further modification of process steps i: i. Weakness n-doping of the second sub-area (D ') is applied by ion implantation. 10. The method according to any one of claims 6 to 9, g e -k e n n z e i c h n e t d u r c h the following modification of process step k: k. The p-doping is attached by means of ion implantation.