DE2534035A1 - ELECTRONIC CIRCUIT FOR A WATCH - Google Patents

Description

EBAUCHES S.A., Neuchätel / Switzerland

Electronic circuit for a clock.

The present invention relates to an electronic circuit for a quartz watch with a stepping motor and a Oscillator and subsequent frequency divider, which feeds a logic stage for controlling the motor.

It is known that one of the main problems in the manufacture of electronic clocks is the space required for
the parts of the electronic circuit as small as possible

MS / mp / 19/356 Case 147f

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keep. A significant proportion of the space required is attributable to the connections, particularly in the case of integrated circuits. It is therefore particularly important to keep the number of connections as low as possible.

The required number of connections or terminals is on the one hand given by the number of special circuit parts that are to be connected to the electronic circuit and on the other hand by the number of connections for checking and control. For example, it can be the To check the frequency of the oscillator, in particular a quartz, and / or to stop the clock to correct the time display.

In the case of a quartz watch with an analog display and a stepping motor the integrated circuit generally has two connections for the power supply, two connections for the Quartz, two connections for the polarized stepper motor and one connection for stopping or stopping the clock on. No special connection is provided for measuring the frequency of the crystal, because this measurement can be carried out at a connection point for the engine. A frequency reduced by the frequency divider appears at this connection of the quartz, from which the actual quartz frequency can be determined. One connection of the motor can do two things meet, namely on the one hand to control the engine and

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on the other hand to get the measurement of the quartz frequency.

The present invention is based on the object Reduce the number of connections in an electronic watch by making connections to the circuit that control it of the motor are also used to check one of the frequency divider derived frequency and / or to stop the clock and to reset to zero at least one stage of the frequency divider be used.

The invention is explained in more detail below with reference to exemplary embodiments which are shown in the drawing.

Figure 1 shows schematically an electronic circuit according to the invention,

Figure 2 shows the circuit according to Figure 1 with others Details,

Figure 3 is a diagram showing various in the circuit represents occurring pulses according to Figure 2,

Figure 4 shows a second embodiment and

Figure 5 is a .Diagramm in which various in the Circuit according to Figure 4 occurring pulses are shown.

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Figure 1 shows schematically the principle of a quartz watch with a polarized stepping motor. It has an oscillator 1 with a crystal 2 and the variable capacitor 3 for setting the crystal frequency. The oscillator 1 is connected to the input of the frequency divider 4, the output of which is connected to a logic circuit 5 for controlling a stepping motor shown schematically by the coil 7. A control stage 6 is located between the motor 7 and the logic circuit 5. The circuit parts described so far are common in quartz watches. In addition, two connections + V__ and - V _n _ are provided for supplying power to the circuit. To measure the frequency of the crystal, the frequency used for the measurement is fed from connection 8 of a stage of the frequency divider 4 to connection B of the motor 7. This measurement frequency can also be fed to the other connection A of the motor 7 in order to be fed from there to a comparison circuit 9 to become _t . which compares this frequency with another frequency called "reading frequency", which is taken from the connection 10 of one of the stages of the frequency divider 4. A switch 11, which allows the stepping motor of the clock to be stopped or shut down, is connected between the connection + V _, _ and the connection A of the motor 7. The output of the circuit 9 can emit a reset signal RES for resetting part or all of the stages of the frequency divider 4 to zero.

During normal operation, that is, when the switch is open, incremental pulses pass through the A connections

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- Jf - _

and B to the stepper motor 7. Between the incremental pulses the measuring frequency fed to connection B can be measured either at this connection or at connection A. because the resistance of the motor is low, so that the measuring frequency from connection B to connection A got.

The comparison circuit 9 allows the presence or absence of the measurement frequency at connection A to be determined between successive drive pulses in the rhythm of a read signal. When the switch 11 is open, the measuring frequency transmitted to the connection B is also transmitted via the motor winding to the connection A and to the comparison circuit 9, and the comparison circuit is designed so that it does not emit a reset signal RES at its output when the measuring frequency is received . If the switch 11 is closed and the connection A of the motor is thus connected to one connection of the voltage source + V _n , the low internal resistance of the voltage source suppresses the occurrence of a signal of measurement frequency at connection A or at the input of the comparison circuit 9. The Comparison circuit 9 is designed in such a way that in this case it generates a reset signal RES which sets the last or all stages of the frequency divider 4 to zero and keeps these stages in this state,

Once the clock's time display has been corrected, the switch 11 is open, the reset signal RES disappears, and the frequency divider 4 begins to operate normally again. After a

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a certain time, which is determined by the number of counter steps set to zero, the motor will receive the first drive pulse. The polarity of this impulse is always the same which means that the motor is brought into a certain position while the time display is being corrected, so that it works correctly from the first drive pulse that occurs.

In the more detailed circuit diagram according to Figure 2 is the frequency divider with the stages a - w shown, each of which as a flip-flop with two inputs Cl and Cl, two outputs Q and Q. and a reset input RAZ is formed. Furthermore, FIG. 2 shows correction circuits 18 and 19, which have NAND gates 16 and 17 act on certain stages of the frequency divider. The 'frequency fo of the crystal oscillator, not shown in FIG is 32 768 Hz. Continued division by the factor results in a frequency of 1 Hz at the output of stage ο Divider stages £ - s_ on which the correction circuit 18 acts, divide this frequency by ten, the steps t - v, on which the correction circuit 19 acts, effect a further division by a factor of six such that the output signal of stage ν has a period of one minute. The way the corkscrew works door circuits 18 and 19 are known. You are talking about potentials "1" ari to certain outputs of the frequency divider and apply a certain reset pulse to the divider stages connected to them at. In the present example, pulses from output Q of divider stage d pass through NAND gates 16 and 17 to the return

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Control inputs of levels £ - v. The logic control circuit 5 is also known. The NAND gates 20 and 21 are opened alternately for one minute through the outputs Q and Q of stage ν. The output Q of the stage ν causes the transmission of a pulse from the output U of the stage ^ (f ₂ ) to the two gates 2O and 21 once per minute operated in the manner described below.

The control stage 6 has two pairs of complementary transistors T _n , -T ₀ and T_, T. The emitters of the transistors T ₁ and

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T "are connected to the terminal - V _n ^, of the voltage source, while the emitters of the transistors T" and T. are connected to the terminal + V _{ß of} the voltage source. The collectors of the transistors T 1 and T _ are connected to one another and form one connection A of the motor 7, while the collectors of the transistors T and T, which are also connected to one another, form the connection B of the motor 7. The output C of the logic circuit 5 controls the base of the transistor T_ via a resistor R ", and the base of the transistor T_ via an inverter and a resistor R ₃ . The output D of the logic circuit 5 controls the base of the transistor T. via a resistor R ₄ and the base of the transistor T ₁ via an inverter I ^ and a resistor R 1. In the present case, it is a motor that does not allow the seconds to be displayed, in that the motor receives only one pulse per minute. The duration of this pulse is very short, for example between 15 and 20 milli-

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Seconds. In the illustrated embodiment, the pulse duration is 15.625 milliseconds. In the exemplary embodiment according to FIG. 2, the outputs C and D are normally in the logic state "1", which corresponds to _{the voltage + ν_ π.} In

DD

In this case, the transistors T ₁ , T 3, T ₃ and T _{4 are} blocked, and no current flows in the winding of the motor 7. A first drive pulse is triggered, for example, when output C emits a first negative pulse whose logic voltage "O" corresponds to voltage −V. During this pulse the transistor T_ becomes conductive and connects the connection B of the motor with the connection - V ₀₀ . The transistor T _{0 also} becomes conductive and connects the connection A of the motor with the connection + V _or> .

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This closes a circuit in which a drive pulse flows through the motor. A minute later, a corresponding negative pulse occurs at the output D of the logic circuit, which makes the transistors T _{1 and T 4} conductive. The connection B of the motor is connected with the voltage + V ^ _n and the connection A of the motor with the voltage - V ₀₁ ,

DD DD

bound, and a drive pulse flows in the opposite direction through the motor. The direction or polarity of the drive pulses thus always alternates.

As Figure 2 also shows, the frequency divider 4 different Pulse signals f,, f, and, f ^ extracted, the frequencies of which are different are. These pulse signals control the inputs of a NAND gate 12. The output of this gate 12 supplies the so-called Read signal via an inverter 13 to one input of a

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second NAND gate 14. The complementary pulse signal from f,,
namely f., reaches connection B via a resistor
of the motor 7. As already explained above, the frequency
this signal either at port A or at port B.
of the motor 7 can be measured. This controls from port A.
Pulse signal f .. the second input of the NAND gate 14. The switch 11 is between the connection + V _._ and the connection A of the

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Motor 7 arranged.

The mode of operation of the last-mentioned parts of the circuit according to FIG. 2 will now be explained with reference to FIG. With normal
Operation, which the curves to the left of the dashed line F in
Figure 3 correspond, no read signal passes through the gate 14,
because this is due to the interaction of the signals f .., f_ and f ~, according to Boole algebra as

f * f · f
^r l ^r 2 ^Γ 3

expressed and appearing at the output of the inverter 13 due to the complementarity of the signal f., which the second input of the gate 14 controls, this gate can never happen. Will

on the other hand, if the switch 11 is closed, the state shown to the right of the dashed line F in FIG
This means that pulses of the read signal f · f · f pass through the gate 14 and are passed on as reset pulses RES. These reset pulses reset the stages 1_, m, ri, c> and w via the inverter 15 on the one hand, and the stages £ - ν on the other hand via the gates 16 and 17. These reset pulses RES make under

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among other things, the logic circuit 5 is ineffective, the outputs C and D of which remain at the potential "1" in such a way / that no drive pulses reach the motor 7. The diagrams of Figure 3 illustrate the operation of the provision. As a result of the inverter 13, the gate 14 cannot have a reset signal during normal operation Submit RES. However, if the switch 11 is closed, the terminal A assumes the logic voltage "1", and the first through the gate 12 transmitted pulse is transmitted to the stages of the frequency divider 4 to be reset. The dashed Line F denotes the moment in which the switch 11 is closed. One minute after the switch 11 opens again the stepping motor receives an incremental pulse again.

It may be that the switch 11 is closed while the connection Ä via the transistor T, to the negative terminal of the Voltage source - V "" is connected. To in this case a

D £ 5

To avoid a short circuit in the battery, a protective device shown in FIG. 2 is provided. It has an NPN transistor T ₅ , the base of which is connected to the output of the inverter I _{via a resistor R 5.} The emitter of this transistor is connected to the negative terminal - V _n -. connected to the voltage source, and its collector is connected to the emitter of an NPN transistor Τ ,, whose base is connected to terminal A of the motor

7 is connected, and whose collector is connected to the collector of a • PNP transistor T _7, which is connected as a diode, and whose emitter is connected to the positive terminal + V _{nD of} the voltage

DD

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source is connected. The base of the transistor T ₇ is connected to the base of another PNP transistor T ₀ , the emitter of which is connected to the

positive voltage + V, and the collector of which is connected _{to the base of an NPN transistor T g.} The collector of the last-mentioned transistor is connected directly to the base of the transistor T- and its emitter is connected to the negative terminal -'V of the voltage source.

If the transistor T .. is saturated, then this also applies to the transistor T,., And the connection A is at the potential - V_ _ß . If the switch 11 is now closed, the voltage at connection A immediately jumps to the value + V _RR , and the voltage source supplies a relatively large current. Under these conditions, the transistor T _c is now conductive, and its collector current is transmitted via the transistors T_ and Tg to the transistor T_, which thus becomes conductive and blocks the transistor T ... Thanks to this circuit arrangement, a short-circuit current can only occur for a very short time, which, incidentally, is limited by the transistor T 1. The duration of the short-circuit current corresponds to the switching time of the transistors T ₆ -, T ₇ , T ₈ and T ₉ .

Figure 4 shows an Ausführungsbexspiel with a rectified by Impulse-driven stepper motor. The circuit also differs from that of Figure 2 in that that the control circuit for the motor is equipped with MOSFET transistors. The frequency divider 4 has in this

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Exemplary embodiment twenty stages a. and with a correction circuit 22, the frequency of the 1 Hz pulses appearing at the output of stage ο being additionally divided by 60. The correction pulse arrives every minute from the output Q of stage j_ through the NAND gate 23. An inverse pulse can be used to control the motor 7. This control pulse arrives at the control electrode of an N-channel field effect transistor T-iQf whose source is connected to ground G and whose drain is connected to terminal E of motor 7. The other, unmarked connection of the motor 7 is connected to the positive terminal + V _n -, the voltage source. With every tax

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impulse, the transistor T, becomes conductive and leaves a stepping impulse flow through the motor 7. The switch 11 is connected in parallel to the motor 7.

The logic circuit 24, which is not described in detail, supplies the pulses f-, the frequency of which corresponds to that of the pulses f. At the output Q of the stage η (2 Hz), and the length of which corresponds to that of the pulses at the output Q of the stage a. is equivalent to. The positive pulses f _T reach the control electrode of an N-channel

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Transistor T- .., whose source is connected to the ground G and its sink via a "resistor R ₇ to the connection E of the motor. The pulses f _T thus reach the connection E of the motor.

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tors. Assuming that the value of the resistor R _{7 is} approximately equal to the resistance of the coil of the motor 7, the voltage of the pulses f _L at the connection E of the motor is only 1/2 V _73n . These impulses are therefore too weak and too short,

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to actuate the motor, but they are strong enough to should be counted The pulses f_ also reach an inverter having an N-channel field effect transistor T, "and a P-channel field effect transistor T ₁₃ and control the control electrode of a P -Kanal field effect transistor ^ ₁₄ , the source of which is connected to one terminal + V _D _, the voltage source and its sink to the control electrodes of two further P-channel field effect transistors T ₁₅ and T-. The control electrodes of the transistors T ₁₅ and T ,, and the sink of the transistor T _1ς are connected to the terminal E of the motor 7, while the sink of the transistor T ₁ , via a resistor R _p with the

16 ο

Ground G of the circuit is connected.

When the switch 11 is open, the pulses f _T are transmitted to the sink of the transistor T. _fi and will thus appear as positive pulses at the resistor R _g . When the switch 11 is closed, however, the transistors T, ^ and T, _{fi are} blocked, and the voltage across the resistor R _ft is zero. The drain of the transistor T, _g is connected to the input S25 of an RS flip-flop 25, the output Q25 of which controls one of the inputs of a NAND gate 30. Two pulse signals f. And f ^, which are taken from the outputs Q of the stages η and m, respectively, control the two inputs of a NAND gate 26, the output of which is connected to the input R25 of the RS flip-flop 25. The pulses ~ i also directly control one of the inputs of a NAND gate 27, while the pulses 'f' control the second input of the gate 27 via an inverter 28, the output of which is connected to the second input of the gate 30. The output of the gate 30 is with the

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Reset inputs RES of the stages k - ο of the frequency divider and via an inverter 29 with one of the inputs of the NAND gate 23 connected, which is also controlled by the correction circuit 22.

FIG. 5 illustrates resetting to zero by resetting pulses RES, which appear at the output of gate 30 when switch 11 is closed. The time at which the switch is closed is again indicated by a dashed line F in FIG. According to Boole's logical algebra the signal at the output of gate 27 can be represented as follows:

^f 4 ^{+ 1} S '

and the signal at the output of gate 26 can be represented by:

^f 4 ' ^f V

This means that the signal f _T when the switch is closed

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ter 11 disappears, which causes the output Q25 of the flip-flop 25 remains at zero such that the signal f + f through the gate 30 can be transferred.

The choice of the pulse signals f. + F ₅ is not of decisive importance. Other combinations of pulse signals can also be selected in order to generate the so-called read signal and, accordingly, the reset signal.

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Claims (5)

2 b 3 4 O 3 5 PATENT CLAIMS: lly electronic circuit for a quartz watch with a Stepper motor and an oscillator and subsequent frequency divider, which is a logical stage for control of the motor, characterized in that connections (A, B) of the circuit, which are used to control the motor (7), also for checking a frequency derived from the frequency divider (4) and / or for stopping the clock and for Resetting to zero at least one stage of the frequency divider (4) can be used. 2. A circuit according to claim 1, characterized in that for checking the frequency of the oscillator (1, 2, 3) a Pulse signal coming from one stage of the frequency divider (4) from one of the connections (A or B) of the motor (7) is derived. 3. A circuit according to claim 1 or 2, characterized in that to stop the clock between the one connection of the motor (7) and a terminal of the voltage source lying switch (11) is closed. 4. Circuit according to one of claims 1 - 3, characterized in that that a reset signal for resetting to zero at least one stage of the frequency divider (4) by 609812/0856 equal to the voltage state at that terminal of the motor (7) to which the switch (11) is connected and the combination of several, of different stages of the Frequency divider derived pulse signals (f .., f, f_ or f., fj.) is formed. 5. A circuit according to claim 4, characterized in that the mentioned combination _{corresponds to the conjunction (f 1} * f _? 'F_) of the pulse signals. 609812/0856