DE2521019A1 - ANALOG / DIGITAL CONVERTER - Google Patents

Description

Applicant's file number:

PI 973 093

Analog / digital converter

The invention relates to an analog / digital converter according to the preamble of claim 1.

The type of analog / digital converter under consideration is especially suitable for implementation in integrated circuit technology.

Various types of analog-to-digital converters are already known. These include versions with a charging curve, double charging curve, voltage / prequez converter, comparative converter, which contain a digital / analog converter and the output signal compare with the input signal, and many others. All known A / D converters have their specific problems intrinsic such as inaccuracies, high effort, etc. The inaccuracy is z. B. the special property of A / D converters with integrators because of the difficulty in achieving linear voltage curves and in adhering to specified voltage transition points. Voltage / frequency converters are also fundamentally non-linear. The A / D converter with D / A feedback are the most accurate, but also the most complex.

All A / D converters have the problem of errors due to the running away or changing of the components and the control signals due to temperature, environmental influences and aging. Various solutions to compensate for such errors are already in place has been proposed. However, these techniques are mostly

509988/0790

2521013

quite complicated.

A precise A / D converter, which can be contained in a single monolithic component, was described by Chellen et al. In a lecture at the IEEE International Solid-state Circuits Conference in Philadelphia in February 1973. A corresponding article appeared on page 22 of the conference reports. The A / D converter described uses a voltage-controlled oscillator that operates with an input voltage and a reference voltage. The output signal and a subharmonic of the associated clock generator are fed to a flip-flop that responds to planks, the output signal of which in turn _{controls the application of the diffraction voltage V R} " _p to the oscillator input. Feedback is used to change the on-duty cycle of the flip-flop output signal so that the on-cycle is a linear function of the analog input signal, the on / off time ratio of the flip-flop depending on the ratio between the input voltage and the diffraction voltage Error self-compensation can be achieved. However, the accuracy of the device depends on the ratio of the input resistances of the oscillator and the linearity of the oscillator. Although the authors claim that the self-compensating provisions sufficiently compensate for the non-linearity of the voltage controlled oscillator, it is known that the linearity of voltage controlled oscillators is not satisfactory for accuracy.

Willard et al. in U.S. Patent 3,530,458 describe an A / D converter with feedback loops to compensate for the deviations regarding gain and zero properties of the converter arrangement. However, a digital computer is necessary for the compensation; Relays and resistors that can be changed by a motor drive are required for setting the input balancing resistor (for the purpose of characteristic curve compensation) and for automatic setting of tapping resistances (to compensate for the gain character

FI 973 093

teristics). This results in a very high outlay and the impossibility of using such an A / D converter in a simple one to accommodate integrated component. The converter also uses a voltage / frequency converter that is built in is nonlinear. In the patent it is mentioned that the corresponding converter is only for low-frequency analog voltages below 5 Hz is usable.

The object of the invention is the prior art to provide a very accurate analog / digital converter, the can be accommodated with all details on an integrated component with relatively little effort; the precaution an automatic self-adjustment on the same integrated component should be possible without difficulty.

The solution to this problem is characterized in claim 1. Advantageous refinements are described in the subclaims.

The subject matter of the present invention does not include precision resistors, no possibly interfering non-linear integrators, no voltage-controlled oscillators and no digital / analog feedback necessary. The converter is self-adjusting, whereby errors are prevented that arise usually result from deviations in the components and / or the control voltages.

The conversion takes place with the impulse discharge of a storage capacitor performed, to which the analog input signal is fed; the discharge pulses are counted until the charge of the capacitor is zero. The pulsed discharge takes place via a constant current path, whereby it is ensured that each Impulse allows a constant amount of charge to flow away. The self-adjustment is carried out with the application of a known reference voltage

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feasible to the storage capacitor, the deviation of the pulses according to number and phase is determined, leading to the complete Discharge of the reference voltage are required, and by adjusting the constant current path accordingly. The number of pulses which is normally required to discharge the capacitor during adjustment is known. If the appropriate Pulse number is given, a first input signal is fed to an input of a phase detector. Once the capacitor charge reaches the value zero, a second input signal is given to the phase detector. The time interval between these both input signals is a measure of the error. Of the The phase detector outputs an error voltage to control the constant current path, the current being increased if the capacitor discharges too slowly; however, the constant current is lowered if the capacitor discharges too quickly occurs.

The deviation of the amplitude and phase of the associated clock generator has no influence on the accuracy, because the constant Current to discharge a given charge, clocking pulses have no influence with regard to their own amplitude, since only simply counting the number of clock pulses required.

Embodiments of the invention are shown in the drawings and are described in more detail below.

Fig. 1 shows the block diagram of an embodiment of the invention.

FIG. 2 shows a modification of the circuit according to FIG. 1.

Fig. 3 shows waveforms for explaining the control signals, respectively Figs. 2 and 4.

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Pig. FIG. 4 shows details of the circuitry according to FIG.

FIG. 5 is a modification of FIG. 4.

Fig. 6 shows circuitry for automatic compensation such as they can be used in connection with FIG.

In accordance with the block diagram in FIG. 1, work is carried out in two operating states: setting and converting. During the adjustment, a reference voltage V _{REP is} measured and the current path is adjusted. During the conversion, the input voltage V _{IN is} sampled and converted. The operating modes can be provided in an alternating sequence; however, it is not absolutely necessary. It can e.g. B. several conversion steps can be carried out after each adjustment step.

The switching and gate signals for the device can be controlled in a conventional manner, which is not shown in detail a clock such as B. the pulse generator 36 are generated. Optionally, the same counter that records the respective digital value of the analog signal can also be used as a timing aid for generating the control signals. Such Execution is in connection with the description of FIGS. 2 and 3 explained in more detail.

Back to Fig. 1. The storing element is the capacitor via a switch 10 are analog voltage values in the capacitor 18 entered. The charge of the capacitor 18 is reduced in pulses via a controllable current path 20, which with each pulse supplied discharges the capacitor by a specified amount. The current path 20 is on the part of the pulse generator 36 via a normally open gate member 38. The transmitted pulses from the generator 36 are on the part a counter 42 is counted. A threshold detector 22 detects if the charge of the capacitor has reached a given threshold

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value, preferably zero volts, is lowered, and gives an output signal which is used for setting during setting and for reading out the count during conversion will.

A phase detector 28 measures the time difference between the signals E1 and E2 input into it. E1 runs in when the threshold value detector 22 detects zero volts on the capacitor 18. E2 is entered when the counter 42 reaches a count N equal to the known number corresponding to the reference voltage V _R ™. The output signal of the phase detector 28 is a voltage, the magnitude and polarity of which depends on the time difference between the two input signals. This output signal is applied to sample and hold circuits 26 which are only sensitive to the applied voltage during adjustment. During the conversion, the voltage recorded in the circles 26 is no longer changed by the phase detector 28. The voltage recorded in the circles 26 is fed to the controllable current path 20 via a low-pass filter and amplifier 24. The voltage supplied to the current path 20 controls the size of the current pulses passing through, which the current path 20 draws from the capacitor 18 under the control of the generator 36.

First, the punctures of the A / D converter will now be described during the setting. For explanation it should be assumed that V _REF = +10 volts and that the converter is provided for processing analog signals up to a maximum of 10 volts in steps of 0.01 volts; that is, a 10 volt input is converted to a digital count of 1000. For Im = 10000, the current path 20 is set in such a way that it draws 0.01 volts from the capacitor 18 for each pulse from the generator 36.

At the beginning a switch 30 is brought into the setting position 34; a control potential for setting appears at the control input of the

PI 973 093

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Circles 26 for scanning and holding. The switch 10 is in position 12 and a clear signal is supplied to the normally permeable gate member 38 and the counter 42. The switch 10 feeds the reference voltage V _RE ″ to the capacitor 18 via its position 12. After a very short sampling period long enough to charge the capacitor 18 to the reference voltage, the switch 10 is brought back into its exhibition 14. The clear signal brings the counter 42 to its initial position zero and blocks pulses from the generator 36 so that they cannot pass through the gate member 38. The circuits 26 for sampling and holding are now susceptible to voltage changes at the phase detector output. The threshold value detector 22 has a sufficiently high input impedance that it itself practically does not contribute to the discharging of the capacitor 18.

Immediately after the switch 10 has returned to its display, the clear signal is also terminated. The timing is not critical as long as the clear signal is not terminated before the capacitor 18 is fully charged. The impulses from the generator 36 are now fed to the current path 20 and the counter 42. Each pulse lets the capacitor 18 through the current path 20 Discharge 0.01 volts in the given example. When the capacitor is fully discharged, the threshold value detector emits a signal El away. If the arrangement is working properly, the counter 42 reaches a count N at the same time as the threshold detector 22 emits the signal El.

Assume that the two signals E1 and E2 come at the same time at the two inputs of the phase detector 28. Then there is no changed output signal at the phase detector output, and the setting of the sample and hold circles 26 is not changed. However, if El comes in before E2, this means that the capacitor 18 was discharged too quickly. The output of the phase detector 28 is a lower voltage in

FI 973 093

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the circles 26 for sampling and holding, whereby the magnitude of the current value of the current path 20 is also decreased. So is the error compensates for the subsequent conversion process (s).

If E2 arrives before E1, this means that the capacitor 18 discharged too slowly. The phase detector output increases the The voltage value stored in the circles 26 and thus brings about an increase in the magnitude of the current value through the current path 20. This in turn compensates for the error for the subsequent conversion step or steps.

At the beginning of each conversion cycle, the switch 30 is brought into the conversion position 32 and the setting control signal is removed from the control input of the circuits 26. The switch 10 is brought into its position 16 and the clear signal is fed to the gate element 38 and the counter 42. The gate 38 is blocked, the counter 42 is cleared and the circuits 26 are made unresponsive to the phase detector output signal. The voltage V _n j N is fed to the capacitor 18. During the actual conversion, the phase detector 28 can be viewed as ineffective; its output signal no longer has any influence on the other components.

After a short period, but long enough to _{charge capacitor 18 to V FIN} , switch 10 returns to its exhibition 14 and the clear signal is removed from gate 38 and counter 42. Pulses from the generator 36 now pass through the gate member 38 and are counted by the counter 42. Each individual pulse also ensures, by means of the current path 20, that the capacitor 18 is discharged by 0.01 volts. Although temperature, supply voltage and tolerance errors aim to change the specified discharge value away from 0.01 volts, the during adjustment processes

FI 973 093

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guided correction every time the return to the desired 0.01 volt value. As soon as the capacitor 18 is fully discharged, the threshold value detector 22 emits a signal E1, which can now read the count reached by the counter 42 via the switch 30. The count reached is the digital equivalent of Vg _IN

It should be noted that the reference voltage need not be equal to the maximum processable voltage. For example, V _REfl can be 1.0 volts, even if the converter is to process voltages up to +10 volts. N is then chosen to be 100 and not 1000. The total counting range, however, remains the same as described above.

As already mentioned, the switching and control signals, such as deleting and setting, can be provided by special Circuits are generated or with the aid of the counter 42. Setting and converting can be carried out alternately will. Fig. 2 shows a modified block diagram for the case that the switching and control signals by the counter 42 and an associated logic is generated and that setting and conversion take place alternately. The details of the FIGS. 2, which correspond to those of FIG. 1, will not be described again.

It is assumed that the counter 42 has a capacity N + η and that a decoder of conventional type is connected to it, which outputs signals when the counter is at zero, N or Ν + δ; δ is smaller than η and preferably one small positive integer like one or two. In this case the counter does not need to be cleared by an external signal although such an external signal could easily be used. A gate member 44 according to FIG. 2 is replaced the gate member 38 of Figure 1. The switch 30 is now in block form shown as an electronic switch and similarly the switch 10 of FIG. 1 as electronic switches 10a and 10b.

FI 973 093

2S21019

The control signals delete, V _{REp switch} on, Vgjjj switch on, convert and set are shown in the time diagram of FIG. They are generated according to the switching states of the counter 42 with simple logic circuits, the flip-flops 46 and 48 and the AND gates 50 and 52.

In the example shown, each operation begins with the count Ν + δ in the counter 42. The pulses from the generator 36 are constantly enumerated in the counter 42. As soon as the counter 42 has reached the count N + n, the next input pulse switches the Counter to zero.

For explanation it should be assumed that the A / D converter is switched to converting and that the counter is at N. Counting steps later, the flip-flop 46 is switched on and generates an output signal delete; the flip-flop 48 is snapped in and emits a set output signal. The signal ogp switch-on now appears at the output of the AND element 50. The switch 10a is switched through with the signal V _{REp switch-} on and connects the reference voltage to the capacitor 18. The gate element 44 is opened or blocked by the signal delete, to possibly receive pulses from Keep current path 20 away. The sample and hold circuits 26 are controlled by the timing signal in order to be conditionally susceptible to changes in the phase detector output signal. The switch 30

rd blocked or switched through by the convert signal. As the pulses from the generator 36 are continuously being enumerated, the counter reaches the count N + n and then goes back to the count zero. At this point the clear and V _R gp turn on signals are terminated. The pulses that now follow are fed to the current path 20 via the gate element 44, and an adjustment takes place as described above in connection with FIG.

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When the counter reaches the count Ν + δ again, a conversion process begins. The following control signals now appear: convert, delete and switch V „ _IN on. When the counter 42 starts again, the signals delete and V ^ -rxT switch-on are aborted again, and the converter begins to discharge the capacitor 18 in discrete steps. When the capacitor 18 is fully discharged, the threshold value detector 22 generates the signal E1 which, on the other hand, also passes through the switch 30 in order to cause the count of the counter 42 to be read out. A non-destructive reading is carried out. If desired, the same signal that controls the reading of the counter 42 can also be used to clear the counter 42 to the count N + δ.

Further details of this second exemplary embodiment are shown in FIG. The Pig. 4 according to the scheme Pig. 2. The components shown in block form correspond to the state of the art; In this respect, details of this are no longer explained. It is well known that such circuits can be manufactured using integrated circuit technology. The phase discriminator may be as described in U.S. Patent 3,870 and the corresponding German patent application P 24 48 533.4 is described. The control signals and the logic for their generation should turn the Pign. 2 and 3 correspond.

The switches for connecting V _REp and V _EIN to the storage capacitor 64 are preferably designed as N-channel field effect transistors of the enhancement type in a metal-oxide semi-conductor design. The control signals V _{1517131 switch} on and V _1n , .. switch on are fed to the gate connections of the field effect transistors 60 and 62, referred to below for short as FET. The threshold detector is shown as a conventional zero-level crossing detector with bipolar transistors 70 and 72 of the PNP type, resistors 68, 74 and 76 and voltage sources E _ß and -Vz. A positive output signal appears on

PI 973 093

f, Π ή Aft R / η 7 Π Π

Collector of transistor 72 via line 78 if the capacitor 64 reaches the level zero. However, any other suitable zero level crossing detector may be used in place of the chosen can also be used.

The controlled current path is designed in the form of a conventional constant current source with a bipolar NPN transistor 88, which is connected to the voltage source -V via a resistor 90. The bipolar NPN transistor 96 connected in emitter follower arrangement with the RC element 92, Sk serves as an amplifier and smoothing filter for the output of the circuits 98 for sampling and holding.

The circuits which, in response to pulses from the pulse generator 104, discharge the capacitor 64 via the current path in predetermined steps let include bipolar NPN transistors 80, 82 and 84, all emitters of which are connected to the collector of transistor 88.

A setting step will now be described first. The counter 106 counts up to the count Ν + δ and causes the output of the signals delete, V _RE p switch on and set. V _{REF switch} on

turns on PET 62 and thus leaves V _n ^ ₁ -, to capacitor 64

only

reach. There is no significant discharge of the capacitor into the zero crossing detector. The delete signal becomes the Base of transistor 82 is supplied and thus opens a constant current curve through transistor 88 of the constant current path. The transistor 80 with a negative bias voltage of -V "is non-conductive. The one by the pulse generator 104 pulses applied to the base of transistor 84 have no effect on transistor 80 at this point; she only open up an additional current path through transistor 84 for part of that flowing through the constant current path constant current. The pulses from generator 104 are counted in counter 106.

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When the counter 106 reaches the count zero, the signals V ₁₃₁ -, - turn on and clear are terminated; their signal level goes thereby

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down and blocks transistors 62 and 82. Preferably, transistor 62 is switched off before the end of the delete signal; this could be solved simply by causing the end of the signal V " _E p switch-on at a count shortly before the count zero, e.g. B. at N + n or at N + n-1 or similar.

The low level at the base of transistor 82 is assumed to _{be below -V 2.} When the generator 104 is pulsed, the base of 84 alternates between high and low levels. The high level is assumed to be above -Vp and the low level to be below -Vp. Thus, during each pulse at the base of 84 when the level is high, all of the constant current will pass through transistor 84 via transistor 88. During the times when low pulse levels are present at the base of transistor 84, all of the constant current is drawn through transistor 80, which thereby discharges capacitor 64 by a given amount. It can be assumed here that the predetermined discharge of the capacitor 64 remains unaffected by small changes in the amplitude of the pulse amplitude level of the generator 104, since the amplitude of the pulses does not control the magnitude of the current flowing through the transistor 80. Phase variations of the generator output pulses also do not affect the measurement, and the counter counts one pulse for each discrete discharge step of the capacitor 64. A variation of the switch-on times of the pulse generator output would, however, have to influence the measurement, because this would affect the duration of the discharge during each discharge step. However, this possibility of error is compensated for by the setting operations previously carried out, as has already been described.

973 093

When the counter 106 reaches the count N, it becomes a signal E2 is supplied to the phase detector 100. Once the charge on capacitor 64 reaches zero volts, transistor 72 of the The zero crossing detector is conductive, thus raising the voltage on the line 78 and emitting a signal E1 to the input of the phase detector 100.

If E1 arrives before E2, which indicates that the capacitor 64 has been discharged too quickly, the phase detector generates a negative output voltage with an amplitude which is proportional to the time difference between the arrival of E1 and E2. While the set signal is pending, the detector output voltage is superimposed on that stored in the hold circuits 98 and lowers the memory voltage. The base of the transistor 96 is lowered and with it the voltage which is fed to the base of the transistor 88; the constant current value via the constant current path is thus regulated smaller. -If El comes in after E2, which indicates that the capacitor was discharged too slowly, the phase detector emits a positive output voltage, the size of which is in turn proportional to the time difference between the signals El and E2. The value of the current drawn via the constant current path is thus set higher.

As soon as the counter 106 reaches the count Ν + δ, the logic 108 switches on the control signals delete, V _ON switch on and convert. Since the signal setting is now switched down to a low level, the voltage stored in the circuits 98 remains unaffected by the output signal of the phase detector 100. The transistor 60 is switched on and allows the capacitor 64 to be charged to the voltage V ^ y ^ to be measured. The constant current path draws its entire current alternately either via transistor 82 alone or via transistors 82 and 84 in parallel. When the counter reaches zero, transistors 60 and 82 turn on

973 093

B Π 3 6 8 β / 0 7 9 Π

turned off and the capacitor 64 discharged gradually. As soon the charge of the capacitor 64 reaches zero, the transistor 72 of the zero crossing detector emits an output signal El, which passes through the AND gate 102, there on the other Input the convert signal is present; the count of the counter 106 is now read out.

By connecting an additional capacitor in parallel to the capacitor 64, the discharge time can be changed with the same number of discharge steps and thus also the conversion ratio. If z. B. two parallel capacitors of 1 picofarad and 9 picofarad are provided, a change ratio of the scale around the factor 10 can be achieved. The initial case under consideration may apply to the two capacitors connected in parallel. So the total capacity is 10 picofarads. One to the A 10 volt signal applied to the capacitor results in a total charge of 100 picojoules; Charge = capacity χ voltage. Like in the Description has been carried out, this charge is to be reduced to zero with 1000 current pulses through the constant current path. An output count of 1000 therefore applies to 10.0 volts.

The measurement range is changed simply by disconnecting 9 picofarads from the total capacitance. Now only results a 100 volt input signal charges the capacitor to 100 picojoules, which again require 1000 discharge pulses. the However, the meter output reading is now considered 100.0 volts. It can be seen that further changes in the measuring range are also possible. The accuracy of the overall arrangement depends in each one Fall in the accuracy of the capacity measurements.

In addition, a PET could be provided in parallel with the capacitor 64 are used to completely discharge the capacitor 64 between the individual operations. This FET would normally have to be locked and only switched on in short intervals between setting and conversion operations will.

PI 973 093

On the basis of the preceding description of FIG. 4, it was explained how the inputs for the voltages V_ _TM and V with the help of the "

* ^1Η REF both FETs 60 and 62 are switched through to capacitor 64.

For certain applications, however, it could be advantageous to arrange an additional bipolar transistor between the two FETs βθ and 62 and the capacitor 64. This is useful when V _FTM is coming from a high impedance source. This modification is shown in FIG. This differs from the circuits considered so far in that the additional MPN input transistor 110 is inserted. The other circuits correspond to those previously described.

The modification according to FIG. 5 has a disadvantage, over the base /

Center diode of transistor 110 is given a voltage drop V _βE . The voltages fed to the capacitor 64 are thus Vg _E and ^v gjja "" ^V BE · This also gives the output result

falsified by V -. ^.

This V " _BE error can be controlled in different ways, one possibility is the measurement of V _n ,, and the corresponding one

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changed count. Instead of the start of counting when the count is zero, the counting in the case of a compensating count could be carried out accordingly V_ "begin. This would be an automatic addition

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/ on Vg _E to V _E T _N -V _BE result. _{On the other hand, a count corresponding to} V ßE could also be added to the count resulting from the measurement. Difficulties which could arise due to an undetermined base potential of the transistor L10 can be solved by earthing this base via a further FET during the discharge time of the capacitor 64.

The explained A / D converter can even be used to measure V _ßE . _{To do} this, a known variable input voltage ν "ΕΙΝ would have to be used. This input voltage would have to be reduced until the counter evaluates it

FI 973 093

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results in zero. Then V _ßE just corresponds to the input voltage. The input is now switched through directly to the capacitor 64, bypassing the transistor 110. A measurement that now takes place gives exactly one digital measured value for V _ßE ·

The voltage V _RF can also be measured automatically and periodically using the circuitry shown in FIG. In this regard, however, it should be pointed out that in the case of the modification according to FIG. 6, the control signals may no longer be generated as shown in FIG. 3; the control signals should preferably be generated by a separate time signal source of a conventional type. Such timer circuits are well known in the art.

The actual modifications according to FIG. 6 relating to the converter will be explained. An additional work step is provided for this purpose, which is to be referred to as the measurement step for V _ßE . During this measuring process, V " _{IN is} not connected to the D terminal. Instead, the terminal D is supplied with _{a voltage V BE via a high gain negative feedback circuit.} V _ßE is then fed directly to the capacitor 64 and evaluated as in the conversion; except, however, that instead of reading the digital equivalent of V _ßE when the signal El is switched on, the digital value V _{ßE is recorded} in the counter and serves as the start count value for the subsequent setting or conversion process. During the deletion times of the conversion and setting processes, the counter does not continue to count as shown in FIG. After these deletion times, when the voltage on the capacitor V ^^^ - V ^^ or ν _πΡΏ -ν _ΌΓ , is converted, starts

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the counter then with the _{count value corresponding to V RF} and stops at the evaluation counts for V, -, ™ or

The negative feedback path contains high gain an operational amplifier 120, two N-channel field effect transistors of the enhancement type 114 and 116, a capacitor 121 and a charging resistor 118. The charging resistor 118 could be a

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Be a P-channel FET with its source connection and gate connection connected are. Furthermore, an N-channel FET 112 becomes an enhancement type intended.

The measurement of V _R "takes place as follows: The clear signal, not shown, does not allow any pulses to reach the constant tread path and the counter. The signal V _ _M on is switched on and switches the FET 60 through. FET 114 is on and FET 112 is off. The feedback branch now forces the terminal D to the voltage V _R ". Because of the extremely high gain of the operational amplifier 120, small negative or positive charges on the capacitor 64 are converted into large negative or positive voltage values for the gate connection of the FET 116. Resistor 118 and FET 116 operate as an inverter. In this case, a small positive charge on the capacitor 64 results in the potential of the terminal D migrating into the negative, with the result that the charge on the capacitor 64 is reduced. A small negative charge on capacitor 64 results in a positive drift of the clamping potential from D, which in turn increases the voltage across the capacitor. This feedback circuit stabilizes in a condition in which capacitor 64 has zero charge and the voltage at terminal D is then _VβE above zero. This voltage stabilization is well known for negative feedback systems and works quickly. The stabilization speed is increased by bridging the capacitor 64 with a switchable resistor while the feedback system is working. After a short time long enough to achieve stabilization, the FET 114 and the feedback branch and also the FET 60 are switched off. The capacitor 121 keeps the terminal voltage at D still at V _ßE · Now FET 112 is switched on to supply V ₁₃₁ -, to the capacitor 64. FET 112 is switched off again and the clearing signal (not shown) is ended; V ™ is converted as described above.

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Adjustment and conversion are then carried out as described at the beginning of the V “ _E measurement process.

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Abstract: An analog / digital converter was described that can be implemented in integrated circuit technology. Samples of the voltage to be converted are fed to a storage capacitor, which is discharged in pulses in predetermined steps that are determined by a voltage-controllable constant current path. The impulses are counted and the resulting count used as a measure for the input voltage. For this purpose, a known bias voltage is fed to the storage capacitor and then discharged in pulses via the voltage-controllable current path. A deviation of the discharge time from the known discharge time, ie the known number of pulses for discharging the capacitor, is used to change the control voltage for the current value in the constant current path.

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^r η q A $ B / η η q η

Claims (1)

PATENT CLAIMS Analog / digital converter for converting the voltage values of an analog signal into equivalent digital values by: a) a storage capacitor (18, 64), b) a switch (10, 10b, 60) for switching samples of an analog input voltage (Vr-Tvr) through ^{to the} storage capacitor, c) a constant current path (20, 88) for the pulse-wise discharge of the respectively stored capacitor charge in Steps of a predetermined size, with discharge steps synchronized with the clock input of the current path of discharge clock pulses are feasible d) a discharge clock pulse source in the form of a pulse generator (36, 104), e) a threshold value detector (22, 70/72) which is connected to the storage capacitor and with its help the decrease in the stored charge to a predetermined threshold value (zero level) can be recognized, and f) a counter (42, 106) for counting the discharge clock pulses which can be fed to the constant current path, wherein a digital value equivalent to the respective sample size of the applied analog input voltage in the form of until the storage capacitor is discharged to the specified threshold value, the number of pulses required on Counter is removable. _{2. A / D converter according to claim 1 with setting circuits for regulating the discharge step size} , characterized by: a) a switch (10, 10a, 62) for switching through a known reference voltage (V _n ^ 7n) to the storage capacitor ItHiX ¹ tor (18, 64), with the introduced reference charge also via the aforementioned constant current path (20, 88) can be lowered in pulses, and FI 973 093 Γ? Π t \ fi fi β / Π 7 3 f ι b) a phase detector (28, 100), the first input of which the output of the threshold value detector (22, 70/72) is connected downstream to compare one of its second Input supplied time signal (E2) known position to the start of discharge with a signal (El), which after the Time at the threshold detector output occurs that is required, that introduced into the storage capacitor Reference charge to the specified threshold value (zero level) with the discharge step size over the constant current path (20, 88) can be set depending on the time difference between the two signals (El, E2). 3. A / D converter according to claim 2, characterized by: a) a constant current path (20, 88), the current intensity of which can be fed to one of its control inputs as a function of the current Control voltage is present, and b) a gate member (38, 44, 84/82), by means of which the discharged aktirapulse from the pulse generator (36, 104) for the Constant current path (20, 88) can be selected on a time-selective basis. 4. A / D converter according to claim 3, characterized by: a) a phase detector (28, 100), at the output of which one of the determined time differences according to sign and size proportional control voltage is removable, and b) circuits (26, 98) for sampling and holding this proportional control voltage and for its continuation to the control input of the constant current path (20, 88), these circuits for sampling the control voltage have a control input from the phase detector, with the help of which a change in the held and transmitted voltage can be carried out time-selectively, controlled by a control signal (setting) is. PI 973 093 25-21013 A / D converter according to Claim 4, characterized in that the time signal (E2) of known position for the start of discharge is given to the second input of the phase detector (28, 100) after as many discharge steps as, under assumed normal conditions, to lower the capacitor charge from the reference voltage ( V _REp ) to the threshold value (zero level) are required, the number of discharge steps required for this is a digital measure for the normal reference discharge time. A / D converter according to Claim 5, characterized by: a) a first bipolar transistor (80) with its emitter and collector between the constant current path (88) and the storage capacitor (64) is arranged and its base with a given fixed potential (-Vp) is connected, b) a second bipolar transistor (84) with its emitter and collector between the constant current path (88) and an equally fixed, other suitable potential (+ V.,) Is connected, and c) a connection from the pulse generator (104) to the base of the second transistor (84), via which the second Transistor clock signals can be fed, under the influence of which the current of the constant current path (88) either during the discharge steps through the first transistor, constantly discharges charge from the storage capacitor or during the pauses in discharge flows through the second transistor as a whole, the charge removal is prevented by the storage capacitor. PI 973 093 A / D converter according to Claim 6, characterized by an additional current path for taking up the entire current of the constant current path (88) during charging periods of the storage capacitor (64), in which the capacitor either receives the reference voltage (V _RE ") for setting or analog to be converted Input voltage (V _E -r _N ) is supplied. A / D converter according to Claim 7, characterized in that that the additional current path for taking up the entire current of the constant current path (88) during charging periods a third bipolar transistor (82), the emitter / er and collector parallel to the second bipolar Transistor (84) between the constant current path (88) and the fixed one given for the second bipolar transistor Potential (+ V.) Is connected, and that the base of this third transistor is a control signal (Erase) can be supplied during the capacitor charging periods, which means that the entire constant current is absorbed can take place in the third transistor without charging the capacitor via the first bipolar transistor (80) to influence. A / D converter according to Claim 8, characterized in that a Decoder is connected, which in turn emits the time signal (E2) known position to the start of discharge when the The number of steps required for normal conditions has been carried out during the reference discharge. FI 973 093 ^ η 9 fl % G / η 7 q π 10. A / D converter according to one of the preceding claims, characterized in that that the switch (10, 10b, 60) for switching the analog input voltage (V _IN ) through to the storage capacitor (18, 64) is designed as a field effect transistor, the flow connections of which are arranged between the terminal for the analog input voltage and the storage capacitor and the gate connection of which is a control signal (V " _X , _T switching on) can be supplied during the charging of the storage capacitor when converting. 11. A / D converter according to claim 10, characterized in that the switch (10, 10a, 62) for switching through the reference voltage (V _REp ) to the storage capacitor (18, 64) is also designed as a field effect transistor, the flow connections of which between the terminal are arranged for the reference voltage and the storage capacitor and whose gate connection a control signal (V _{REp switch} on) can be fed in during the charging of the storage capacitor to the bias voltage when setting. 12. A / D converter according to claim 10 or 11, characterized in that that between the provided field effect transistor (s) (60, 62) and the storage capacitor (18, 64) bipolar input transistor (110) is provided, the emitter of which with the storage capacitor, the collector of which with a suitable fixed potential (+ V-.) and its Base is connected to the field effect transistor (s) (60, 62). FI 973 093 ^Γ > π q R η β / η 7 ^ ο 13. A / D converter according to claim 12, characterized by circuits for supplying an additional, the base emitter voltage drop of the input transistor (110) compensating additional voltage to the storage capacitor (18, 64). 14. A / D converter according to claim 13, characterized in that the additional circuits to compensate for the Base emitter voltage drop have the following characteristics: a) a negative feedback path with a high gain between the storage capacitor (64) and the FET connection (D) for the analog input voltage (V _IN ) or for the reference voltage ( ^V _REP ) » b) a switch (FET 114) for controllably switching the feedback circuits on and off and c) an additional field effect transistor (112) between the FET terminal (D) selected according to a) and the storage capacitor, whereby this field effect transistor can be switched through inversely to the predetermined switch (FET 114) is. 15. A / D converter according to one of claims 12 to 14, characterized in that that another field effect transistor for the complete discharge of the storage capacitor (64) in time periods between setting, converting and measuring the voltage drop at the input transistor (110) in parallel is arranged to the storage capacitor. FI 973 093 P η 9 $ η β / η 7 π η 2 B 210l 3 16. A / D converter according to one of claims 12 to 15, characterized in that that an additional pelde effect transistor for definition the base potential of the input transistor (110) between the base of the input transistor and a defined Potential (zero potential) is arranged, this additional field effect transistor during the discharges of the Storage capacitor (64) can be switched through. 093 ^Γ > Π 3 R $ β / ΓΙ 7 q ρ