DE2419768A1 - Frequency divider with non-binary division ratio N - also contains binary frequency divider - Google Patents

Abstract

The binary frequency divider output has a maximum division ratio m smaller than n, and is so connected to a monostable stage with a period (n-1-m)/f, that its output pulses trip the monostable stage. One output of the latter is connected to a blocking input of the binary frequency divider, so that a blocking potential is applied to it during the time interval (n-1-m)/f, and the divider does not respond to the input pulses. The division ratio is as independent as possible from temperature conditions, the parameters of the active circuit and the voltage source.

Description

Frequency divider circuit The invention relates to a frequency divider circuit.

It is known (Siemens switching examples April 1965, page 5), for Division of a frequency by the factor n to use a monostable multivibrator, whose period (n - i) is 1 / f, which is excited by every nth input pulse and the intervening n - 1 input pulses overlap.

The period T of such a monostable multivibrator may Have a maximum total tolerance AT of 1 / f, so there is no wrong division factor arises. The relative tolerance is T 1 T n-1.

The higher n, the smaller the relative tolerance. At a Division factor of e.g. n = 19, the relative tolerance is 5.5 5 '.

Since the relative tolerance of the temperature, supply voltage, the parameters of the associated active circuit and mainly the charging capacitor of the monostable elultivibrator, the limit for n will be reached very soon.

In the case of the problem of dividing a frequency, there are both binary division factors of size 2 as well as non-binary division factors, where x is an integer.

A frequency division with a binary counter, in which the counting process after is aborted by feedback every nth input pulse is described by R. Heuner, J. Litus, A. flavasy in "COSMOS MS I Counter and Register Design and Applications "RCA-Application note ICAN-6166 3/71. It is only applicable to binary Division factors easy to implement. In the case of non-binary division factors, for An extensive logic is necessary.

The aim of this invention is to provide a frequency divider circuit of simple construction with the division factor n, where the division factor is as constant as possible regardless of the temperature behavior and the parameters of the active circuit and from the supply voltage.

The frequency divider circuit that solves this problem is According to the invention, characterized in that the output of a binary frequency divider With a maximum division factor m <n so with the input of a monostable Stage with a period (n - i - m) I / f is connected that its output pulses excite the monostable stage and that an output of the monostable stage is connected to a blocking input of the binary frequency divider that at this during the time (n - m - 1) 1 / l blocking potential is applied and the binary frequency divider cannot react to input pulses.

An embodiment of the arrangement according to the invention shows Figure. BZ is the binary counter with input E, output AZ and a Reset input ER. M91 is the monostable multivibrator with input EM and the output A.

The monostable multivibrator is from the output AZ via its input EM is excited at the end of each output pulse of the binary counter and lasts over its output A the reset input ER of the binary counter during the time (n - m - 1) 1 / f on blocking potential, so that the binary counter on input pulses does not se can react.

In the case of a frequency divider according to the prior art mentioned above are e.g. with n = 19 either a monostable multivibrator with 5.5% more relative Tolerance or a five-level binary counter with feedback logic required. In the arrangement according to the invention, which satisfies the same conditions, on the other hand, only a four-stage binary counter without feedback logic and a monostable multivibrator with a relative tolerance of 50 5 'required.

Claims (1)

Claim Frequency divider circuit with the non-binary division factor n, the contains a binary frequency divider, characterized in that the output (AZ) of the binary frequency divider (BZ) with a maximum division factor m <n so with the input (EM) of a monostable stage (NM) with a period duration (n --1 - m) 1 / f is connected that its output pulses the monostable stage each excitation and that an output (A) of the monostable stage with a blocking input (ER) of the binary frequency divider is connected in such a way that during the time (n - m - i) i / f blocking potential is applied and the binary frequency divider to input pulses can not react. ee e e