DE2451362A1 - AUTOMATIC RESET SHIFT - Google Patents

Description

PATENT LAWYERS

DIPL.-ING. LEO FLEUCHAUS DR.-ING. HANS LEYH

DIPL.-ING. ERNST RATHMANN

Mönch «7i, October 28, 1974-

Melchloratr. 42

Un..rDraw: M0176P-1239

Motorola, Inc. 5725 East River Road Chicago , Illinois 60631 V.St.A.

Automatic reset circuit

The invention relates to an automatic reset circuit which is switched between two voltage levels.

The basic task of a reset circuit, which is effective in connection with the switching on of the power, consists in delivering a signal that is triggered by connecting the operating voltage and to the various Set nodes of the circuit by charging or discharging predetermined levels so that the circuit can perform its operational function. Such reset circuits are in integrated circuits often needed when logic elements and flip-flops are on a certain initial logic state should be set or if capacitors are within the circuit for the operational function must assume a certain initial function. There are reset circuits known in

Fs / wi integrated

509827/0516.

^ M0176P-1239

integrated MOS semiconductor circuits are provided and require external components for their function. These components can, for example, consist of resistors with a relatively large resistance values and large capacities exist »These high resistance or capacitance values and the associated long time constants mean that the reset circuits are not simply constructed and included in the integrated circuit can be built in with. Furthermore, such relatively long time constants are also frequent therefore required because the switch-on behavior for the power supply in systems with such integrated MOS semiconductor circuits is very different, i.e. in one In this case, the applied supply voltage can be comparatively slow accept their company, as they are relatively large Capacitors are to be reloaded, whereas in another case the operating voltage very quickly assumes its operating value or high-frequency noise signals are superimposed on the operating voltage in the event of a slow increase, »The RC time constant of Reset circuits for this purpose must be sufficiently large to meet different switch-on conditions. Reset circuits of this type have not yet been possible in easily integrate into semiconductor circuits, so that it is desirable to have an automatic reset circuit create that overcomes all of the disadvantages mentioned and when applying the operating voltage to an integrated circuit Brings all nodes to the initial voltage levels required for the circuit to function properly are.

This object is achieved according to the invention in that the Reset circuit comprises a reference voltage circuit, the voltage drop between the two voltage levels causes and supplies a voltage to control an amplifying reversing stage at an output-side node, that the amplifying reverse stage has a threshold voltage between

- 2 - the

509827/051 6

3 MO176P-1239

causes the node and the upper voltage level, which is smaller in amplitude than the voltage drop at the Reference voltage circuit, and that the amplifying reverse stage is coupled on the output side to the output of the reset circuit via an intermediate circuit.

Further features and advantages of the invention emerge from further claims.

The invention allows an automatic reset circuit, which is effective in connection with the creation of the operating circuit, create which in particular in integrated MOS circuits can be integrated on semiconductor wafers is. This reset circuit acts in such a way that when the operating voltage is switched on, the switching point of the amplifying Inverse stage is changed in length until its output assumes the correct logic voltage level, whereby this approach to the correct voltage level via further inverting stages and a signal-shaping network of an output stage is supplied, which reliably delivers the desired reset signal.

The advantages and features of the invention also emerge from the following description of an exemplary embodiment in FIG Connection with the claims and the drawing. Show it:

Fig. 1 shows an automatic reset circuit;

2 shows an output side connected to the reset circuit Start-stop circuit;

Fig. 3 is a diagram for explaining the operation of the Reset circuit according to FIG. 1.

- 3 - The

509827/0516

The automatic reset circuit 10 according to FIG. 1 comprises a bending voltage circuit 12 and a boosting inverter 14, which together perform the desired function. The automatic reset circuit 10 is between .the supply voltage Vjjjj connected to terminal 16 and earth 18. The reference voltage circuit 12 comprises a PN diode 20, P-channel MOSFETS 22, 24 and an N-channel MOSFET 26, the between the supply voltage at terminal 16 and ground lie. The anode of the diode 20 is connected to the supply voltage, while the cathode is connected to the source of the P-channel MOSFET 22 is connected »The drain of this MOSFET is connected to the source of the P-channel MOSFET 24, which is connected to its drain is at the drain of the N-channel MOSFET 26. The source of this MOSFET is connected to ground. The gate of the MOSFET 22 is connected to a terminal 54, via which the manual reset can be done. The gate and drain of the MOSFET are connected together «, the output node of the The reference voltage circuit 12 is the node 27, from which a capacitor 32 is connected to ground. This junction 27 is also connected to the input of the boosting inverter 14. The reinforcing inversion stage 14 comprises a P-KaAaI MOSFET 28 and an N-channel MOSFET 30 shown in FIG The gates of the MOSFETS 28 and 30 are connected in series between the operating voltage at terminal 16 and ground connected to each other and represent the input of the inverter, which is connected to the node 27.

The output of the inverter 14 is connected via a conductor 31 to a further circuit which comprises the MOSFETS 34, 36, 40, 42, 44, 46, 48 and 50. The purpose of this circuit is to shape the signal received via conductor 31 and to make the desired reset signal V _{R available} at terminal 52 on the output side. The conductor 31 is connected to the gate of the P-channel MOSFET 34 and the N-channel MOSFET, which are connected in series between the operating voltage and

- 4 - mass

509827 / Ü516

MO176P-1239

Mass lying. A capacitor 38 is connected between the conductor 31, ie between the gate of the MOSFETS 34 and 36 and the operating voltage. The interconnected drains of the MOSFETS 34- and 36 acting as an inverting stage are connected to the interconnected gates of the further MOS-FETs 4-0 and 4-2 acting as an inverting stage, which are also in series between the operating voltage and ground. The MOSFET 40 has a P-conductive channel path and the MOSFET 4-2 has an N-conductive channel path. The drains of the MOSFETS 40 and 42 are in turn connected together and are connected to the likewise connected gates of the MOSFETS 44, 46, 48 and 50 in the output stage of the automatic reset circuit. The MOSFETS 44 and 46 have a P-conductive channel path and the MOSFETS 48 and 50 an N-conductive channel path. The source of the MOSFET 44 is connected to the operating voltage, while its drain is connected to the source of the MOSFET 46. The drain of the MOSFET 46 is connected to the drain of the MOSFETS 48 and 50 and is also connected to the output terminal 52. The source of the MOSFETS 48 and 50 is connected to ground. The gates of the MOSFETS 44 and 48 are also connected together and are at the output of the MOSFETS 40 and 42, which act as an inverter. The gates of the MOSFETS 46 and 50 are connected to the terminal 54 for manual reset. The reset circuit is switched off via P-channel MOSFETS 56 and 60 and an N-channel MOSFET 58. The two MOSFETs 58 and 60 are connected in series between the operating voltage and ground and their gates are connected to the cut-off terminal 62. The drains the MOSFETS 58 and 60 are connected to the gates of the MOSFETS 56 and 26. The source of the MOSFET 56 is connected to the operating voltage, whereas. the drain of which is connected to node 27. The typical values with regard to the channel width and channel length of the individual MOSFETS used are based. the table below. The capacitor C, (32) can be on the order of about 75% or more of the nodal capacitance.

- 5 - table

509827/0516

M0176P-1239

Tabel Channel width Channel length χ 2.54 χ '10 " ² mm 2.54 10 mm 1.0 0.4 5.0 0.4 0.2 2.8 0.4 0.6 - 0.6 0.6 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 3.0 0.4 ■ 3.0 0.4 3.0 0.4 3.0 0.4 ■ ■ 1.0 0.4 0.4 0.4 0.4 0.4

MQSEE3?

22 24 26 28 30 34 36 40 42 44 46 48 50 56 58 60

The DC operation of the reset circuit according to Pig. I can be described by assuming that V ^ originally has the vert 0 and slowly increases in value up to a voltage of possibly 10 to 15 V. It is also advantageous to assume that the threshold voltages of the P-channel and N-channel MOSFETS are around 2V . An explanation of the mode of operation can also be found in the graphic representation according to Pig. 3, in which the voltage V _{R is shown} over the operating voltage V-η-η and describes the direct current transition function.

The basic purpose of the circuit is for a slowly increasing operating voltage Υγ, γ. therein, a reset signal

- 6 - V _R to

509827/0516

M0176P-1239

V "to be supplied, which is held essentially at ground for at least part of the time during which the operating voltage reaches a certain value. When this operating voltage value is reached, the reset signal V _R rises along curve section C in FIG. 3 to the value of operating voltage V-η-η and remains the same as this operating voltage, which continues to rise along curve section D. The dashed curve sections A and B represent possible variations of the transition function, which can be triggered by parasitic leakage currents at low voltages at different nodes of the circuit.

Assuming that the voltage at reset terminal 54 and shutdown terminal 62 has the potential value 0, * all nodes of the circuit are at ground potential. When the operating voltage V- ^ increases, the diode 20 is forward biased. As soon as the operating voltage Vyj-j, the sum of the threshold voltage of the MOSI ¹ ET 22 and the voltage drop V ^ at the diode 20 in the forward direction exceeds, the MOSi ¹ ET 22 is conductive, so that the drain of this MOSFET, which is connected to the source of the MOSFET 24- is connected, rises to a voltage value which is Vp-η - V- ^. The diode-connected MOSFET 24 is also switched on. A MOSFET acts as a diode when its gate is connected to its source, as is apparent from the book "The Theory and the Applications of Field Effect Transistors" by Cobbald, published in 1970 / by John Wiley & Sons, Inc. The voltage in node 27 follows the operating voltage V ^ at V-nT) - ^V T) ~ Vrjvpi where V _T p is the threshold voltage of the MOSFET 24-. The current over the path, which includes the diode 20 and the MOSFETS 22 and 24, is determined by the resistance of the MOSFET 26, the gate voltage of which follows the operating voltage V- ^ as soon as it exceeds the voltage V ^ p, as the MOSFET 60 is in the on state. It can be seen from the table that the MOSFET 26 is a high resistance element, that is, has a large channel length and a small channel width. the

- 7 - ": Power loss 509827/0516

»M0176P-1239

Power loss is therefore low for the reference voltage circuit 12 »

At this point the voltage between the gate and source of MOSFET 28 is approximately Vmp + Vy. Which means that MOSFET 28 is on and overdriving by V ^ V. This voltage is about 0.6 V. The overdrive of the MOSFET 28 therefore remains constant with the increase in the operating voltage V-jypj, so that the line 31 is at the value of the operating voltage Vjj-po V. When the MOSFET 36 is switched on, the output is located of the complementary MOSFETS 34 and 36, which are effective as reversing stages, to the value 0 _o This turns on the MOSFET 40, so that the output signal at the complementary MOSFETs 4-0 and 4-2, which are effective as reversing stages, has the value of the operating voltage V ^ y. assumes, with which the MOSFET 48 is switched on and in turn holds the reset signal V_ at 0V. This state corresponds to curve section E according to FIG. 3.

If the operating voltage V ^ rises further, the overdrive of the MOSFET 28 remains the same as this voltage V ^. However, the voltage at node 27 increases and drives the MOSFET 30 further into the conductive state, at the same time, due to the geometry and the resulting channel resistance of the MOSFETS 28 and 30, the output signals of the complementary MOSFETS 28 and 30 of the value of the Operating voltage Vjypj change to the value 0 when the MOSFET 30 controls the MOSFET 28 in terms of power. This triggers a corresponding switchover of the MOSFETS 34 and 36 as well as 40 and 42, which act as an inverting stage, the output signal of the latter MOSFETs falling from the value of the operating voltage V ₇ J ₁ J to the value 0 and the MOSFET 46 off and the MOSFET 44 turns on. The MOSFET 46 is in the switched-on state, since it was assumed that the connection terminal 5 ^ - is at ground potential.

■ - 8 - if

50982 7/0516

M0176P-1239

When the connection terminal 5 ^ for the reset signal is applied with a voltage V ^ ", the MOSFET 50 becomes conductive and the MOSFET 46 non-conductive. As a result, the reset signal V" is held at ground regardless of the other conditions of the reset circuit 10. Under these conditions the MOSi ¹ ET 22 is also switched off, which interrupts the current through it and thus also eliminates power loss on the current path assigned to this MOSFET.

When the voltage at the shutdown terminal 62 is raised to V ^ -p V. becomes, the MOSFET 56 becomes conductive and holds the node 27 on the operating voltage V- ^. The MOSFET 26 is thereby made non-conductive and switches off the reference voltage source 12, so that there is no more power loss at this. This switch-off function has the advantage that the The entire circuit can be switched off and power loss can be eliminated. The 'reset terminal 5' can be used for this to initiate the reset function from outside, in which case the automatic switching function of the circuit is not used.

To the reliability of the alternating current behavior of the circuit To improve it, it can be advantageous to design the capacitor 32 large enough so that when a voltage surge occurs the operating voltage terminal 16 is effective, the voltage in node 27 only increases to a value below the Switchover point or switchover value for the reversing stages acting MOSFETS 28 and 30 is located.

During the switch-on conditions, the capacitor 38 raises the voltage on the line 31 in the direction of the operating voltage V _DD and thus improves the reliability in that a relatively high initial voltage is effective on the operating line 31.

- 9 - It

50982 7/0516

MO176P-1239

It should be noted that diode 20 is fabricated such that N ⁺ diffusion is performed within P-type well diffusion, which is a conventional method for fabricating complementary MOS. The well 'only needs to be biased to + V ^ Y in order to avoid that a parasitic vertically running NPN transistor is switched on, which can occur between the N-type diffusion, the P-type well area, which acts as a base and the N-conductive substrate, for this reason it can be important to arrange the diode so that it connects to terminal 16 for the operating voltage Vy, ^ and not from any other point in the circuit to MOSFETS 22 and 24 connected is.

For certain circuit applications, especially if complementary MOS circuits are provided together with dynamic MOS circuits on the same semiconductor chip, it may be desirable that the reset circuit delivers a pulse of a certain width when the operating voltage is applied and not a certain DC voltage level, as in the circuit according to FIG Figure "1" This can be by means of a start-stop circuit can be achieved which is illustrated in FIG _o 2 "This start-stop-circuit at the output of the reset circuit 70 corresponds to the according to the circuit of Fig. 1, and includes a Start-stop reversing stage? €>, a capacitor 78 and a NAND gate 80, the output of which is connected to a further circuit 7 ^ on the same semiconductor wafer. When the input signal of the start-stop circuit 72 rises, the output of the inverter 76 remains at a high level until the capacitor 78 is charged to the threshold voltage of the NAND gate 80. A low signal level appears at the output of the NAND gate 80 until the capacitor 78 is charged to above the threshold voltage. Then the output of the NAKD gate 80 goes back to the operating voltage value V ^.

- 10 - Claims

509827/0516

Claims (12)

M0176P-1239 Claims Automatic reset circuit, which is switched between two voltage levels, thereby g e k e η η ζ e rejects that the reset circuit (10) a Reference voltage circuit (12) comprises, between the two voltage levels (operating voltage, ground) a ^ A voltage drop causes and at an output-side node (27) a voltage for controlling a amplifying inversion stage (14) supplies that the amplifying inversion stage (14) a threshold voltage between causes the node and the upper voltage level, 'which is smaller in amplitude than the voltage drop an'der reference voltage circuit, and that the amplifying reverse stage on the output side (31) to the output (52) the reset circuit via an intermediate circuit is coupled. 2. Reset circuit according to claim 1, characterized in that that the interconnection is a signal-shaping network. 3. Reset circuit according to claims 1 and 2 ^ thereby gekennzeichn et that a shutdown signal is sent to the reference voltage circuit via a shutdown network and a reset signal can be applied to the signal-shaping network. 509827/051 6 4. reset circuit according to one or more of claims 1 to 3? characterized in that the Reference voltage circuit consists of a diode (20), a first MOSFET (24) and a second MOSFET (26), which are connected in series between the two voltage levels that the reference voltage circuit a The diffraction voltage supplies, in terms of amplitude, approximately Sum of the voltage drops across the diode and the second MOSFET corresponds, and that an inverting circuit is made complementary MOS is connected between the two voltage levels, which on the input side with the interconnected Gate and drain of the second MOSFET is connected. 5. Reset circuit according to claim 4, characterized in that the signal-shaping network on the output (31) of the amplifying inverter (14) is connected to complementary MOS and to one corresponding output terminal (52) supplies the desired output signal. 6. reset circuit according to claim 5, characterized in that g e k e η η ■ indicates that the reference voltage circuit (12) comprises a third MOSFET (26) that the diode (20) with its anode at the upper voltage level and with its cathode at the source of the first MOSFET (22) is that the first MOSFET, which has a P-type channel path, has its drain connected to the source of the second MOSFET is connected, which also has a P-channel channel, and that the drain at the input of the amplifying reverse stage (14) and is connected at the same time to the drain of the third MOSFET (26), wherein the third MOSFET has an N-channel path and with its source at the lower voltage level lies. 509827/0516 MO176P-1259 7 · Reset circuit according to one or more of the claims 1 to 6, characterized in that the signal-shaping network has further reversing stages of complementary MOS includes that cascade one behind the other are switched. 8. Reset circuit according to one or more of claims 1 to 7 »characterized in that the shutdown network comprises a further MOS (4-6) with a P-conductive channel path between the drain of a MOSi ¹ ET (44) and the Drain of the other MOSi ¹ ET (48) of the further inverter is connected, and that the reset signal terminal (54) is connected to the gate of this further MOSFET (46) and the gate of the first MOSFET (22), that the switch-off network is a MOSFET (56) with P-conductive channel path, whose source is connected to the upper voltage level and whose drain is connected to the input (node 27) of the amplifying reversing stage, and that the input of this MOSFET and the third MOSFET can be controlled by the switch-off signal via the further reversing stage is. 9. reset circuit according to one or more of claims 1 to 8, characterized in that a There is a start-stop circuit connected to the output terminal (52) of the reset circuit can be connected. 10. Rückstellschaltjung according to one or more of the claims 1 to 9? characterized in that a capacitor (32) is connected between the input of the amplifying Reversing stage (14) and the lower voltage level is switched. 50982 7/0516 MOl 76P-12 '/) 11. Reset circuit according to one or more of the 'claims 1 to 10, indicated by the fact that a Another capacitor (58) is connected between the input of the second inverter (MOSFET 34, 36) and the upper voltage level. 12. Reset circuit according to one or more of claims 1 to 11, characterized in that the Reset circuit is designed as an integrated semiconductor circuit and a reset signal to other circuits supplies on the semiconductor die. 509827/0516