DE2219016C3 - Method for phase synchronization at the receiving end to the phase position of the bit clock of a received data block - Google Patents

Description

The invention relates to a method for phase synchronization on the receiving side to the phase position of the Bit clock of a received data block, which is used for phase synchronization, the beginning of the Data block characterizing code word containing bit sequence precedes which by means of digital correlation with a bit sequence that is identical to it and stored at the receiving end is compared, in particular in time-division multiplex data transmission systems.

The lead of the wireless and wired block-wise data transmission is the real one The data block is always preceded by a pulse group that consists of two parts. The first part is often one Sequence of z. B. 30 bits, within which 0 and 1 bits alternate. This bit sequence is used to determine the Bit clock for the data bits. For this purpose, a bit clock generator is provided in the receiver, its phase position with the phase position of the bit sequence is compared.

Depending on the comparison result, the phase position of the bit clock generator is adjusted so that in the Evaluation circuit the sampling of the bits of the second part of the pulse group and the data bits in the middle of the bits takes place. As with all scanning processes, the duration of the abiast taki is significantly shorter than that Duration of the bits. The clock frequencies of the bit clock generators in the transmitter and in the receiver must be sufficient exactly match. The second part of the preceding Bit sequence is mainly used for data transmission in time division duplex mode (two-way communication between two stations with time division for sending and receiving) or in time division multiplex mode (receiving of several stations with time division) It consists of one that is the same for the data blocks Code word and means that after the last bit of this code word the first bit of the actual message or the sender or

ίο recipient address follows this process as recognition of the beginning of the block or block synchronization. A so-called is used for block synchronization digital filter, also called digital correlator It consists of a shift register in which

\ ^r < the 0 or 1 outputs of the individual stages are wired with resistors according to the code word to be recognized. The other ends of the resistors are connected together and, together with a threshold value circuit, form an AND circuit.

2 «The above-mentioned facility is in IEEE transactions, Volume COM-16, Aug. 4, 1968, pp. 597-605, described in detail and shown in FIG. 1 shown

In DE-AS 12 16 921 a device for synchronizing the receive clock is ciphered

2 ^r ) third and unencrypted transmission described, in both. Cases a longer run-in phase is provided, during which the clock generator on the receive side is adjusted to the transmit clock. In the case of encrypted transmission, the key impulses and

jo is used for unencrypted transmission 01 sequences

To determine the step deviation, three feedback shift registers are provided, into each of which the last η bits enter. Got to the first

Γ. the key pulse sequence or 01 sequence generated at the receiving end, on the second the received key pulse sequence or 01 sequence and on the third the received, phase-shifted key ^{pulse sequence or 1} OI sequence. By comparing the first digits of the first and the second shift register as well as the first and the third shift register, the sign of the deviation from the receive clock compared to the transmit clock is determined.

Like the transition from running-in (synchronizing) operation

4 ^r > on the transmission of the actual useful information is successful, is not described in DE-AS 12 16 921; there is therefore no block-wise transmission of information in which the beginning of the useful information is identified by a special code word.

^r ) is 0 net.

In both known devices, the phase of the bit clock generated on the receiving side is related to the phase of the received bit clock. Such a control process is time-consuming, regardless of how

^r > ^r ) after synchronization, the transition to the transmission of the useful information takes place.

In the literature cited in the first place there is on page 605 in the left column in the last sentence of Proposal for the bit sequence for determining the bit rate

w) for the data bits and the code word that marks the beginning of the actual message. .

It is the object of the invention to provide a realization of this proposal.

This problem is solved in that the bit sequence consists only of the code word that characterizes the beginning of the data block, that the bits of the bit sequence are fed in parallel to N correlators,

their associated shift registers with - based on the bit duration T - shift clock pulse sequences that are offset by T / N in time, and that the middle of the correctors delivering the correlation value 1 is determined and the clock of the shift clock pulse sequence which advances its shift register is taken as the phase-synchronous bit clock.

Since the phase position of the bit clock is determined simultaneously with the determination of the start of the block, it is not applicable the first part of the preceding impulse group, and the time gained in this way also stands for the transmission of the actual data available.

The invention will now be explained in more detail, for example with reference to the drawings. It shows

F i g. 1 part of a known receiver for block-wise data transmission,

F i g. 2 shows a block diagram of a device for the method according to the invention,

F i g. 3 shows a timing diagram for FIG. 2.

The known device according to FIG. 1 was already mentioned in the introduction. Signal groups s, each of which consists of a number, e.g. B. 30 bits for phase synchronization, from a code word of z. B. 11 bits to recognize the block size and consists of the message block. The phase position of the bits for phase synchronization is compared in a comparator V with the phase position of the clock pulses f of a generator G 1. The frequencies of the signals reaching the comparator are the same. With the output signal of the comparator V, the phase position of the clock pulses t is readjusted until it matches the phase position of the bits for phase synchronization.

The signal groups s also reach a digital correlator DK which contains a shift register which is operated with the clock t and to whose zero or one stage resistors are connected. The other ends of the resistors are connected to a threshold value stage SW which, when responding via an AND circuit UA , applies the clock f, which has already been set correctly, to a memory 5 for receiving the message block. The shift register is connected in such a way that when the correlation value is 1, the shift clock f is switched off via an AND circuit US.

The device for the method according to the invention according to FIG. 2 no longer contains a phase-locked circuit. The in-phase clock is selected from among several. Because the pulse duration of the clock is shorter than a incoming pulse, several clocks with different phase positions can be selected. from Then the middle one is used as the one with the correct phase position for sampling the message bits.

The signal group 5 ', which reaches the device according to FIG. 2, consists only of the code word for recognizing the beginning of the block and of the message block. The preceding code word for recognizing the beginning of the block reaches eight digital correlators DK 1 to DK 8 at the same time, all of which, like the digital correlator DK in FIG. 1 are formed. The correlators DK 1 to DK 8 are each operated with one of eight clocks / I to (8, which are supplied by a generator G 2. The clocks M to (8 have the same clock frequency, but phase positions that are shifted by the same distances from one another ( Fig. 3) The pulse duration of a cycle is equal to one eighth of the

Pulse duration of an undisturbed bit,! N F i g. 3 is / that Undisturbed last bit of the code word to determine the beginning of the data block.

The incoming bits of the code word are scanned by the clocks 1 1 to / 8 and shifted on with the respective clock. Depending on the signal-to-noise ratio, the length of the bits of the signal group 5 'is more or less shortened or lengthened (phase jitter). The sampling with different phase positions of the clocks f 1 to ί 8 therefore leads to a different number of errors. If the code word is completely in the shift registers, then correspondingly more or less of the correlators DK 1 to DK 8 supply the correlation value 1. Some examples of the possible correlations are listed below.

DK
1 2 3 4th 5 6; r 8 Signal to noise
relationship 0
i 0
0 0
0 1
0 0
0 0 (
0 ( ) 0
) 0 small 0
1 0
0 1
0 1
0 1
1 1
1 0
1 middle 1
0
1 1
1
1 0
1
1 1
1
1 1
1
T 1
1
0 1
1
1 great

The underlining indicates the optimal shifting rate, which is to be determined by the evaluation logic. If several correlators have responded, the optimal shift clock is the shift clock of the central correlator. The correlation results for the pulse diagram according to FIG. 3 are shown in the last line of the table above. All correlators except DK 6 responded; the optimal shift rate is r 2.

The outputs of the correlators are shown in FIG. 3 denoted by al to a8. The effective edge of the clocks is the negative. Clock / 6 is on the edge of i, so the correlator DK 6 supplies the correlation value 0.

The output signals a1 to a8 are fed via differentiators K 1 to K 8 to an OR circuit Oi , the output signals of which are denoted by b in FIG. Counting pulses MO are used to determine the first correlation value 1, in the example a 7.

The correlation signals are only evaluated within a certain period of time in order to avoid incorrect synchronization due to noise. This is possible because, in the exemplary embodiment, the receiver roughly knows when a data block is to be expected. At this point in time, a pulse ρ , not shown in FIG. 3, is generated each time, which lasts approximately as long as that in FIG. 3 time shown. This pulse enables the output signals of the differentiating elements K 1 to K 8 to be counted via an AND circuit i / 9 and an AND circuit i / 3. A reset pulse f 11 also generated by the generator G 2 sets a 3-bit counter Zuber an AND circuit i / 2 to zero. From the beginning of the pulse ρ on, the counting pulses MO are fed to the counter via the AND circuit (73 and the OR circuit O 2).

In Γ 'g. 3 a time scale is drawn in at the bottom. At time 0 the counter is set to zero, until /. At time 7.5 eight counting pulses 1 10 reach the counter Z. The output signals f, g and h of the counter cannot

get on because downstream AND circuits ί / 5, L'6 and U7 are blocked by a flip-flop FFI via the inverter 12. At time 8 the counter starts counting again from zero. The first pulse b, which occurs at time 14, switches the flip-flop FFl and a flip-flop FF2 to the other position. FFl thus blocks the hasty AND circuit Ui its input for further pulses; he continues to block the supply of further counting pulses 1 10 to the counter Z via the AND circuit L / 3 and the resetting of the counter by f 11 via an inverter / 1 and the AND circuit L / 2. Circuits L / 5, L / 6 and L / 7 released so that the output signals f, g and h of the counter Z reach a selection device F. The selection device switches the clock / 1 to i8 assigned to the respective counter reading through to the AND circuit U 4. The AND circuit L / 4 remains blocked until the end of the evaluation; a delay circuit D.

The pulses following the first pulse b at time 14 each switch the flip-flop FF2. It acts as a frequency divider and therefore only advances the counter by one digit ■ -, after every second input pulse. The counter has currently counted 14 to 110 (binary) = 6 (decimal). Due to the negative edges of the output signal from FF2, it continues to count until 001 (binary) = 1 (decimal). The clock f2 belongs to this counter reading, and this is the optimal clock for the

ίο assumed correlation case.

With the release of the AND circuit LJ 4 , the clock f 2 is switched through from the selection circuit F to the memory S, which is used to receive the message block. The next negative edge of (2

ii therefore initiates the takeover of the message block in the memory.

A pulse e, not shown in the diagram, moves the flip-flops FF1 and FF2 to their initial position brought and the clock shutdown from the correlators is canceled.

For this 3 sheets of zcicliiuiimcn

Claims (2)

Patent claims: 1. Method for receiving phase synchronization to the phase position of the bit clock of a received data block which is preceded by a bit sequence which is used for phase synchronization and contains a code word identifying the beginning of the data block and which is compared by means of digital correlation with an identical bit sequence stored on the receiving side, in particular in time-division multiplex data transmission systems, characterized in that the bit sequence consists only of the code word characterizing the beginning of the data block, that the bits of the bit sequence are fed in parallel to N correlators (DK 1 ... DK 8), their associated shift registers with - on the bit duration T related - shift clock pulse sequences (ti ... (8) offset in time from one another by 7'W are incremented, and that the middle of the correlators supplying the correlation value 1 is determined and the clock rate of the shift clock pulse sequence incrementing its shift register is taken as the phase-synchronous bit clock d. 2. The method according to claim 1, characterized in that the mean correlator is determined by means of a ² log A-digit binary counter (Z) , starting with the shift clock pulse sequence (ti) assigned to the shift register of the first correlator (DKi), until the first occurrence of the Correlation value 1 counts with the clock frequency N / T and from then until the last occurrence of the correlation value 1 with the clock frequency N / 2T , so that the counter reading reached the last time the correlation value 1 occurs indicates the ordinal number of the mean correlator to be determined.