DE2141714B2 - DEVICE FOR DETECTION OF DATA - Google Patents

Description

The invention relates to a device for the detection of data signals obtained from a z. B. magnetic Data memory and are preferably read out as binary characters, the distance between each corresponds to two adjacent signal transitions of a bit cell or the multiple value of a bit cell, with the help of integration links.

The data recognition for signals with different states with the help of the integration has opposite those with an evaluation of the signal lengths have the advantage of a low susceptibility to interference as well as a greater sensitivity to the data signals. In many systems the signal is on two different states that each represent one of the two binary values (NRZ signals). At a Another embodiment are a transition between the signal states as the one binary value and the The absence of this transition at a certain point is marked as the other binary value (NRZl signals). Further display options for Data signals are known, e.g. B. phase-coded signals, frequency-modulated signals, etc.

As the speed of the data increases, so do the requirements for sensitivity and reliability the recognition systems are also larger. In the case of one made to recognize the data In the known systems, integration of the data signals must be part of the recognition period for this can be used to return the output signal of the integration element to a reference value. This part is the greater, the higher the data speed with the same feedback time.

It is therefore the object of the present invention to provide a device for recognizing data signals Help to create integrators, in which the adverse influence of the feedback time of the output signals of the integration members is not given and thus during the entire recognition period one Integration can take place. This object is achieved according to the invention in the device mentioned at the beginning solved in that two integration elements are provided for each signal state, which logic circuits for the allocation of the input information depending on its signal status and

from the state of a binary clock signal synchronized with it are connected upstream in such a way that they are alternately switched on for the duration of a clock pulse signal when the corresponding data digital state is present and then returned to a reference value in their integration pause determined by the subsequent clock time, and the outputs of the one Data signal state associated integration elements are combined and connected to an input of an amplitude comparison device controlled by the clock signal, which compares the amplitudes of the applied signals at intervals of one bit cell at the time of a possible transition between two data signal states, with the respective polarity of the determined in a comparison Difference signal, the data signal status in the preceding interval corresponding to the length of a bit cell can be determined. The data signals are preferably binary signals and a clock signal period is equal to the duration of two bit cells, whereby, due to gate circuits in front of the four integration elements, integration by the first and second integration elements is provided when the data signal has the first binary state and a division between these integration elements is done in such a way that the first integration element is switched on when the first signal state of the clock signal is present and the second integration element is switched on when the second signal state of the clock signal is present, and integration by the third and fourth integration element is provided when the data signal has the second binary state and a division between these integration elements is carried out in such a way that the third integration element when the first signal state of the clock signal is present and the fourth integration element when the second is present Signal state of the clock signal are switched on. The state of the amplitude comparison device is sampled at intervals of one bit cell. A constant input current source is preferably assigned to each integration element. For the feedback of the output signal of an integration element, a speed is advantageously provided which is only slightly greater than the speed of the rise of this output signal during the integration.

The invention is explained in more detail below with reference to an embodiment shown in the figures. It shows

F i g. 1 the block diagram of a device for recognizing data signals,

F i g. 2 a larger number of idealized curves of the in the device according to FIG. 1 occurring Signals,

Fig.3 further details from the device according to F i g. 1 and

F i g. 4 and 5 the conversion of phase-coded signals into NRZ signals and frequency-modulated Signals in NRZI signals.

The data stored on a magnetic recording medium 11 in FIG. 1 are transmitted via a Read head 12 sensed. They are differentiated in a differentiation stage 13 and then one Phase shifter and limiter 14 supplied. The differentiation stage 13 can also have compensation circles included for interfering signals. The phase shifter and limiter 14 generates amplitude limited Signals (+ D) 10 from the recorded signals and makes them available on a line 15. Corresponding complementary, i.e. reversed in polarity, signals (-D) are applied to one at the same time Line 16 released. In both signal trains, there is a change between the signal states within a data period from plus to minus or vice versa a binary one, while the absence of a such signal transition indicates a binary zero within one data period.

The signal 10 on the line 15 and also the complementary signal on the line 16 are fed to a clock generator 20 with a variable frequency, whereby this provides clock signals 21 and 22. The clock signal 21 has a period which corresponds to the data period. When the speed of the recording medium 11 changes, the clock generator 20 changes the frequency of the clock signals it generates in a corresponding manner. The clock signal 22 (+ C) is derived from the clock signal 21 and sent to a line 23. The complementary signal (-C) appears on a line 24. The clock signal 21 is fed to a comparison circuit 40 via a line 25, where it causes the data signals to be sampled.

The data signals 10 as well as the clock signals 22 and the corresponding complementary signals become integrators 30 and 31 forwarded. The ratio of the output amplitudes of these two integrators is shown indicates the polarity of signal 10 during the immediately preceding sample period. The sampling period extends between successive bit cell centers. The integrator 30 integrates the positive components of the data signal 10 (+ D). The integrator 31 integrates the negative components of the Signal 10 (- D) by the positive components of the signal complementary to the data signal 10 on the line 16 integrated. Because both integrators process signals of the same polarity, a simplified one is obtained Circuit design and increased reliability.

Since both integrators 30 and 31 are constructed identically, the parts used in them receive the the same reference numerals, those in the integrator 31 additionally being provided with a prime. Everyone Integrator has two integration members 33, 34 and 33 ', 34'. The integration member 33 is effective when both the data signal 10 and the clock signal 22 have the positive signal state (+ D + C). That Integrator 34 is switched on when the data signal 10 the upper and the clock signal 22 den have lower signal state (+ D-C). The integration elements in the integrator 31 are effective when the data signal 10 has the lower state. The integration member 33 'works when the Clock signal 22 has the higher signal state (- D + C) and the integration element 34 'when the Clock signal 22 is also in the lower signal state (- D - C). The two elements of integration are one Integrators are thus alternately actuated by the clock signal when see the data signal 10 in one of its two states. In this way, the entire data period can be used for recognition will. No parts of this data period are lost for the return of the integration links. the Using a substantial portion of the subsequent detection period allows slow recovery the output value of an integration link. As a result, the frequency requirements for the

Feedback loop and the occurrence of interference signals are reduced as well as a highly smoothed output signal of integrators.

The signal 35 in FIG. 2 is the output signal of the integration element 33. It always shows when the Data signal t0 and clock signal 22 have their upper state, a linear increase. The signal 36 is the starting siena) of the integrating member 34. It has a positive rise when the data signal 10 has the upper signal state and the clock signal 22 the have lower signal state. Accordingly, the signal 35 'is the output signal of the integration element 33 'and the signal 36' that of the integration element 34 '. The outputs of the integrators 33 and 34 are combined in an analog OR circuit 38. The output of this OR circuit is fed to the comparison circuit 40 via a line 39.

The analog OR circuit leaves that one of the signals present at its inputs pass that has the greatest amplitude of a given Has polarity In the present example, this is positive polarity. On the line 39 thus occurs in F i g. 2 shown signal 41, which is composed of the signals 35 and 36 and in each case that of corresponds to these two signals, which has a higher amplitude than the other.

The output signal of the integrator 33 is in the time periods in which the clock signal 22 is the has lower state, traced back to a reference value at Integrationsgüed 34 takes place when the clock signal 22 has the upper state, the Feedback preferably takes up a substantial part of the sampling period following an integration, for example 75% of this. A sampling period advantageously corresponds to a bit period of the data signals.

The scan, i.e. H. the recognition of the data signals takes place immediately after each sampling period, i. H. in every cell center. The sampling time is given by the upward transition in the clock signal 21. Circuit 45 responsive to these positive junctions brings a transistor over line 104 46 briefly in the conductive state. As a result, the comparison circuit 40 is excited as follows will be explained. Between these sampling times the transistor 46 is non-conductive, whereby the comparison circuit 40 is blocked by this selective control of the comparison circuit 40, the signal 125 in Figure 2 is obtained on a Output line 47 and the complementary signal on a line 48.

The following is the selective control of the integration elements 33 and 34 and the feedback their output signals are described in more detail. Two special AND circuits 55 and 56 are connected to lines 15 connected to 23 or 15 and 24 and »eggs constant input signals to the integrators 33 and 34 during predetermined periods of time. One such a special AND circuit is illustrated in FIG. 3 will be explained. The constant input signals of the integration elements cause their output signals to increase linearly with time and so one reliable indication of the duration of each signal state of the data signal 10 during a sampling period give. When the clock signal 22 on the line 23 or the complementary signal on the line 24 den Have the lower signal state, then a constant current source is provided via the associated AND circuit 55 or 56 57 or 58 connected to the input of the integration member 33 or 34, whereby the Output signal of the respective integration element at a given speed to a given speed Reference potential is fed back. When this is achieved, the effectiveness of the appropriate Constant current source 57 and 58 repealed. if

, o the clock signal 22 the upper and the data signal 10 have the lower state on the line 15, then no input signal is received by the integrator 33 fed. However, the upstream impedance is so great that the output signal of the integration element maintains the achieved value. This is in FIG. 2 shown at 64, 65 and 71

The mentioned ability to keep the output signal aul an achieved value is an advantage in the Elimination of interference signals in the data signal 10. The dashed curves 60 and 61 in FIG. 2 show two such spurious signals. The interference signal 61 sets the integration element 33 into action, as by the rise 62 is indicated in curve 35. After the end of the glitch, the output signal keeps it Integration link its value at, as the horizontal section 64 of the curve 35 shows Integration element 33 'is also influenced by this interference pulse 61. While this is occurring Interference pulse does not work the Integrationsgüed 33 'but its output signal is already at that achieved value. This corresponds to the potential 65 irr curve 35 '. After termination of the interference pulse wire the integration continues, as the rise 67 shows.

At the time of the subsequent bit cell center 68, the amplitudes of the signals 41 and 41 become compared to each other. Since the amplitude of the signal: 41 'at 70 is greater than that of the signal 41 at 71 the lower state is displayed in the data signal (-D; This means that no state change irr Data signal has taken place and thus a binary zero was sampled in d> 1 cell center 68. There; However, the interference signal results in a reduction in the differences between the two signals 41 'and 41. A similar The problem occurs when there is a

Shift of transitions takes place Such a shift occurs when transition 72 fails in the cell mesh, but for example first spatula takes place as indicated by 73. The present detection device can such phase shift Compensate exercises that go up to the through 7 < approach the marked cell boundary between two cells in the middle. Such strong shifts before However, 50% does not usually occur. Typical «shifts are around 25%. A phase error can be displayed when the output amplitudes of the analog OR circuits 38 and 38 'are about the same are.

to achieve such immunity to interference need a relatively sensitive comparison circuit

and linear and identical integrators are provided

be. The F i g. 3 shows an advantageous linear action:

Integrating element and a preferred comparison circuit

with high sensitivity It will be de

Integrator 30 described in more detail, with advance law

is that the integrator 31 is constructed in the same way

The integrator 34, the AND circuit 56 to

the clock circuit 80 A for the integration element 34 sin <

also shown only in blocks. The data signal 11

on line 15 is fed via an inverter 81 and the AND circuit 55 at the emitter of a transistor 82. A clock circuit 80 brings the transistor 82 into the conductive state so that it can transmit a signal with a constant amplitude from the inverter 81 to the integration element 33. The clock circuit 80 receives a clock signal at the base terminal of a transistor 83 via the line 23. Whenever the signal on the line 23 is in the upper state, the transistor 83 is conductive, whereby the potential on a line 84 is reduced to the negative potential -Vl is brought. A constant current source 85 thereby causes a constant current through the collector of transistor 82. This is directly connected to an integration capacitor 87, which is charged linearly. The base connection of a transistor 88 in the integration element 33 is connected to the integration capacitor 87. The output signal of the integration element is taken from the emitter of this transistor and fed to the analog OR circuit 38 via a line 89. This also the output signals of the integration element 34 are fed via a line 34 A. The analog OR circuit 38 allows the signal on lines 89 and 34 A to pass which has a greater positive amplitude. For this purpose, a resistor 90 is provided, one end of which is at a negative potential -V. The voltage drop across this resistor 90 is determined by the signal with the larger positive amplitude. The line 39, which leads to the comparison circuit 40, therefore has this potential.

The clock circuit 80 also causes the integration element 33 to be returned to the initial state during the subsequent detection period. This happens when the clock signal on line 23 in the lower state passes. The transistor 83 is then blocked. This increases the potential on the line 84 on, so that the transistor 95 goes into the conductive state. At the base of this transistor 95 is a fixed preload. The collector of this transistor is connected to the base of the feedback transistor via a line% 100 connected in AND circuit 55. The integration capacitor 87 discharges through this Transistor 100 at constant speed up to about the potential -Vl. A diode 101 is in parallel with the The base-emitter path of the transistor 100 is connected and forms a well-known constant current connection. The discharge rate of the capacitor 87 becomes determined by the value of the emitter resistance of transistor 100. The constant current source 85 can can also be formed by a diode placed in parallel with the base-emitter path of the transistor 83. This is then in series with a resistor between the line 23 and the potential -Vl switched

The output signal of the analog OR circuit 38 is via the line 39 to an input of the Comparison circuit 40 given. In the same way, the output signal of the suction-ODHR circuit is also activated 38 'of the integrator 31 is fed via a line 39' to a second input of the comparison circuit 40 This comparison circuit essentially corresponds to one already in the IBM Technical Disclosure Bulletin. Circuit published February 1964 on page 69. The present comparison circuit shows this however, there are some improvements that result in increased sensitivity in particular.

The comparison circuit 40 includes two cross-coupled transistors 98 and 99. The emitters of these both transistors are connected to one another via a line 105 and to the collector of one Transistor 102 connected in common base. The emitter of this transistor is connected to the emitter of the Transistor 46 is connected and is connected to the potential -Vl via a suitable resistor. Of the The collector of the transistor 46 is connected to ground potential. As shown in FIG. 1 can be seen, receives the

ίο base connection of transistor 46 via line 104 Clock pulses that unlock the comparison circuit 40.

Before a sample time, the emitter terminal of transistor 102 is relatively negative Potential, whereby this transistor is kept conductive. This also causes the emitters of the transistors 98 and 99 brought to a relatively negative potential, so that both transistors 98 and 99 are blocked. the active elements of the comparison circuit 40 are thus negatively biased and can respond to signals to the both inputs of the circuit do not respond. At the sampling time, i. i.e., immediately after each bit cell center, the transistor 46 is made conductive by a pulse on the line 104. This has the consequence that the transistor 102 is blocked and the potential on the line 105 increases. The switching status of the Transistors 98 and 99 thus become dependent on the potentials on lines 39 and 39 '.

A special input circuit for the comparison circuit 40 increases the sensitivity of the comparison process. For this purpose, there is a constant current source 110 with the emitters of two input transistors 11 * and 112 tied together. The signals on lines 39 and 39 'are each via one of these two input transistors transferred to the bases of transistors 98 and 99. The constant current source 110 causes an exact current division between the two transistors 111 and 112 as a function of their Base potentials. Therefore, a more precise comparison of the signal amplitudes on lines 39 and 39 ' be performed. The potentials on lines 113 and 114 are therefore firmly connected the output potentials of the integrators 30 and 31. Any possible change in the from the current source 110 supplied current affects both inputs of the comparison circuit in the same way. By Appropriate choice of transistors 111 and 112 can be made continue to achieve temperature compensation.

The output circuit of the comparison circuit 40 includes two transistors 120 and 121 with one common KoUektorverbind.die via a diode 122 to ground potential The collectors of the Transistors 98 and 99 are connected to the base electrodes of transistors 120 and 121. When the signal on line 39 has a greater amplitude than that on line 39 ', then the transistor 98 conductive. A relatively negative potential occurs at the base electrode of the transistor 121. In contrast the potential at the base of transistor 120 becomes positive, so that it becomes conductive. The

Diode 122 and transistor 120 bring line 4a to approximately ground potential Line 39 'is larger than that on line 39, then this process runs in the same way, but with it opposite sign, from. Receives on line 47

the signal 125 shown in FIG. 2 is then obtained. The pulses occurring in this signal coincide in time with the clock pulses on the line 104.
The positive or negative impulses on the

609 5Β4 / 2Ί6

Lines 47 and 48 only take up part of a bit. Due to the frayed state of the Comparison circuit 40, an output switch 51 is set or reset, the at its Output occurring signal 12 <> the data signal 10 The conversion of the data signal 126 into differently modulated signals is known and is used here no longer considered

The device shown in Fig. 1 can also be used for phase-coded or frequency-modulated signals, if the phase shifter and limiter 14 an EXCLUSIVE-OR circuit added. As in F i g. 4, the EXCLUSIVE-OR circuit 150 receives phase encoded input signals 151 (Fig. 5) via line 152. This signal has been differentiated in a known manner and in amplitude limited. The signal 21 of the clock generator 20 is the other input of the EXCLUSIVE-OR circuit fed. At the output of the circuit 150, due to the combination of the signals 21 and 151, the signals shown in FIG NRZ signals 153 shown. These are via the line 15 or in complementary form via the Line 16 is fed to AND circuits 55, 55 ', 56 and 56.

When the signal 151 is frequency modulated, i. i.e., at the cell boundaries the transitions occur, true If they are in the cell position for phase-coded signals, then the output signal is the EXCLUSIVE

ίο OR circuit 150 a NRZI signal. The recognition these signals takes place in the same way as the de NRZ signals, although the meaning of the rekon structured signal 126 is a different one.

The present device can also be used for RZ (Return to Zero) signals and other informa tion-containing signals. Additional measures can be used for processing these signals, such as those for phase-coded and frequency-modulated signals have been described be made.

For this purpose 2 sheets of drawings

Claims (7)

Patent claims: 1. Device for the detection of data signals from a z. B. magnetic data storage and preferably read out as binary characters, the distance between two adjacent signal transitions of a bit cell or the multiple value of a bit cell, with the help of integration elements, characterized in that two integration elements (33,34; 33 ', 34') are provided, which logic circuits (55, 56; 55 ', 56') for allocating the input information depending on their signal state and the state of a binary clock signal (22) synchronized therewith are connected upstream in such a way that they are present when the corresponding data signal state are alternately switched on for the duration of a cycle time of the clock signal (22) and then returned to a reference value in their integration pause determined by the subsequent cycle time, and that the outputs of the integration elements (33,34; 33 ', 34' assigned to a data signal state) ) summarized and with each ils are connected to an input of an amplitude comparison device (40) controlled by the clock signal (21), which compares the amplitudes of the applied signals at intervals of a bit cell at the time of a possible transition between two data signal states, with the polarity determined during a comparison Difference signal the data signal state in the preceding, length e ^; ner bit cell corresponding interval can be determined. 2. Device according to claim 1, characterized in that the data signals are binary signals and the clock signal period is equal to the duration of two bitsHen, with a result of four integrators (33, 34; 33 ', 34') of horizontal gates (55, 56; 55 ', 56') ei.the integration by the first (33) and second (34) integration element is provided when the data signal (10) has the first binary Has state and a division between these integration members made in the way is that the first integration element (33) when the first signal state of the clock signal is present (22) and the second integration element (34) when the second signal state of the clock signal is present (22) are switched on and integration by the third (33 ') and fourth (34') integration element is provided when the data signal (10) has the second binary state and a division between these integration elements in the way is made that the third integration member (33 ') in the presence of the first Signal state of the clock signal (22) and the fourth integration element (34 ') when the second is present Signal state of the clock signal (22) are switched on. 3. Device according to one of claims I or 2, characterized in that each integration element (33, 34; 33 ', 34') has a constant input current source assigned. 4. Device according to one of claims 1 to 3, characterized in that for the return of the output signal of an integration element (33, 34; 33 ', 34') a speed is provided which the speed of the rise of this output signal during the Integration. 5. Device according to one of claims 2 to 4, characterized in that the amplitude comparison device (40) a switch (51) is connected, at the output of which the binary data signal (126) occurs. 6. Device according to one of claims 2 to 5, characterized in that the amplitude comparison device (40) a bistable switch (98, 99) and means for blocking (46, 102) this switch between the sampling times. 7. Device according to claim 6, characterized in that the inputs of the amplitude comparison device (40) are led to two transistors (IfI, 112), which have a constant total current and via which the bistable switch (98.99) can be controlled.