DE2055356C3 - Raster synchronization circuit for digital communication systems - Google Patents

Description

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Si iiltung 4 is made up of counters i - w Ui 'I is passed on in dependence on the Au-uau .'- sigiuil ι Oi- blanking gate 3. um \; -rseh; edene Z. liiteuerimpuiszüge at the • Nusgnnii ^ 's'emmen 9 to e:, - narrow, which the same period as the Kasierperi! .. ^! -.-own. This circuit 4 can have a counter 30 se: r. ·. as it is in Chapter 18 of.-Pulse. Digital and Sv-. !! china Waveforms ^ by Jacob M i 11 ma η η i:! ui Herbert Taub, published: by the MeCiraw-Hill Book Company in the year 1465. Circuit 5 for raster synchronizing pulse generation receives the timing pulse signals from circuit 4, whereby only one preliminary synchronizing pulse r is generated in each raster period. The circuit 5 can, as described in Chapter 9 of the above publication, be formed in AND gates. In general, the temporal position of the preliminary synchronization pulse c behaves according to the original state of the receiving-side circuit. This temporal position does not always coincide with the temporal position of the synchronizing pattern. of the received pulse train. For this reason, synchronization is required in order to bring the two time positions into coincidence. In the case of the in FIG. 1, the synchronization process is effected by a circuit loop which comprises the blanking gate 3, the circuit 4 for the timing pulse generation and the circuit 5 for the raster synchronization pulse generation. The circuit loop further comprises a pre-gate 6 for suppressing the synchronizing pulse c when the pulse d is generated. In addition, the line loop has a delay circuit 7 for delaying the output signal d of the pre-gate 6. The blanking gate 3 suppresses or blocks the clock pulses every time a delayed synchronization pulse e with the output of the delay device 7 occurs.

In the case of the FIG. 2, the correct position of the synchronization pulse of the receive pulse train occurs at time T ₁ . on, and the presynchronization pulse c is at the time 7 '., erveuai. At this point in time the clock pulse 7 "., Reaches demtiemul." the circuit 4 to the timing pulse generation and this represents ;.> chaltung 4 corresponding to continue after the time T _1. as long produces no Auinahrneimpuls /), appear until the next pulses of the S \ nchronisiersinnalmiisters in 'tem received Impuls7ui. In this Wci-e the position of the synchronization pulse c generated on the receiving side is brought into coincidence with that of the synchronization pulse.

In this circuit, blocking or blanking of the Ausasigattt-rs 3 is essential. In order for this process to be properly maintained, the time interval in which the successive process in the line loop is completed must be less than a tactiiilervLÜ. Fin such successive prelude begins with the application of a clock pulse to the blanking gate 3 and ends with the application of the delayed synchronizing pulse c to the blanking gate 3. In the circuit shown in FIG liinzelschaltung each equal to zero and dab the Verzögerungsschaitung 7 is a \ e ^r delay -. / e \ t of about three quarters of a Taktintcrvalles ei / EUGT. In practice, however, an on / cit delay is inevitable in every fin circuit, and therefore the raster synchronizing circuit should be designed with such a delay time in advance.

With reference to FIGS. ? and FIG. 4, the embodiment shown therein has the same structure as the decoded circuit, with a received pulse train being applied in the same way to a company output terminal 101 , a synchronizing signal pattern recording pulse h being generated by a synchronizing signal recording circuit 108 , clock pulses generated by a clock pulse source 102 are applied to a Austastgatter 103 whose blanking or inhibit input is fed by a delay circuit 107 I, and further, the Ausgangsimpuisc m a circuit 104 are fed to timing pulse generator which supplies the timing pulse trains output terminals 109, and further wherein a pre-synchronizing / by a circuit 105 generated for synchronizing pulse generation and the synchronizing signal pattern pulse h st ^ as the presynchronizing pulse / are applied to a raster synchronizing circuit

the. Due to the inherent propagation delay, the pre-gate 106 generates the discoincidence pulse / at a first delay time /) after the generation of the pulse /. This latching synchronizing circuit comprises a flip-flop circuit 110 which is switched by the discoincidence pulse / in order to generate an output signal k for the first delay training 107 after a delay time D. The raster synchronization circuit further comprises a second delay circuit 111 which is connected between the output terminal of the synchronization signal recording circuit 108 and the reset terminal of the flip-flop circuit 110 in order to reset this circuit 110 after the generation of the pulse after a third delay time D. is essentially equal to the delay times D ₁ ID ,,.

In the circuit according to FIGS. 3 and 4, it is assumed that the correct synchronization position 2 " _{exists at time T 5} and that the pre-synchronization pulse / 'is generated at time T _3. switches the flipflop circuit 110 via the Vorgatter 106 at a time D ₁ 4 D ₂ after the generation of the pulse /. The Signalmustcraufnahmeimpuls / 1, which is generated at the time 7 _'5, sets the flip-flop circuit HO at a time D .. after the line point T. The width of the output signal k of the flip-flop circuit 110 is equal to a whole multiple of the clock pulse interval, which is equal to the time difference between the generation of the presynchronization pulse and the generation of the pulse / 1. Therefore, so many clock pulses c g to be applied to the circuit 104 for timing pulse generation are blanked that the generation of the next synchronizing pulse / is in synchronism with the generation of the next synchronizing signal pattern recording pulse / 1.

Incidentally, the first delay circuit 107 is used to bring the leading and trailing edges of the blanking pulse 1 generated out of coincidence with the corresponding edges of the clock pulses g , and this circuit can therefore be dispensed with if the delay period D, -t D “Or D _{n is} quite different from the clock interval or an integral multiple thereof.

It is thus now clear that the propagation delay of the circuit loop that always occurs is not directly related to the synchronization process. Furthermore, the size of the running line delay of the circuit loop should only be a value with which the synchronism is restored at the time of the occurrence of the next synchronization signal pattern in the received pulse train and which need not be less than one clock time interval. It is also possible to blank the required number of clock pulses g at any time interval during a raster which generally comprises more than a few hundred bits. Due to the transit time delays in the lines and other delays, the in Fi g. The phase relationship shown in 4 must necessarily not be observed. It should be noted, however, that since a wide variety of pulses generated in the present system are synchronized with the clock pulses, the invention can be used regardless of the phase relationship.

1 sheet of drawings

Claims (1)

1 ° 2 of the receiver ropes generated a discoincidence pulse Claim: if there is a coincidence between the synv.nro- nisiersignalmusterimpuls. which is generated when that Raster synchronizing circuit for digital synchronization systems contained in the received pulse train with a device for recording or scanned generating a synchronization signal pattern. uno the synchronizing impulse. which is generated by SCs, if at least one pulse of a w: rbe-use of \> ^λ : ι of a time period matched \\ nchroniaiersignalmuster in the given Zeustcuenrnpu ^ en. fail, if the digital impulse train appears, one au! in the case of the device which addresses the clock pulses and which is to be fed to the timing circuit: -. impulses suppressed by the Diskoi'izidenzimpuls · - generating a Rastcrsynehronisierimpulses in or blanked. every rasi, period. This V, nchronisingerschaliuni: will not nchr.g testify to a Di-koin / i.ieiViPipulses when he.-ieberi. if not the delay time line: the S \ r, chronisiei impulse is not in coincidence with the synchro between the application of a clock pulse and the nisiersignalmiisicrinipuK ij Lrzeu ^ un ·; of the discoincidence pulse is smaller than a lesser, and an adjustment to the off clock interval. In practice, however, it is often the load or blocking of an appropriate number of full that the delay or transit time of the switching of the clock pulse. to create a. Starting 20 stone. This is the reason why a conventional pulse (/ ι-) of a width with which the required synchronization circuit cannot always be used with the same number of clock pulses. digital communication systems is suitable.
a second device (circuit path with From the German Auslegeschrift 1 277 91 2 is fer gate 106: for supplying the Diskoinziuenz- ner a synchronization method is known in which impulses / l of the first device (110) and 25 the clock pulses during every second sampling period of a third . Device! 1! 1 ί for supplying the to be shifted by one bit until the synchronous synchronizing pattern pulse to the first assignment of the received pulses to the pulse field device. The width of the output menu is reached. With this method, the pulse (A ) Due to the time difference between the recovery period, the discoincidence pulse and the Svn-30 be correspondingly longer than is determined in the above-mentioned method according to US Pat. No. 3,065,3 () 2 or in the raster synchronization circuit according to FIGS. 1 and 2 described below as known. The invention is based on the object of a 35 raster synchronization circuit to create in which the Difficulties that arise with regard to the running time, are practically turned off. In the previously known circuits was The invention relates to a Rastersynchronisier- always uses a common circuit path, circuit for digital communication systems such as 40 to initiate clock pulse suppression or a PCM communication system. being the syn- cancel. According to the invention, however, this Chronizing circuit work at high clock frequencies. Circuit path divided into two paths. Furthermore, ten can. the time difference between the synchronization signal With digital communication systems, in particular the sample pulse and the synchronizing pulse, the those in the PCM communication system, the 45 generated on the receiving end is measured directly, Digital signal to be transmitted by word or grid to generate the next timing pulse sent in multiplex. Therefore, a grid is around one of the time difference or the time difference Synchronization device necessary, which means that the corresponding value is shifted in time. Through Word sequence on the receiving end exactly and correctly Applying this principle is the running time. η can be identified. Usually a pre-50 factor becomes of secondary importance. With the certain special signal pattern, which makes it possible to use a raster synchronization digital signal does not accept on the transmitter side to circuit with quick recovery time for the inserted in a special position in each grid. To create synchronization, so this circuit On the receiving end, the specific signal is also used for digital communication systems with high pattern to the timing circuit in synchronization 55 clock frequencies can be used at which the running to bring, recorded or scanned, whereby the switching time is no longer negligible. the raster synchronization is effected. Two types The use of the circuit according to the designation is mainly of synchronization patterns are known. The one special is expedient in cases where a The type consists of synchronizing a bit in each raster consisting of a large number of bits while the other type is, 60 is used. a series of several bits in each grid. use. The latter type is explained in more detail by its rapid matic drawings. Recovery time for you. Synchronization marked- Fig. 1 shows a block diagram of a previously used draws. borrowed raster synchronization circuit; An embodiment of a raster synchronizer 65 Fig. 2 shows a timing diagram for illustration circuit is in U.S. Patent 3,065,302 of the operation of the in Fi g. 1 circuit shown; Hisashi Kaneko has been described. Briefly Fig. 3 shows a block diagram of a grid tzesast, this circuit is operated so that on synchronizing circuit according to the invention while