DE1948377C3 - Circuit arrangement for processing binary variables - Google Patents

Description

The invention relates to a circuit arrangement zui Processing of binary variables, which consists of similar logic elements, each of which is divided Using a magnetic core with a rectangular hysteresis loop, which when Ver

link condition during a writing process in one of its two remanence states and during the subsequent interrogation process by an interrogation pulse back to the original other Remanence state is magnetized out, where he s emits a read signal, and in which such read signals other such linkage elements can participate in the fulfillment of the linkage condition should.

The links that make up the circuit ι ο Assembling arrangements for processing binary variables are often implemented using a Magnetic core with a rectangular hysteresis loop because they have a number of advantages, such as unlimited service life, high reliability, Storage capacity, as well as integrating properties that have a beneficial effect in the event of malfunctions. At acquaintances Linking elements of this type is during the writing process either by the coincidence of Variables to be linked with a write pulse of the magnetic core in one of its two remanence states magnetized or due to the opposing action of the coincident pulses such a reversal of magnetization is prevented. A subsequent interrogation pulse magnetizes the core, if it has previously been remagnetized, back to the original remanence state, in which case a read signal is emitted. If the read signals of such operated logic elements than further Variables to be processed are to be fed to downstream cores, special measures must be taken be taken to a temporal coincidence of such read signals with the also the write process still to ensure determining other signals. In the event that all cores from a central -o Pulse source write-in pulses can be supplied, can be according to a known solution (Steinbuch, Taschenbuch der Nachrichtenverarbeitung, 1967 edition, page 428) avoid this difficulty in that the write pulses are generally made shorter than the shortest of the read pulses to be expected.

It has also already been proposed (DT-OS i9 47 615) for a circuit arrangement for processing binary variable in which the logic elements of the same type are NOR elements, the write-in pulses not to be supplied from a central point, but rather by means of the read signals of these logic elements controlled modules of the same conception, whose read signals represent the write pulses and the the desired short one by reducing the number of turns of the reading and control windings accordingly Have duration. In the case of logic elements written in this way, the write-in pulses carry the write-in pulses for the logical connection with, which simplifies the wiring, because in such logic elements the write winding is identical to a control winding. Besides that This type of control has the advantage that not all of the cores that do not have them in the reverse direction influencing variable to be processed are supplied, are written, so that a total of one less energy is required for the central delivery of interrogation pulses, resulting in a saving of interrogation pulse amplifiers leads.

The invention now provides a circuit arrangement in which, on the one hand, the temporal Coincidence of the pulses involved in the writing of the individual logic elements ensured and which also has the advantages of using the proposed solution mentioned above. Bauswinen for the decentralized generation of write-in pulses with it, can also have without that this, however, such additional modules are required.

For this purpose, the circuit arrangement described at the outset is characterized according to the invention: that interrogation pulses are supplied with such a short duration that thereupon a magnetization in the saturation area corresponding remanence state is initially not reached, but by a the auxiliary pulse immediately following the interrogation pulse is set to such a small amplitude, that read pulses linked with this are not sufficient to remagnetize downstream cores.

As will be explained further below, the shortening made according to the invention has Interrogation pulses compared to known circuit arrangements in which the interrogation pulses the magnetic cores magnetize to saturation, the advantage that the length of the used for further processing Read pulse independent of component tolerances, temperature and wiring length and on the number of downstream devices controlled by the read signal of a core Cores is. In this way, however, read signals can also be written in without further measures downstream cores and thus as a contributing variable to the linkage, without the coincidence with read signals from other cores which may move the core in the opposite direction of magnetization have to influence is in question.

As embodiments of the circuit arrangement according to the invention, an exclusive-or element, a bistable multivibrator, a frequency divider and a binary counter are specified.

In the following, the structure and mode of operation of exemplary embodiments of the invention Circuit arrangement explained in more detail with reference to 10 figures.

The F i g. 1 shows an example of a known logic element from which the inventive Circuit arrangement is assembled.

The F i g. 2 shows the symbolic representation for such a linkage, which is also used for representation of the individual embodiments is used.

The F i g. 3 shows the hysteresis loop of the cores used for the logic elements.

The F i g. 4 to 7 show embodiments of the invention Circuit arrangement for processing binary variables, namely

the F i g. 4 an exclusive OR element,

the F i g. 5 a bistable multivibrator,

the F i g. 6 a frequency divider and

the F i g. 7 a binary counter.

In the case of the FIG. 1, which is known per se, is a NOR element. It contains a magnetic core M, which should have a rectangular hysteresis loop, and which is symbolized by a vertical, strongly drawn line. This magnetic core has a series of windings, which are indicated by short lines that symbolize the magnetic core at 45 °. By inclining these lines to the right or left, the different one becomes

Winding sense of the windings indicated. The lines intersecting the core horizontally indicate the supply lines of the individual windings.

The magnetic core M carries an interrogation winding η 1, an oppositely wound reading winding η 2 to which the diode D is connected, a writing winding η 3, which is also wound in the opposite direction for the interrogation winding, and a number of logic windings η 4, the direction of which is in turn opposite to that of the writing winding η 3 is. The number of turns of the read winding is chosen so that the read pulses emitted have at least the same amplitude as the write pulses. The NOR link comes about because the core can only be written to the line and thus a read signal can only be output during the subsequent query if a variable with the binary value "1" is not supplied to any of the logic windings. The diode blocks the circuit of the reading winding η 2 when writing and suppresses interference currents up to their threshold value, which are induced when variables are fed to the logic windings.

In FIG. 2 is the link according to FIG. 1 shown in simplified symbols. The magnetic core M is illustrated here again by a vertical, strongly drawn line. The upper end of this line is assigned the positive remanence state of the magnetic core + Br or the binary value "1" and the lower end is assigned the negative remanence state of the core - Br or the binary value "0". The core windings are shown here in the form of arrows. The query winding η 1, the write-in winding π 3 and the windings π 4, to which the variables to be processed are supplied, i.e. all windings are supplied via the pulses that contribute to the remagnetization of the core, run in the direction of the line symbolizing the magnetic core in this representation. Depending on whether the impulses influencing the magnetic core cause magnetization in the direction of the remanence state + Br, the arrowhead is directed upwards or downwards Core beam gone. Since the interrogation pulses are supplied from a central point and are constantly present, no leads are drawn in the arrow symbolizing the interrogation winding, and this arrow is filled in, which indicates the particularly large pulse amplitude of the interrogation pulses. From the position of the arrows in relation to the center of the core bar marked by a small horizontal line, the time position of the pulses supplied to the windings or emitted via them can also be recognized. It can thus be seen that the interrogation pulses and the read pulses linked to them, on the one hand, and the write pulses and the variables to be linked on the other, occur during different periods of time

Based on the F i g. 3. which shows a hysteresis loop, how they used the magnetic cores to build the circuit arrangement according to the invention Linking elements according to FIG. 1 and FIG. 2 will have that of the circuit arrangement according to the invention underlying operating mode explained in more detail. If the magnetic core of a linkage member the circuit arrangement according to the invention inscribed has been, this is in the positive remanence state + Br. An interrogation pulse is then supplied magnetizes the magnetic core again in the direction of the negative saturation state - Bs In contrast to known arrangements, however, according to the inventive rule, the temporal Before the duration of the interrogation pulse is so short that de corresponds to a magnetization in the saturation range The corresponding remanence state -Br is initially not achieved. I. E. so that the interrogation pulse has already ended is before the steep left part of the hysteresis

ίο loop has been run through. It then arises, for example, in the FIG. 3, a remanence state Bx , although the interrogation pulse has such a large amplitude that the magnetic core is heavily overdriven. The magnetic core then acts primarily Na

is like a transformer, so that those with the queries pulses linked read pulses from the core properties and the output load of the core; are independent and have essentially the same duration as the interrogation pulses. It can

jo therefore read pulses supplied by different nuclei become, without further ado, by influencing one; further core can be linked without that special measures would have to be taken to ensure their temporal coincidence.

As the F i g. 3 shows, after interrogation with shortened interrogation pulses, a magnetic core is in an undefined remanence state Bx. The next interrogation pulse would therefore deliver a second read signal, albeit of a lower amplitude. In order for the cores to be in a clear remanence state again after each interrogation, according to a further feature of the invention, an auxiliary pulse is supplied to the magnetic core immediately after the interrogation pulse occurs, which the magnetic core

up to the steep part of the hysteresis loop. After the auxiliary pulse has subsided the negative remanence state - Br is then established in any case. The amplitude of this auxiliary pulse on the other hand, is still kept so small.

that the read pulses linked with this auxiliary pulse not sufficient to remagnetize downstream magnetic cores, i.e. not even in defective ones Way can fake the presence of a useful pulse.

As an exemplary embodiment of the circuit arrangement according to the invention, FIG. 4, an exclusive OR circuit is first described. The circuit arrangement according to FIG. 4 contains two logic elements with the magnetic cores £ 1 and £ 2, which are queried at the same time. The logic windings λ 14 and η 24 of these magnetic cores are connected in parallel and thus both contribute to the delivery of result variables. The input variable e 1 influences the magnetic core £ 1 via a write-in winding π 13 in

Writing direction and the magnetic core E2 via a logic winding η 24. which is connected in series with the winding η 13 of the core £ 1 against the writing direction. The input variable e2, however, influences the magnetic core £ 1 via the logic winding

π 14 against the writing direction and the magnetic core £ 2 via the writing winding η 23 in the writing direction. Each of the two magnetic cores £ 1 and £ 2 is thus derived from an input variable in the writing direction and from the other input variable.

fts influenced against the writing direction If these input variables, as explained above, are influenced by interrogation generated by other magnetic cores not shown here! we don't need any further action

Men be provided in order to ensure their temporal coincidence when acting on the two magnetic cores. The circuit arrangement according to FIG. 4 only supplies an output signal if only one and only one of the input variables takes on the binary value "1". Only in these two cases is the writing of one of the two cores £ 1 and £ 2 not prevented by one of the two input variables e 1 and el due to the blocking effect of the respective other input variables. One of the two cores then sends a read signal to the common output a. If, on the other hand, both input variables assume the binary value "1", writing is prevented due to the blocking effect of one input variable, or if both input variables assume the binary value "0", neither of the two cores is written due to the lack of a write excitation. In both of the last-mentioned cases, there is no reversal of magnetization of the cores during the query and therefore no read pulse is emitted.

In FIG. 5 describes an embodiment of the circuit arrangement according to the invention in the form of a bistable multivibrator with dynamic input, that is, such a multivibrator that is switched from one stable state to the other stable state in response to each input signal at one and the same input. The circuit arrangement according to FIG. 5 contains an exclusive OR circuit with the magnetic cores £ and A, as shown in FIG. 4 is shown, which is followed by a further logic element with the magnetic core R. The magnetic cores £ and A of the circuit arrangement are interrogated in a first interrogation cycle phase, while the magnetic core R is interrogated in a second interrogation cycle phase, which is indicated by the different positions of the arrows symbolizing the interrogation windings for the magnetic cores £ and A on the one hand and for the magnetic core R on the other hand. The read signals supplied by the magnetic cores £ and A via the read windings π 12 and π 22 influence the magnetic core R via its write windings nR3 in the write direction. The read signal of the core R emitted via the read winding nR2 represents one input variable of the exclusive OR gate formed by the cores E and A , so it influences the magnetic core A via the write-in winding π 23 in the write direction and the magnetic core £ via the winding π 14 in the reverse direction. The input variable el causing the switching of this circuit arrangement acts on the magnetic core £ in the writing direction and on the magnetic core A counter to the writing direction. The read signals from cores £ and A as well as the read signal from core A3 can be used as output signals.

In one of the two stable states of the circuit arrangement, none of the cores is written, so no read signals are emitted in response to the interrogation pulses. If the magnetic core £ is now written by the input variable e 1, this core sends a write pulse to the core R when it is queried, which in turn writes the magnetic core A when it is queried. In the case of further inquiries, the magnetic cores A and R write themselves in alternately and accordingly emit alternate read signals. This second stable state of the circuit arrangement is maintained until an input signal e 1 occurs again. However, the core E can now not be written because it is blocked by the core R here. On the other hand, the core A is blocked and accordingly no longer emits any writing impulses to the core R either. But with this all remain; Cores in the non-registered state until the cycle occurs again with an input pulse; repeated.

A tilting stage of the aforementioned type could per se also be different using only two Clock phases interrogated magnetic cores who built the, one of which in each case the writer excitation for supplies the other. Due to such feedback, however, the occurrence of minor, For example, temperature-related disturbances lead to the flip-flop in the more stable The state is switched in which both magnetic cores are alternately written in and read out.

The F i g. 6 shows an exemplary embodiment of the circuit arrangement according to the invention in the form of a four-stage frequency divider. Its second to fourth stages 52 to 54 are formed by bistable flip-flops, as shown in FIG. 5 have been described. The interrogation of the cores of these stages takes place in such a way that cores of the same order of successive stages are interrogated for the respective other clock phase. If, for example, the cores £ 2 and A 2 for the first clock phase and the core R 2 for the second clock phase are queried at stage 52, then at the following stage 53 the cores £ 3 and A 3 for the second clock phase and the core R 3 for the first cycle phase queried. The cores of the subsequent stage 54 are then queried again in each case at the same clock phase as the cores of the same order in stage 52. The read windings of those cores of the stages that carry the input winding used for writing are each connected to the input winding of the corresponding core of the next stage used for writing, as well as to the input winding used to block the core queried for the same clock phase. So the read winding of core £ 2 of stage 52 is connected to the input winding of core £ 3 used for writing and to the input winding of core A 3 of stage 53 used for blocking. The same applies to the connection of the read winding of the core £ 3 of stage 53 with the input windings of stages £ 4 or A 4 of stage 54. In the case of stages 52 and 53, the read signals of cores £ 2 and £ 4 also provide the output signal of the Step. For stage 53, whose core £ 3, as explained, is queried for a different clock phase like cores £ 2 and £ 4, an auxiliary core H 3 is also provided for clock conversion of the output signal, which is written by the read signal from core £ 3 and is queried simultaneously with the £ 2 and £ 4 cores.

The three bistable flip-flops 52 to 54 is a pulse divider stage connected upstream of the input pulses are supplied and each second input pulse suppressed These pulse scaler stage includes three magnetic cores El, At and L 1. The input pulses are the core £ 1 in Einschreibrichtung fed This core is the first clock phase, interrogated Its read signal excites the core A 1 of this reduction stage, which is interrogated for the second clock phase, also in the writing direction. The read signal of this core A 1 writes the third core L 1 of the reduction stage and the core £ 2 of the first bistable multivibrator of the frequency divider. The read signal of the core L 1 of the reduction stage blocks the core

703 607/136

A 1 and at the same time represents the output signal of this frequency divider stage.

If initially none of the cores El, A 1 and Li of the reduction stage S1 is registered, the first input pulse at the input F first inscribes the core £ 1, which in the subsequent interrogation cycles also includes the writing of the cores A 1 and L 1 and the delivery of a Read signal at output / 72. By interrogating the core L 1, however, the core A 1 is blocked, so that when a second pulse occurs at the input F , only the core E1 is written and therefore no output signal is emitted via the output F / 2. Since the core A 1 is no longer blocked, a third pulse at the input F again causes all three cores to be written in and an output signal to be emitted.

The read signal of the core A 1, which is also only emitted in response to every second input pulse, but occurs in the second interrogation clock phase, is fed as a write-in signal to the core E 2 of the stage S 2. This works in the basis of FIG. 5, thus leads to a further pulse reduction in a ratio of 1 to 2, so that at the output F / 4 supplied by it, an output signal is only emitted after every fourth pulse. The same applies to the further scaling through stages 53 and 54, at whose outputs F / 8 and F / 16 output signals are emitted on every eighth input pulse and every 16th input pulse.

In FIG. 6 the two cores M1 and M 2 are also shown, which are interrogated at different clock phases and apart from the interrogation windings each carry only one reading winding. The read winding of the core Ml is connected to a blocking winding of the core A3 of the stage S3 and the reading winding of the core M 2 is connected to a blocking winding of the cores /? 4 and R 2 of the stages 54 and S 2. Since the nuclei M1 and M2 do not receive any write excitation, they only emit signals of low amplitude, which correspond to the respective magnetization from the negative remanence state of these nuclei to the negative saturation state. The abovementioned supply as inhibit signals to the designated R cores of the bistable multivibrators is ensured that the respective feedback of the cores A 2 and R 2, A 3 and R 3 Rowie A 4 and R 4 at temperature-related disturbances do not produce an unwanted switching of these Tilt stages leads

In FIG. 7 shows another embodiment of the circuit arrangement according to the invention in the form of a three-stage binary counter. B. at stage 51 the cores G 1 and Λ 1, to a first clock phase and the third z. B. N 1 were queried for a second clock phase.

The read signals of these first two cores G 1 and A 1 each act as blocking signals for the third core Ni. The read signal of the third core Ni magnetizes the first core G1 in the writing direction and the second core A 1 in the reverse direction. The second core A 1 and the third core N 1 are each written by a central write-in pulse source, which is symbolized by arrows without lead lines drawn in the relevant halves of the core bars

is ».
The read signal of the third core N 1 is fed to the first cores G 2 and G 3 of the stages S2 and 53 as well as a transfer magnet core U as a blocking signal. Transmission magnetic core Ü, which is also written to a first clock phase by a central write pulse source, magnetizes all third cores N 1 to N3 of stages S1 to S3 in the write direction with its read signal.

One to one is used to record the counting pulses

second clock phase queried magnetic core Z, which of

ίο the counting pulses is magnetized against the writing direction and its read signal magnetizes all first cores G 1 to G 3 of the stages of the counter and the carry core U against the writing direction. As long as the described counter takes the counter reading O, all cores of the stages labeled N emit a read signal for the second interrogation clock phase, which blocks the cores labeled A of the same stage. These cores A 1 to A 3, the read windings of which form the outputs a 1 to a 3 of the stages, so do not emit any read signal in the following. The same applies to cores G 1 to G 3, since they are blocked by read pulses from core Z.

The occurrence of a count has locking the core Z a result, the thus does not emit a blocking pulse at the cores G 1 and to the carry core Ü at its query. The core G 1 is therefore written by the read signal from the core Ni , the cores G 2 and G 3, on the other hand, are still blocked by the read signal from the core N 1 and N 2, respectively 1, the core N 1 is blocked so that it can no longer emit a read signal when it is queried. This has the consequence that, in its query no lock signal is delivered to the core A 1 and this is written by the central Einschreibimpuls and its query regarding the Ausgan _e a I emits an output signal, whereby the second counter state is set.

When a second counting pulse occurs, the blocking excitation supplied by core Z for cores Gl to G 3 is no longer available. However, only core G 2 from core Λ / 2 is written in, since core Ni likewise does not supply any blocking excitation to the write-in winding of core G 2. The cores G 1 and G 3, on the other hand, are not written in, the core G 1 not because the core N 1 does not provide any write regimg, the core G 3 not because the write excitation supplied by the core Λ / 3 is caused by the write excitation from the core N 2 supplied blocking excitation is compensated.

When it is interrogated, the core G 2 emits a read signal which, together with the central write-in pulse, writes the core N 1 of the previous stage against the blocking excitation supplied by the core A 1, so that the stage S1 returns to the binary value "0" during the subsequent interrogation cycle. corresponding state is set. The reading pulse of the core G '. on the other hand, blocks the core N 2, whereupon accordingly the processes of the core A 2 written in connection with the stage S1 and outputs an output signal when it is queried via the output a 2. This sets the third counter status

The occurrence of a third counting pulse and then the elimination of the blocking supplied by the core Z for the cores GI to G 3 results in the writing of the core G i . The core G 2 cannot be enrolled. Yes to him from the core N 1 only

a reverse excitation is delivered and the core G 3 can not be enrolled because the Einschreiberregung delivered by the core N 3 is compensated by the read signal of the core N. 1 The read signal emitted by the core G t during the subsequent interrogation blocks the core NI of this stage, so that it in turn no longer emits a read signal when it is interrogated and thus no longer prevents the core A 1 of the stage 51 from being written. Output signals are now emitted both via output a 1 and output a 2, with the result that the fourth counter status is set.

From the steps explained above, it follows that the cores labeled G are first written can become, if the levels before the level to which they belong, the set state, i. H. thus assume the state corresponding to the binary "!" and that on the one hand they set the own stage and on the other hand the deletion of the previous stage, i.e. d <* ren switchover to the dem according to the binary "O" state.

According to this principle is one of the occurrence of further counts of binary counter described up to an eighth count position, was, ere enrolled from which he by the read signal of the core Ü after the occurrence of the eighth count for the first time throughout the counting process, restored to the counter state 0 will.

In the exemplary embodiments of the circuit arrangement according to the invention described above the individual links of at least one of the variables to be processed were in the blocking direction influenced. The advantages that are caused by the query according to the invention occur naturally even if the variables to be processed are also the cores of the logic elements in the writing direction influence and when they coincide with a write-in pulse or with another in the write-in direction Acting variables cause the magnetic reversal of the core during the writing phase.

For this purpose 2 sheets of drawings

χ J

Claims (7)

Patent claims: 1. Circuit arrangement for processing binary variables consisting of logic elements of the same type consists, each using a magnetic core with a rectangular hysteresis loop are built up, if the link condition is met during a write-in process in one of its two retentive states: o and during the subsequent query process magnetized again by an interrogation pulse to the original other remanence state is, whereby it emits a read signal, and in the case of such read signals in the fulfillment of the Linking condition in each case other such linkage elements should be able to cooperate, d a through characterized in that interrogation pulses are supplied with such a short duration, that thereupon the magnetization in the saturation 2u The corresponding remanence state is initially not reached but is directly achieved through a range Auxiliary pulse following the interrogation pulse is set to such a small amplitude that the read pulses linked to this are not sufficient to remagnetize downstream cores (Figs. 4 to 7). 2. Circuit arrangement according to claim 1 for linking two binary variables in the form of an exclusive-OR function, characterized in that it consists of two logic elements whose magnetic cores (£ 1, £ 2) are queried simultaneously and their reading windings (n 12, η 22) both contribute to the delivery of the result variable (a) , and that both input variables (el, e2) each have separate windings (n 13, η 14, η 23, π 24) one magnetic core in the writing direction and the other magnetic core in the opposite direction magnetize, for which purpose they are fed in such a way that their effects on one and the same core are directed in the opposite direction (FIG. 4). 3. Circuit arrangement according to claim 2, characterized in that its output (a) supplies the write-in excitation for a third magnetic core (R) which is queried at a different clock phase and its read winding (nR 2) the input variables for one of its inputs (e 2), so that it works as a bistable multivibrator, the switching of which is effected by the switching variable supplied to the other input (e 1) (FIG. 5). 4. Circuit arrangement according to claim 3, characterized in that it is part of a chain of similar stages (52 to 54) forming a frequency divider, in which cores of the same order of successive stages are queried for the respective other clock phase and in each of which the read winding of the input winding of a stage load-bearing core (£ 2, £ 3, £ 4) is connected to the input winding of the next stage, and in those of these cores (£ 2, £ 4). which are queried for the first clock phase, also emits the output signal (F / 4, F / 16) of the stage, but with those of these cores (£ 3), it supplies the write excitation for an auxiliary core (H3) assigned to the same stage (53), which <> 5 is queried for the first clock phase and the output signal of the relevant stage is output via its read winding, and whose first frequency divider stage (52) is preceded by a pulse scaler stage (51) to suppress every second input pulse (Fig-6). 5. Circuit arrangement according to claim 4, characterized in that the pulse reduction stage (51) contains three magnetic cores (£ 1, Ai, Ll) , of which the first (El), to which the pulses (F) to be reduced, are supplied, and the second (A 1) to write the input signal for the first stage (52) of the chain, each subsequent core (Λ 1, L 1) magnetized in Einschreibrichtung, and the third (Ll), the read signal and the output signal (F / 2 ) of the stage, the previous second core (A 1) magnetized in the opposite direction and that the first (£ 1) and the third core (L 1) are queried for the first clock phase, the second core (A 1) on the other hand for the second clock phase is queried. 6. Circuit arrangement according to claim 4 or 5, characterized in that two compensation cores (Ml, M2) are additionally provided to which only query pulses are fed to different clock phases, and the compensation pulses via their reading windings at each query to such third cores (R2 , R 3, /? 4) of frequency divider stages (52, to 54) which are queried for the other clock phase that these nuclei are excited against the writing direction (FIG. 6). 7. Circuit arrangement according to claim 4 and 5 in the form of an η-stage binary counter, characterized in that the mutually identical stages each consist of three magnetic cores (G, A, N) of which the first two (G, A) form a first Clock phase and the third (N) are queried for a second clock phase, of which the first two (G, A) magnetize the third with their read signals in each case opposite to the writing direction and the third (A) with its reading signal the first (G) in the writing direction magnetized and of which the second (A) and third fN ^ are each written by a separate central write pulse source that the read signal of the third core (N) of the stages, the first cores (G) of all subsequent stages as well as a first clock phase interrogated Transfer magnet core (Ü) against the writing direction magnetized that the read signal of the first cores (G) of the stepper the first cores (G) of all the previous stepper in writing It is magnetized that the reading signal of the transfer magnet core (O) magnetizes all third K ^ rne (N) of the stages in the writing direction, and that the counting pulses eir for the second clock phase interrogated magnetic core (Z is used, which is used by the counting pulses against the one writing direction is magnetized and its reading signal all first cores (G) of the stages of the counter: as well as the transfer magnetic core (U) magnetized against the writing direction (F i g. 7).