DE112020001253T5 - Techniques for Training a Neural Network Using Transformations - Google Patents

Abstract

Apparatus, systems and techniques for performing neural network training using stacked transformed images. In at least one embodiment, a neural network is trained on stacked transformed images and a trained neural network is provided to be used for processing images from an unseen domain that is different from a source domain, with stacked transformed images according to transformation aspects in relation transformed to domain variations.

Description

PRIORITY CLAIM

This application claims priority from U.S. Provisional Application No. 62 / 819.432 entitled "BIG AUGMENTATION TRAINING FOR GENERALIZING MEDICAL IMAGE SEGMENTATION TO UNSEEN DOMAINS," filed March 15, 2019, the entire contents of which are hereby incorporated by reference.

TECHNICAL FIELD

In at least one embodiment, a processor comprises one or more arithmetic logic units (ALUs) in order to carry out training and / or inferencing using neural networks. In at least one embodiment, a multiplicity of one or more neural edge networks are trained on input images using batch transformations.

GENERAL STATE OF THE ART

Neural networks can be trained with ground truth data of features in training images to recognize features of images generated by images output by imaging devices such as medical imaging devices. It may be the case that images from different imaging devices have different properties, and images cannot be freely distributed for privacy or other reasons, which is the simple training of a neural network using images from a wide variety of imaging devices prevented. Processes for training neural networks while maintaining the locality of training data can be improved.

Figure list

• 1 illustrates an example of an image training system for training a neural network in accordance with at least one embodiment;
• 2 illustrates an example of a neural network processor using a trained neural network to determine segmentation of an image, according to at least one embodiment;
• 3 Fig. 10 illustrates an example of an aspect parameter table as might be used by an image transformer, in accordance with at least one embodiment;
• 4th FIG. 11 illustrates an example of an image transformer in accordance with at least one embodiment; FIG.
• 5 Figure 3 illustrates an example of a method of training a neural network to process unseen images by training on input images that are subjected to transformations, in accordance with at least one embodiment;
• 6th illustrates examples of images that could be processed by an image training system and images that could be processed by a neural network processor, in accordance with at least one embodiment;
• 7th illustrates examples of images that could be processed into transformed images by an image training system and unseen images that could be processed by a neural network processor trained on transformed images, in accordance with at least one embodiment;
• 8th illustrates examples of unseen images that could be processed by a neural network processor trained on transformed images compared to images processed by other methods, in accordance with at least one embodiment;
• 9A illustrates inference and / or training logic in accordance with at least one embodiment;
• 9B illustrates inference and / or training logic in accordance with at least one embodiment;
• 10 illustrates the training and use of a neural network in accordance with at least one embodiment;
• 11th illustrates an example data center system in accordance with at least one embodiment;
• 12A illustrates an example autonomous vehicle in accordance with at least one embodiment;
• 12B illustrates an example of camera locations and fields of view for the autonomous vehicle 12A according to at least one embodiment;
• 12C Figure 12 is a block diagram depicting an exemplary system architecture for the autonomous vehicle 12A illustrates, in accordance with at least one embodiment;
• 12D Figure 3 is a diagram showing a system for communication between cloud-based server (s) and the autonomous vehicle 12A illustrates, in accordance with at least one embodiment;
• 13th Figure 3 is a block diagram illustrating a computer system, in accordance with at least one embodiment;
• 14th Figure 3 is a block diagram illustrating a computer system, in accordance with at least one embodiment;
• 15th Fig. 10 illustrates a computer system in accordance with at least one embodiment;
• 16 Fig. 10 illustrates a computer system in accordance with at least one embodiment;
• 17A Fig. 10 illustrates a computer system in accordance with at least one embodiment;
• 17B Fig. 10 illustrates a computer system in accordance with at least one embodiment;
• 17C Fig. 10 illustrates a computer system in accordance with at least one embodiment;
• 17D Fig. 10 illustrates a computer system in accordance with at least one embodiment;
• 17E and 17F illustrate a shared programming model in accordance with at least one embodiment;
• 18th illustrates example integrated circuits and graphics processors associated therewith in accordance with at least one embodiment;
• 19A-19B 10 illustrates example integrated circuits and graphics processors associated therewith in accordance with at least one embodiment;
• 20A-20B illustrate additional example graphics processor logic in accordance with at least one embodiment;
• 21 Fig. 10 illustrates a computer system in accordance with at least one embodiment;
• 22A Figure 3 illustrates a parallel processor in accordance with at least one embodiment;
• 22B Fig. 10 illustrates a partition unit in accordance with at least one embodiment;
• 22C Fig. 10 illustrates a processing cluster in accordance with at least one embodiment;
• 22D Figure 3 illustrates a graphics multiprocessor in accordance with at least one embodiment;
• 23 Fig. 10 illustrates a multiple graphics processing unit (GPU) system in accordance with at least one embodiment;
• 24 Figure 3 illustrates a graphics processor in accordance with at least one embodiment;
• 25th Figure 3 is a block diagram illustrating a processor microarchitecture for a processor, in accordance with at least one embodiment;
• 26th illustrates a deep learning application processor in accordance with at least one embodiment;
• 27 Figure 3 is a block diagram illustrating an exemplary neuromorphic processor, in accordance with at least one embodiment;
• 28 illustrates at least portions of a graphics processor in accordance with one or more embodiments;
• 29 illustrates at least portions of a graphics processor in accordance with one or more embodiments;
• 30th illustrates at least portions of a graphics processor in accordance with one or more embodiments;
• 31 Figure 3 is a block diagram of a graphics processing engine of a graphics processor in accordance with at least one embodiment;
• 32 Figure 3 is a block diagram of at least portions of a graphics processor core in accordance with at least one embodiment;
• 33A-33B Figure 8 illustrates thread execution logic that includes an array of processing elements of a graphics processor core, in accordance with at least one embodiment;
• 34 Fig. 10 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;
• 35 Fig. 10 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;
• 36 Figure 3 illustrates a memory partition unit of a parallel processing unit (“PPU”) in accordance with at least one embodiment;
• 37 Figure 8 illustrates a streaming multiprocessor in accordance with at least one embodiment.
• 38 Figure 3 is an exemplary data flow diagram for an advanced computational pipeline in accordance with at least one embodiment;
• 39 Figure 3 is a system diagram for an exemplary system for training, adapting, instantiating, and deploying machine learning models in an advanced computational pipeline in accordance with at least one embodiment;
• 40 includes an exemplary illustration of an advanced computational pipeline 3910A for processing imaging data in accordance with at least one embodiment;
• 41A includes an exemplary data flow diagram of a virtual instrument supporting an ultrasound device, in accordance with at least one embodiment;
• 41B includes an exemplary data flow diagram of a virtual instrument supporting a CT scanner, in accordance with at least one embodiment;
• 42A illustrates a data flow diagram for a process of training a machine learning model in accordance with at least one embodiment; and
• 42B Figure 3 is an exemplary illustration of a client-server architecture for extending annotation tools with pre-trained annotation models in accordance with at least one embodiment.

DETAILED DESCRIPTION

1 Figure 11 illustrates an example of an image training system 100 , which can be used for training a neural network, according to at least one embodiment. In at least one embodiment, an image training system could train a neural network using images in an input sentence that are transformed in such ways that they might correspond to variations among images to be processed that are obtained independently of that input sentence. In at least one embodiment, an image set comprises medical images and a neural network processor is used to derive segmentation data for medical images. In at least one embodiment, images could include two-dimensional (2D) images that include arrays of pixel values, three-dimensional (3D) images that include arrays of voxel values, or other configurations. In at least one embodiment, segmentation data for an image could indicate boundaries of objects or regions in that image or estimated boundaries.

In at least one embodiment, an initial set of images 104 a transformer 102 provided. In at least one embodiment, the transformer could 102 an image transformer 112 and a segmentation transformer 114 include. In at least one embodiment, it could be the initial set of images 104 These are medical images that are available in a primary location, and they could be images that containment controls can exist so that the images cannot be freely distributed. In at least one embodiment, the initial image set includes 104 Ground truth data for segmentation for images in the initial image set 104 . In at least one embodiment could include images of the initial image set 104 can be obtained from medical imaging equipment, such as ultrasound, MRI, or other imaging equipment.

In at least one embodiment, the transformer receives 102 the initial set of images 104 and transformation aspect parameters from an aspect parameter store 106 . In at least one embodiment, the transformer transforms 102 Images of the initial image set 104 and corresponding segmentations, as described in more detail herein, to a training set 108 with transformed images and their corresponding segmentations, which may also be transformed. In at least one embodiment, images and segmentations of the training set are used 108 a cutter 120 provided that can crop images into partial volume images. In at least one embodiment, the cutter provides 120 resulting images and segmentations to a processor 122 of a neural network ready to create a neural network 126 to exercise and exercise using a loss assessor 124 to refine. In at least one embodiment, the loss assessor could 124 a dice loss function as a loss function in the loss assessor 124 use. In at least one embodiment, the dice loss function could equalize distributions of positive and negative voxels. In at least one embodiment, the processor gives 122 of the neural network a trained neural network 130 which may be in the form of a set of network layer weights or some other representation of a trained neural network.

In at least one embodiment, the operation of the transformer could be 102 the training set 108 deploy as a deep stacked data expansion image set. In at least one embodiment, a deeper stacked data expansion image set could be used to generalize deep learning based segmentation models for medical images to unseen domains. In at least one embodiment, transformed images could be in the training set 108 transformed according to variations between medical imaging modalities and providing domain generalization in medical imaging. In at least one embodiment, deep learning for the segmentation of medical images using a neural network processor trained with transformed images can provide automated detection of shapes in medical images such as 2D images or 3D volume images.

In at least one embodiment, the image training system can 100 Address generalization and accuracy of domain shifts across different imaging service providers, different imaging equipment providers, different imaging protocols, and varying patient populations as a few examples. In at least one embodiment, the image training system can 100 the trained neural network 130 train without requiring transfer learning or domain customization techniques. In at least one embodiment, the image training system can 100 provide a trained model that can function equally well across unseen domains without requiring further training. In at least one embodiment, the training set could 108 be a result of a series of batch transforms applied to images of the initial image set 104 is applied. In at least one embodiment, domain differences could be known, unknown, or partially known.

In at least one embodiment, the image training system simulates 100 Domain shifts using transformations on images based on aspects that may correspond to a domain shift or at least an expected difference between domains. In at least one embodiment, there could be a number of transformed images in the training set 108 greater than a number of images in the initial image set 104 being. In at least one embodiment, an initial image is transformed into a transformed image per aspect, transformed according to an aspect area and a probabilistically selected aspect transformation value is selected from such an aspect area. In at least one embodiment, information about domain shifts and / or transformations that are used to generate training images can be involved in training a neural network. In at least one embodiment, image processing of an unseen image by a trained neural network could include inputs corresponding to details of domain shifts and / or transformations used to generate training images.

2 illustrates an example implementation 200 a neural network that includes a processor 208 a neural network comprising a trained neural network 210 to determine a segmentation 212 of an image 204 used, according to at least one embodiment. In at least one embodiment, a medical device creates 202 Signals sent by an equipment processor 206 processed to the picture 204 to create. In at least one embodiment, can the trained neural network 210 using images of equipment in a location other than a location of the medical device 202 be trained. In at least one embodiment, the image is 204 not for training the trained neural network 210 used. In at least one embodiment, medical equipment could include T2 MRI devices, ultrasound devices, CT devices, OCT devices, or other devices, and it could vary scanning protocols such as tilt angle, repetition time, etc.

3 illustrates an example of an aspect parameter table 300 as might be used by an image transformer, according to at least one embodiment. In at least one embodiment, an image transformer could select from aspects listed in the aspect parameter table 300 are represented, possibly by random selection of values for aspects which are selected according to a probability distribution. In at least one embodiment, specific step sizes are used and thus a number of possible image variations are defined for an aspect. In at least one embodiment, continuous variations could be used for aspect parameter values. In at least one embodiment, a set of transformed images includes one image per aspect. In at least one embodiment, the transformer could 102 (please refer 1 ) for example for each of ten aspects in the aspect parameter table 300 and an input image output ten images, each transformed according to a single aspect and an aspect value, which could be a randomly selected value for such a single aspect. In at least one embodiment, input images could comprise a set of 10 to 32 volume images and their segmentations from a single source domain and be useful for segmenting images from unseen domains. In at least one embodiment, more than a hundred source images could be used.

In at least one embodiment, aspects could relate to specific types of aspects, such as a quality aspect, an appearance aspect, and a space configuration aspect. In at least one embodiment, image quality aspects could include sharpness, blurring, and noise levels that can correspond to variations in image quality in medical imaging. In at least one embodiment, blurring caused by movement artifacts in MRT / ultrasound can affect the interpretability of images and the computing power of segmentation processes. In at least one embodiment, Gaussian filtering can be used to blur an image to form a transformed image, where a size (possibly defined by a standard deviation of a Gaussian kernel) ranges between a minimum and a maximum. In at least one embodiment, a blur range can be from 0.25 to 1.5.

In at least one embodiment, unsharp masking could be used to compensate for blurring to simulate unseen, sharper images. In at least one embodiment, Equation 1 provides an example that a transformer could use as a filter to perform unsharp masking in reverse to blurring, where I _blurred and I _blurred by applying Gaussian filters to an image I and an image I _{blurred, respectively} Are images and α is a magnitude or strength of a sharpening effect. In at least one embodiment, as in 3 shown, α could be in a range between 10 and 30, with other ranges being possible. $${\mathrm{I.}}_{GescH\ddot{a}rft}={\mathrm{I.}}_{weicHGezeicHnet}+\left({\mathrm{I.}}_{weicHGezeicHnet}-{\mathrm{I.}}_{GefilterweicHGezeicHnet}\right)\times \alpha$$

In at least one embodiment, noise is added to a transformed image having a standard deviation (SD) of a Gaussian distribution in a range between 0.1 and 1.0. In at least one embodiment, image quality transformations are based on a Gaussian function / filter, a speckle function / filter, Poisson noise, a median value, a median filter, etc. In at least one embodiment, the transformer transforms 102 an input image with image quality transformations while leaving its annotation, Y _S , unchanged. In at least one embodiment, the annotations Y _S relate to segmentation or other features of an image.

In at least one embodiment, the transformer could 102 transform according to one type of aspect of the image's appearance, such as brightness, contrast, and intensity disturbance. In at least one embodiment, the transformer could 102 transform an image according to a brightness aspect value representing a shift in the intensity level, the magnitude being within a range. In at least one embodiment, an exemplary range is from -0.1 to +0.1.

In at least one embodiment, the transformer could 102 transform an image according to a contrast aspect value representing gamma correction, where a gamma value is within a range. In at least one embodiment, an exemplary range is from 0.5 to 1.0 and / or from 1.0 to 4.5, with a size = 1 leaving an original image unchanged and smaller / larger values making an image lighter / darker .

In at least one embodiment, the transformer could 102 transform an image according to disturbed image intensities by multiplying a scale factor for an input image and adding a shift factor, in each case within a few ranges. In at least one embodiment, each range is from -0.1 to +0.1. In at least one embodiment, the transformer transforms 102 an input image with types of transformation of the image's appearance while leaving its annotation, Y _S , unchanged.

In at least one embodiment, the transformer could 102 transform according to one type of aspect of the spatial configuration, such as rotation, scaling and deformation. In at least one embodiment, deformation could represent organ movement or abnormalities across patient populations.

In at least one embodiment, the transformer could 102 transform an image according to a rotation aspect value representing rotation within a range. In at least one embodiment, an exemplary range is -20 ° to + 20 ° and could take place in one, two or three dimensions.

In at least one embodiment, the transformer could 102 transform an image according to a scale aspect value representing a scale within a range. In at least one embodiment, an exemplary range is by a factor of 0.4 to 1.6 and could be in one, two, or three dimensions.

In at least one embodiment, the transformer could 102 transform an image according to a deformation including a standard deviation for the deformation and a deformation scale each varying within a range. In at least one embodiment, deformation could be done by scanning a grid with random offset vectors that are smoothed by a Gaussian smoothing filter. In at least one embodiment, an exemplary range for a standard deviation for the deformation is from 10 to 13 and an exemplary range for a deformation scale is from 0 to 1000. In at least one embodiment, the transformer transforms 102 when transforming an input image, an input image with a spatial configuration aspect and also transforms its annotations, Y _S , accordingly.

In at least one embodiment, the transformer could 102 allocate a capacity of a GPU memory to model training using partial volumes, as can be done in cases where an entire 3D volume does not fit into the limited memory of a GPU. In at least one embodiment, a CPU-based space transformation technique could be used in which the transformer 102 computes a 3D coordinate grid of a sub-volume to which a spatial configuration type aspect transformation, such as a combination of spatial configuration aspects including combining random 3D rotation, scaling, deforming and cropping operations, is applied, and then image interpolation is performed. In at least one embodiment, further acceleration is provided by omitting interpolation outside of a cuboid with a minimum surface area that contains a 3D coordinate grid. In at least one embodiment, an expansion of the spatial transformation can be carried out spontaneously during the training.

In at least one embodiment, using one or more transformations as described above, a neural network can be trained using images from a source domain and then used in an unseen domain. In at least one embodiment, a transformation can be treated as in Equation 2, and more generally, data, X _S , and annotations, Y _S , from a source domain can be used _{to train and effect a model, f S} , from such source domain that it performs well across unseen domains. In at least one embodiment, both the data X _S and the annotations Y _{S could be} 3D volumes and f _S could be a 3D segmentation mesh. In at least one embodiment, a transform could be a sequence of a number, n, of batch transforms, τ (.), Where each transform is an image processing function and each function is associated with a probability, p, to an associated one Function and a quantity, m, to apply such a function. In at least one embodiment, a training image and an associated annotation could be generated according to transformations shown in equation 1. $$\left({\widehat{x}}_s{\text{,}\widehat{\text{y}}}_s\right)={\tau }_{p_n\text{,}{m}_n}^n\left({\tau }_{p_{n-1}\text{,}{m}_{n-1}}^{n-1}\left(...{\tau }_{{\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="DE112020001253T5\_0005.png,DE112020001253T5\_0007.png"\; state="\{\{state\}\}">p</figure-callout>}}_1\text{,}{\mathrm{<figure-callout\; id="1"\; label="m"\; filenames="DE112020001253T5\_0005.png,DE112020001253T5\_0007.png"\; state="\{\{state\}\}">m</figure-callout>}}_1}^1\left(x_s\text{,}{y}_s\right)\right)\right)$$

In at least one embodiment, transformations could be applied in each minibatch during training to account for a contribution from domain-specific shifts in medical images. In at least one embodiment, transformations in Equation 2 could be performed in varying orders.

In at least one embodiment, a 3D segmentation network can use deep 2D and / or 3D segmentation networks by conveying deep features learned from large-scale 2D images into a 3D encoder-decoder network. In at least one embodiment, inputs for training can be partial volumes that are cut from entire volumes, with outputs being corresponding partial volumes of segmentation masks with 1-channel annotations. In at least one embodiment, partial volumes can be tailored randomly to increase the variation of training data and evenly distributed between a foreground and a background. In at least one embodiment, dice loss is used as a loss function and a sliding window can be used, with overlap being applied to an entire 3D volume to produce a final 3D segmentation.

4th illustrates an example of an image transformer 406 according to at least one embodiment. In at least one embodiment, the image transformer acquires 406 a picture 402 and its corresponding segmentation together with aspect parameters from an aspect parameter store 404 . In at least one embodiment, the image transformer turns 406 Selects one or more aspect transformations and selects values for the aspect transformation, possibly using a random number generator (RNG) 408 to select values. In at least one embodiment, aspect transformation blocks can include a Gaussian soft focus, an unsharp masker, a noise injector, a brightness adjuster, a contrast adjuster, an intensity interferer, a rotator / scaler and / or a deformer. In at least one embodiment, the image transformer is there 406 then transformed images 420 with their corresponding segmentations.

5 illustrates an example of a procedure 500 for training a neural network to process unseen images by training on input images that are subjected to transformations, according to at least one embodiment. In at least one embodiment, a transformer in step 501 Source images from one place and by step 502 a segmentation of these source images. In at least one embodiment, a transformer determines in step 503 what transformation aspect parameters to use to generate an output image, and what aspect parameter values, how many images to generate, etc. In at least one embodiment, a transformer cuts in step 504 randomly to partial volumes and he generates in step 505 accordingly transformed training images and their corresponding segmentations.

In at least one embodiment, step 506 trains a neural network on transformed training images and their corresponding segmentations. In at least one embodiment, step 507 If this neural network is trained, a training system will supply this trained neural network to additional locations for use in the image processing of unseen images from unseen domains. In at least one embodiment, a transformer determines if this neural network is not sufficiently trained at step 510 additional transformations and moves at step 504 away.

In at least one embodiment, the method could 500 implemented using NVIDIA's Medical Imaging Transfer Learning Toolkit. In at least one embodiment, data in a source domain could be set to a fixed resolution of 1.0 mm × 1.0 mm × 1.0 mm and image intensities, I, normalized to [0.1] by (I-min) / (max- min), be scanned again, where min = 0, max = 2048 for MRIs and min = 0, max = 255 for ultrasound. In at least one embodiment, a probability to be applied to each transformation is set to 0.5. In at least one embodiment, image intensities could not be renormalized after the transformation. In at least one embodiment, cut sub-volumes could be 96 × 96 × 32 (w × h × d) for task 1 (see 8th ) and 96 × 96 × 96 for task 2 and task 3. In at least one embodiment, ADAM could be used to optimize a network with an initial learning rate of 0.0001. In at least one embodiment, Task 1 and Task 2 could be trained on four GPUs of a DGX cluster from NVIDIA and Task 3 could be trained on a Titan XP GPU from NVIDIA, all using SGD and with a mini-batch size of four regions of Regions of interest (ROIs) per GPU.

In at least one embodiment, a model could 300 Training epochs can be trained three times on a source domain and a model with the best computing power on a validation set of this source domain could be selected to be applied to unseen domains. In at least one embodiment, in the model inference, test data could be resampled to 1.0 mm × 1.0 mm × 1.0 mm and normalized to [0, 1] and a sliding window increment could be (w-16) × (h -16) × (d-16). In at least one embodiment, a 2-class model could be trained first and then its output could be combined with into a 1-class model.

6th Figure 11 illustrates examples of images that could be processed by an image training system and images that could be processed by a neural network processor, in accordance with at least one embodiment. In at least one embodiment, segmentation of a medical image in a source domain could be applied to images in an unseen domain, such as a medical imaging modality that is different from a medical imaging modality of the source domain. In at least one embodiment, imaging differences caused by domain shift of MRI are the quality and appearance of the image, with sharpening being most significant, followed by contrast, brightness, and intensity perturbation. In at least one embodiment, examples show an MRI of the prostate 6th that contrast and sharpening are the main differences between the Unseen A and Unseen B images compared to a source image. In at least one embodiment, spatial transformations can help to transform MRIs of the heart, wherein the shape, size and orientation of a heart can be very different, as shown in an image set of a right ventricle 6th and MRI of the heart 7th .

In at least one embodiment, imaging differences caused by domain shifting from different ultrasound providers can be larger, where 3-D scaling is significant, followed by brightness, blurring, and contrast. In at least one embodiment, a bottom line of illustrates 6th Examples. In at least one embodiment, spatial transformations can contribute significantly to a segmentation task of an ultrasound of the heart, partly because a heart is a deformable object and different angles between an ultrasound probe and a heart can lead to images with different degrees of rotation.

7th Figure 10 illustrates examples of images that could be processed into transformed images by an image training system and unseen images that could be processed by a neural network processor trained on transformed images, in accordance with at least one embodiment.

8th Figure 11 illustrates examples of unseen images that could be processed by a neural network processor trained on transformed images compared to images processed by other methods, in accordance with at least one embodiment. In at least one embodiment, an exemplary task for training a neural network can consist of training on 3D data sets of an MRT of the prostate and to test on other 3D data sets of an MRT of the prostate as unseen domains. In at least one embodiment, another exemplary task can be used to train a neural network on 3D data sets from an MRT of the heart. In at least one embodiment, yet another exemplary task for training a neural network can consist of training on a 3D ultrasound data set, with source data originating from one provider and unseen data originating from other providers. In at least one embodiment, a neural network can use an unseen image to determine boundaries of an object, such as 3D objects shown in various images of the following 8th are illustrated.

INFERENCE AND TRAINING LOGIC

9A illustrates inference and / or training logic 915 used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are below in connection with 9A and / or 9B provided.

In at least one embodiment, the inference and / or training logic 915 without restriction code and / or data memory 901 to store forward and / or output weighting and / or input / output data and / or other parameters to configure neurons or layers of a neural network that is trained and / or used for inference in aspects of one or more embodiments . In at least one embodiment, the training logic 915 Code and / or data storage 901 or be coupled to, to store graph code or other software to control the timing and / or order in which weighting and / or other parameter information is to be loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic and logical units (ALUs)). In at least one embodiment, code, such as graph code, weighting, or other parameter information, loads into processor ALUs based on a neural network architecture to which such code corresponds. In at least one embodiment, the code and / or data memory stores 901 Weighting parameters and / or input / output data of each layer of a neural network that is trained or used in connection with one or more embodiments, during the forward propagation of input / output data and / or weighting parameters during training and / or inferencing using aspects one or more embodiments. In at least one embodiment, any portion of the code and / or data memory 901 be contained in other on-chip or off-chip data storage, including the L1, L2, or L3 cache or system memory of a processor.

In at least one embodiment, any portion of the code and / or data memory 901 internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or code and / or data memory 901 Cache memory, dynamic randomly addressable memory ("DRAM"), static randomly addressable memory ("SRAM"), non-volatile memory (e.g. flash memory) or other memory. In at least one embodiment, a choice can be made as to whether the code and / or code and / or data memory 901 for example internal or external to a processor, or comprising DRAM, SRAM, Flash or some other type of memory, of the available on-chip or off-chip memory, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inferencing and / or training a neural network, or a combination of these factors.

In at least one embodiment, the inference and / or training logic 915 a code and / or data memory without restriction 905 to store backward and / or output weighting and / or input / output data corresponding to neurons or layers of a neural network that is trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the code and / or data memory stores 905 Weighting parameters and / or input / output data of each layer of a neural network that is trained or used in connection with one or more embodiments, during the backward propagation of input / output data and / or weighting parameters during training and / or inferencing using aspects one or more embodiments. In at least one embodiment, the training logic 915 Code and / or data storage 905 or be coupled to, to store graph code or other software to control the timing and / or order in which weighting and / or other parameter information is to be loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic and logical units (ALUs)).

In at least one embodiment, code such as graph code causes weighting or other parameter information to be loaded into processor ALUs based on a neural network architecture to which such code conforms. In at least one embodiment, any portion of the code and / or data memory 905 be contained in other on-chip or off-chip data storage, including the L1, L2, or L3 cache or system memory of a processor. In at least one embodiment, any portion of the code and / or data memory 905 internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data memory 905 Cache memory, DRAM, SRAM, non-volatile memory (e.g. flash memory) or other memory. In at least one embodiment, a choice can be made as to whether the code and / or data memory 905 for example is internal or external to a processor or includes DRAM, SRAM, Flash memory or some other type of memory, of the available on-chip or off-chip memory, the latency requirements of the training and / or inference functions that are performed, the batch size of the data used in inferencing and / or training a neural network, or a combination of these factors.

In at least one embodiment, the code and / or data memory 901 and the code and / or data memory 905 be separate storage structures. In at least one embodiment, the code and / or data memory 901 and the code and / or data memory 905 be a combined storage structure. In at least one embodiment, the code and / or data memory 901 and the code and / or data memory 905 partially combined and partially separate. In at least one embodiment, any portion of the code and / or data memory 901 and the code and / or data memory 905 be contained in other on-chip or off-chip data storage, including the L1, L2, or L3 cache or system memory of a processor.

In at least one embodiment, the inference and / or training logic 915 without restriction one or more arithmetic-logical unit (s) ("ALU (s)") 910 including integer and / or floating point units to perform logical and / or mathematical operations based at least in part on or indicated by training and / or inference code (e.g. graph code), a result of which are activations (e.g. B. Output values from layers or neurons within a neural network) can be stored in an activation memory 920 are stored and the functions of input / output and / or weighting parameter data are stored in the code and / or data memory 901 and / or the code and / or data memory 905 are stored. In at least one embodiment, the activation memory 920 stored activations generated according to linear algebraic and / or matrix-based mathematics, which are generated by the ALU (s) 910 is performed in response to the execution of instructions or other code, in the code and / or data memory 905 and / or the data memory 901 stored weighting values are used as operands together with other values such as distortion values, gradient information, moment values or other parameters or hyperparameters, any or all of which are in the code and / or data memory 905 or the code and / or data memory 901 or another on-chip or off-chip memory.

In at least one embodiment, the ALU (s) are 910 contained within one or more processors or other hardware logic devices or circuits, while in another embodiment the ALU (s) 910 external to a processor or other hardware logic device or circuit using them (e.g., a coprocessor). In at least one embodiment, the ALUs 910 be contained within the execution units of a processor or otherwise within a bank of ALUs, to which the execution units of a processor can access, either within the same processor or distributed among different processors of different types (e.g. central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, the code and / or data memory 901 , the code and / or data memory 905 and the activation memory 920 share a processor or other hardware logic device or circuit, while in another embodiment they may be in different processors or other hardware logic devices or circuit or in a combination of the same and different processors or other hardware logic devices or circuit . In at least one embodiment, any portion of the activation memory 920 be contained in other on-chip or off-chip data storage, including the L1, L2, or L3 cache or system memory of a processor. Furthermore, the inference and / or training code can be stored with other code that can be accessed by a processor or other hardware logic or circuit and that is generated using the retrieval, decoding, planning, execution, elimination and / or other logic circuits of a processor is called up and / or processed.

In at least one embodiment, the activation memory 920 Cache memory, DRAM, SRAM, non-volatile memory (e.g. flash memory) or other memory. In at least one embodiment, the activation memory 920 wholly or partially located inside or outside of one or more processors or other logical circuits. In at least one embodiment, a choice can be made as to whether the activation memory 920 for example internal or external to a processor, or comprises DRAM, SRAM, Flash memory or some other type of memory, of the available on-chip or off-chip memory, the latency requirements of the training and / or inference functions being performed, the batch size the data used in inferencing and / or training a neural network, or a combination of these factors.

In at least one embodiment, the in 9A illustrated inference and / or training logic 915 used in conjunction with an application-specific integrated circuit ("ASIC"), such as a TensorFlow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore ™ or a Nervana® processor (e.g. "Lake Crest") from Intel Corp. In at least one embodiment, the in 9A illustrated inference and / or training logic 915 used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as field programmable gate arrays (“FPGAs”).

9B illustrates inference and / or training logic 915 according to at least one embodiment. In at least one embodiment, the inference and / or training logic 915 include, without limitation, hardware logic in which computing resources are dedicated or otherwise used solely in conjunction with weighting values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, the in 9B illustrated inference and / or training logic 915 can be used in conjunction with an application-specific integrated circuit (ASIC), such as the TensorFlow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore ™ or a processor of the Nervana® type (e.g. "Lake Crest") from Intel Corp. In at least one embodiment, the in 9B illustrated inference and / or training logic 915 used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as field programmable gate arrays (FPGAs). In at least one embodiment, the includes inference and / or training logic 915 the code and / or data memory without restriction 901 and the code and / or data memory 905 that can be used to store code (e.g., graph code), weighting values, and / or other information including distortion values, gradient information, instantaneous values, and / or other parameter or hyper-parameter information. In at least one embodiment described in 9B illustrated is each of the code and / or data memory 901 and the code and / or data memory 905 with a dedicated computing resource, such as the computing hardware 902 or the computing hardware 906 , associated. In at least one embodiment, each of the computing hardware includes 902 and the computing hardware 906 one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on information that is in the code and / or data memory 901 or the code and / or data memory 905 are stored, the result of which in the activation memory 920 is saved.

In at least one embodiment, each corresponds to the code and / or data stores 901 and 905 and the corresponding computing hardware 902 or. 906 different layers of a neural network, so that the resulting activation of a memory / arithmetic pair 901 / 902 of the code and / or data memory 901 and the computing hardware 902 as input for a next memory / arithmetic pair 905 / 906 of the code and / or data memory 905 and the computing hardware 906 is provided to reflect a conceptual organization of a neural network. In at least one embodiment, each of the memory / compute pairs 901 / 902 and 905 / 906 correspond to more than one layer of a neural network. In at least one embodiment, additional memory / computing pairs (not shown) can follow or parallel to the memory / computing pairs 901 / 902 and 905 / 906 in inference and / or training logic 915 be included.

TRAINING AND USE OF NEURAL NETWORKS

10 illustrates the training and use of a deep neural network in accordance with at least one embodiment. In at least one embodiment, the untrained neural network 1006 using a training data set 1002 trained. In at least one embodiment, the training framework is 1004 a PyTorch frame, whereas the training frame 1004 in other embodiments is a TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deepleaming4j or other training framework. In at least one embodiment, the training frame trains 1004 an untrained neural network 1006 and enables it to be trained using the processing resources described herein to be a trained neural network 1008 to create. In at least one embodiment, the weights can be chosen randomly or through pre-training using a deep belief network. In at least one embodiment, training can be performed in either a supervised, partially supervised, or unsupervised manner.

In at least one embodiment, the untrained neural network 1006 trained using supervised learning, the training data set 1002 includes an input paired with a desired output for an input, or wherein the training data set 1002 includes an input having a known output and an output of the neural network 1006 is assessed manually. In at least one embodiment, the untrained neural network 1006 trained in a monitored manner and it processes inputs from the training data set 1002 and compares the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then caused by the untrained neural network 1006 backpropagated. In at least one embodiment, the training framework provides 1004 Weights that the untrained neural network 1006 steer. In at least one embodiment, the training framework includes 1004 Tools to monitor how well the untrained neural network is doing 1006 converges to a model such as the trained neural network 1008 which is suitable for generating correct answers, such as in the result 1014 based on input data such as a new record 1012 based. In at least one embodiment, the training frame trains 1004 the untrained neural network 1006 repeatedly while adjusting weights to provide an output of the untrained neural network 1006 using a loss function and an adjustment algorithm such as stochastic gradient descent. In at least one embodiment, the training frame trains 1004 the untrained neural network 1006 until the untrained neural network 1006 achieved a desired accuracy. In at least one embodiment, the trained neural network 1008 then used to implement any number of machine learning operations.

In at least one embodiment, the untrained neural network 1006 trained using unsupervised learning, the untrained neural network 1006 tries to train itself using unlabeled data. In at least one embodiment, the training data set contains 1002 for unsupervised learning input data without associated output data or “ground truth” data. In at least one embodiment, the untrained neural network 1006 Groupings within the training data set 1002 learn and determine how individual entries work with the untrained data set 1002 related. In at least one embodiment, unsupervised training can be used to create a self-organizing map in the trained neural network 1008 capable of performing operations that reduce the dimensionality of the new data set 1012 are useful. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which is the identification of data points in the new data set 1012 allows that of normal patterns of the new record 1012 differ.

In at least one embodiment, semi-supervised learning can be used, which is a technique in which the training data set 1002 contains a mixture of labeled and unlabeled data. In at least one embodiment, the training frame 1004 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 1008 to refer to the new record 1012 adapt without forgetting the knowledge that the trained neural network 1008 was taught during initial training.

DATA CENTER

11th illustrates an exemplary data center 1100 , in which at least one embodiment can be used. In at least one embodiment, the data center includes 1100 a data center infrastructure layer 1110 , a frame layer 1120 , a software layer 1130 and an application layer 1140 .

In at least one embodiment, as in 11th shown can be the data center infrastructure layer 1110 a resource orchestrator 1112 , grouped computing resources 1114 and node computing resources ("node CRs") 1116 (1) -1116 (N) where "N" represents a positive integer (which may be a different integer "N" than used in other figures). In at least one embodiment, the node CRs 1116 (1) -1116 (N) any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), storage devices 1118 (1) -1118 (N) (e.g. dynamic read-only memory, solid-state memory or hard disk drives), devices for network input / output ("NW-I / O"), network switches, virtual machines ("VMs"), Include, but are not limited to, power modules and cooling modules, etc. In at least one Embodiment may be one or more node CRs from the node CRs 1116 (1) -1116 (N) be a server that has one or more of the computing resources mentioned above.

In at least one embodiment, the grouped computing resources 1114 include separate groupings of Node CRs housed within one or more racks (not shown) or multiple racks housed in data centers in different geographic locations (also not shown). Separate groupings of node CRs within the grouped computing resources 1114 may, in at least one embodiment, include grouped computing, network, memory, or data storage resources that may be configured or assigned to support one or more workloads. In at least one embodiment, multiple node CRs including CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks can also contain any number of power modules, cooling modules and network switches in any combination.

In at least one embodiment, the resource orchestrator 1112 one or more node CRs 1116 (1) -1116 (N) and / or grouped computing resources 1114 configure or otherwise control. In at least one embodiment, the resource orchestrator 1112 a software design infrastructure ("SDI") management entity for the data center 1100 include. In at least one embodiment, the resource orchestrator 912 Include hardware, software, or a combination thereof.

In at least one embodiment, as in 11th shown includes the frame layer 1120 a task planner 1122 , a configuration manager 1124 , a resource manager 1126 and a distributed file system 1128 . In at least one embodiment, the frame layer 1120 a framework for supporting software 1132 the software layer 1130 and / or one or more application (s) 1142 the application layer 1140 include. In at least one embodiment, the software 1132 or the application (s) 1142 include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, it can be the frame layer 1120 Be a kind of free and open source software web application framework such as Apache Spark ™ (hereafter “Spark”), which is the distributed file system 1128 for processing large amounts of data (e.g. "Big Data"), without being limited to it. In at least one embodiment, the task scheduler can 1132 Include a Spark driver to facilitate the planning of workloads that move through different tiers of the data center 1100 get supported. In at least one embodiment, the configuration manager 1124 be able to do this with different layers, such as the software layer 1130 and the frame layer 1120 , including Spark and the distributed file system 1128 , to be configured to support the processing of large amounts of data. In at least one embodiment, the resource manager 1126 be able to manage clustered or grouped computing resources that support the distributed file system 1128 and the scheduler 1122 mapped or assigned. In at least one embodiment, clustered or grouped computing resources can be grouped computing resources 1114 in the data center infrastructure layer 1110 include. In at least one embodiment, the resource manager can 1126 with the resource orchestrator 1112 coordinate to manage these mapped or assigned computing resources.

In at least one embodiment, the software layer 1130 included software 1132 Include software that runs through at least sections of the Node CRs 1116 (1) -1116 (N) , the grouped computing resources 1114 and / or the distributed file system 1128 the frame layer 1120 is used. One or more types of software, in at least one embodiment, may include, but are not limited to, software for browsing Internet web pages, software for scanning emails for viruses, database software, and software for streaming video content.

In at least one embodiment, those in the application layer 1140 contained application (s) 1142 involve one or more types of applications, at least through portions of the node CRs 1116 (1) -1116 (N) , the grouped computing resources 1114 and / or the distributed file system 1128 the frame layer 1120 be used. One or more types of applications may, in at least one embodiment, include any number of a genomics application, a cognitive computation application, and a machine learning application, including training or inference software, machine learning framework software (e.g. . PyTorch, TensorFlow, Caffe etc.) or other machine learning applications used in conjunction with, but not limited to, one or more embodiments.

In at least one embodiment, any of the configuration manager 1124 , the resource manager 1126 and the resource orchestrator 1112 implement any number and type of self-modifying acts based on any amount and type of data collected in any technically feasible manner. In at least one embodiment, self-modifying actions can allow a data center operator of the data center 1100 Relieve the burden of making potentially poor configuration decisions and avoiding potentially underutilized and / or malfunctioning sections of a data center.

In at least one embodiment, the data center 1100 Include tools, services, software, or other resources to train one or more machine learning models or to predict or inference information using one or more machine learning models in accordance with one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weighting parameters according to a neural network architecture using software and computing resources described above with respect to the data center 1100 are described. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to compute information using the information provided above with respect to the data center 1100 inferring or predicting the resources described using weighting parameters calculated by one or more training techniques described herein.

In at least one embodiment, the data center can use CPUs, application specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inferencing using the resources described above. In addition, one or more of the software and / or hardware resources described above can be configured as a service to enable users to train or perform inferencing information, such as image recognition, speech recognition or other artificial intelligence services.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the inference and / or training logic 915 in the system 11th can be used for inference or prediction operations at least in part on the basis of weighting parameters calculated using training operations for neural networks, functions and / or architectures of neural networks or use cases described herein for neural networks.

AUTONOMOUS VEHICLE

12A illustrates an exemplary autonomous vehicle 1200 according to at least one embodiment. In at least one embodiment, the autonomous vehicle can 1200 (here alternatively as “vehicle 1200 “Referred to) be, without limitation, a passenger vehicle, such as a car, truck, bus and / or other type of vehicle that carries one or more passengers. In at least one embodiment, the vehicle can 1200 be a semi-trailer truck used to move cargo. In at least one embodiment, the vehicle can 1200 be an airplane, robotic vehicle, or other type of vehicle.

Autonomous vehicles can be described in terms of automation levels supported by the National Highway Traffic Safety Administration ("NHTSA"), a division of the US Department of Transportation, and the Society of Automotive Engineers ("SAE") "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g. B. Standard No. J3016-201806, published June 15, 2018, Standard No. J3016-201609, published September 30, 2016, and previous and future versions of this standard) are defined. In one or more embodiments, the vehicle may 1200 be able to a functionality according to one or more of level 1 up to and including level 5 of the levels for autonomous driving. For example, in at least one embodiment, the vehicle 1200 Depending on the embodiment, a conditional automation (level 3), a high level of automation (level 4) and / or a complete automation (level 5) be able.

In at least one embodiment, the vehicle can 1200 include, without limitation, components such as a chassis, vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle. In at least one embodiment, the vehicle can 1200 a drive system without restriction 1250 include, such as an internal combustion engine, a hybrid electric engine, an all-electric motor, and / or some other type of propulsion system. In at least one embodiment, the drive system 1250 with a drive train of the vehicle 1200 be connected, which may include a transmission without restriction to drive the vehicle 1200 to enable. In at least one embodiment, the drive system 1250 in response to receiving signals from a throttle / accelerator pedal (s) 1252 being controlled.

In at least one embodiment, a steering system 1254 , which may include a steering wheel, without limitation, used to drive the vehicle 1200 to steer (e.g., along a desired path or route) when the propulsion system 1250 is in operation (e.g. when the vehicle 1200 is in motion). In at least one embodiment, the steering system 1254 Signals from steering actuator (s) 1256 receive. In at least one embodiment, a steering wheel can be optional for the functionality of full automation (level 5). In at least one embodiment, a brake sensor system 1246 used to apply vehicle brakes in response to receiving signals from brake actuator (s) 1248 and / or operate brake sensors.

In at least one embodiment, control (s) 1236 that can have one or more systems on a chip (system on chips - "SoCs") (in 12A not shown) and / or graphics processing unit (s) (“GPU (s)”) may include one / one or more components and / or systems of the vehicle 1200 Signals (e.g. representative of commands) ready. For example, in at least one embodiment, the controller (s) 1236 Signals for operating vehicle brakes via the brake actuator (s) 1248 to operate the steering system 1254 via the steering actuator (s) 1256 , for operating the drive system 1250 via the throttle / accelerator pedal (s) 1252 send. In at least one embodiment, the controller (s) 1236 include one or more on-board (e.g., integrated) computing devices that process sensor signals and issue operating commands (e.g., signals representing commands) to enable autonomous driving and / or a human driver driving the vehicle 1200 to support. In at least one embodiment, the controller (s) 1236 a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functionality (e.g. machine vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergencies and / or other controls. In at least one embodiment, a single controller can handle two or more of the above functionalities, two or more controllers can handle a single functionality, and / or any combination thereof.

In at least one embodiment, the controller (s) 1236 Signals for controlling one / one or more components and / or systems of the vehicle 1200 ready in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data can be received, for example and without limitation, from sensor (s) 1258 of global navigation satellite systems ("GNSS") (e.g. sensor (s) of the global positioning system), RADAR sensor (s) 1260 , Ultrasonic sensor (s) 1262 , LIDAR sensor (s) 1264 , Sensor (s) 1266 an inertial measurement unit ("IMU") (e.g. accelerometer (s), gyroscope (s), a magnetic compass or magnetic compasses, magnetometer (s) etc.), microphone (s) 1296 , Stereo camera (s) 1268 , Foresight camera (s) 1270 (e.g. fisheye cameras), infrared camera (s) 1272 , All-round camera (s) 1274 (e.g. 360-degree cameras), long-range cameras (in 12A not shown), medium-range camera (s) (in 12A not shown), speed sensor (s) 1244 (e.g. to measure the speed of the vehicle 1200 ), Vibration sensor (s) 1242 , Steering sensor (s) 1240 , Brake sensor (s) (e.g. as part of the brake sensor system 1246 ) and / or other types of sensors.

In at least one embodiment, one or more of the controller (s) 1236 Inputs (e.g. represented by input data) from an instrument cluster 1232 of the vehicle 1200 receive and outputs (e.g. represented by output data, display data, etc.) via a display 1234 a human-machine interface ("HMI"), an acoustic alarm, a loudspeaker and / or via other components of the vehicle 1200 provide. In at least one embodiment, outputs can include information such as vehicle speed, engine speed, time, map data (e.g. a high-resolution map (in 12A not shown), location data (e.g. the location of the vehicle 1200 such as on a map), direction, location of other vehicles (e.g. an occupancy grid), information about objects and the status of objects, as provided by the control (s) 1236 perceived, etc. include. To the For example, in at least one embodiment, the HMI display 1234 Display information about the presence of one or more objects (e.g. a street sign, a warning sign, a switching traffic light, etc.) and / or information about driving maneuvers that the vehicle has performed, is currently performing or is about to perform (e.g. now Change lanes, the exit in two miles 34B take etc.).

In at least one embodiment, the vehicle includes 1200 also a network interface 1224 , the wireless antenna 1226 and / or modem (s) to communicate over one or more networks. For example, in at least one embodiment, the network interface 1224 be able to do so via networks with Long-Term Evolution ("LTE"), broadband code division multiple access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communication ( "GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") etc. to communicate. In at least one embodiment, the wireless antenna (s) can 1226 also communication between objects in the vicinity (e.g. vehicles, mobile devices, etc.) using local area network (s) such as Bluetooth, Bluetooth Low Energy (“LE”), Z-Wave, ZigBee, etc., and / or wide-area network (s) with low power consumption (low power wide-area networks - “LPWANs”), such as LoRaWAN protocols, SigFox protocols, etc.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the inference and / or training logic 915 in the system 12A can be used for inference or prediction operations at least in part on the basis of weighting parameters calculated using training operations for neural networks, functions and / or architectures of neural networks or use cases described herein for neural networks.

12B illustrates an example of camera locations and fields of view for the autonomous vehicle 1200 out 12A according to at least one embodiment. In at least one embodiment, the cameras and the respective fields of view represent an exemplary embodiment and they are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras can be included and / or the cameras can be at different locations on the vehicle 1200 condition.

In at least one embodiment, camera types for cameras may include, but are not limited to, digital cameras for use with components and / or systems of the vehicle 1200 are designed. In at least one embodiment, the camera (s) can be operated with the automotive safety integrity level (“ASIL”) B and / or with a different ASIL. In at least one embodiment, depending on the embodiment, the camera types can be capable of any image recording rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc. In at least one embodiment, cameras may be able to use rolling shutters, global shutters, some other type of shutter, or a combination thereof. In at least one embodiment, the color filter array may be a Red-Clear-Clear-Clear (“RCCC”) color filter array, a Red-Clear-Clear-Blue (“RCCB”) color filter array, a Red-Blue-Green-Clear- ("RBGC") color filter array, a Foveon X3 color filter array, a Bayer sensor ("RGGB") color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, clear pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter array, can be used in an effort to increase photosensitivity.

In at least one embodiment, one or more of the camera (s) can be used to perform functions of the advanced driver assistance systems (“ADAS”) (e.g. as part of a redundant or fail-safe configuration). For example, in at least one embodiment, a multifunction mono camera can be installed to provide functions that include lane departure warning, traffic sign assist and intelligent headlight control. In at least one embodiment, one or more of the camera (s) (e.g. all cameras) can simultaneously record and provide image data (e.g. video).

In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom designed (three-dimensional (“3D”) printed) assembly, to isolate stray light and reflections from the interior of the vehicle 1200 (e.g. reflections from the dashboard that are reflected in the windshield mirrors) cut out the Can affect the image data acquisition capabilities of the cameras. With reference to side mirror mounting assemblies, in at least one embodiment, the side mirror assemblies can be custom 3D printed so that a camera mounting plate conforms to a shape of a side mirror. In at least one embodiment, the camera (s) can be integrated in side mirrors. In at least one embodiment, in the case of side view cameras, the camera (s) can also be integrated within four columns at each corner of a cabin.

In at least one embodiment, cameras can have a field of view that covers sections of an area in front of the vehicle 1200 includes (e.g., forward-facing cameras) that use all-round visibility to help identify forward-facing paths and obstacles, and one or more controls 1236 and / or to help control SoCs provide information that is critical to generating an occupancy grid and / or determining preferred vehicle paths. In at least one embodiment, front-facing cameras can be used to perform many similar ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, forward facing cameras can also be used for ADAS functions and systems including, without limitation, lane departure warnings ("LDW"), autonomous cruise control ("ACC"), and / or other functions such as traffic sign recognition.

In at least one embodiment, a variety of cameras may be used in a front-facing configuration, including, for example, a monocular camera platform that includes a complementary metal oxide semiconductor (CMOS) color image sensor. In at least one embodiment, a foresight camera 1270 can be used to perceive objects that come into view from a periphery (e.g. pedestrians, crossing traffic or bicycles). Although in 12B just a foresight camera 1270 As illustrated, in other embodiments, any number (including zero) of foresight cameras on the vehicle 1200 to be available. In at least one embodiment, any number of long-range camera (s) 1298 (e.g. a pair of far-sighted stereo cameras) can be used for depth-based object detection, in particular for objects for which a neural network has not yet been trained. In at least one embodiment, the long-range camera (s) can 1298 can also be used for object detection and classification as well as basic object tracking.

In at least one embodiment, any number of the stereo camera (s) 1268 also be included in a forward-facing configuration. In at least one embodiment, one or more of the stereo camera (s) 1268 Include an integrated control unit that includes a scalable processing unit that can provide programmable logic (“FPGA”) and a multi-core microprocessor with an integrated interface for a controller area network (“CAN”) or Ethernet on a single chip. In at least one embodiment, such a unit can be used to create a 3D map of the surroundings of the vehicle 1200 including a distance estimate for all points in an image. In at least one embodiment, one or more of the stereo camera (s) 1268 Contain, without restriction, compact stereo vision sensor (s) that can contain, without restriction, two camera lenses (one each left and right) and an image processing chip that can determine the distance from the vehicle 1200 measure to a target object and use the generated information (e.g. metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo camera (s) 1268 can be used in addition or as an alternative to those described herein.

In at least one embodiment, cameras can have a field of view that covers sections of the surroundings to the side of the vehicle 1200 includes (e.g., side view cameras) that provide all-round visibility, thereby providing information that is used to create and update an occupancy grid and generate side impact collision warnings. For example, in at least one embodiment, the all-round camera (s) 1274 (e.g. four all-round cameras, as in 12B illustrated) on the vehicle 1200 be positioned. In at least one embodiment, the all-round camera (s) 1274 include, without limitation, any number and combination of foresight cameras, fisheye camera (s), 360-degree camera (s) and / or similar cameras. For example, in at least one embodiment, there may be four fish-eye cameras on a front, a rear, and sides of the vehicle 1200 be positioned. In at least one embodiment, the vehicle can 1200 three all-round camera (s) 1274 (e.g. left, right and rear) and use one or more other camera (s) (e.g. a front-facing camera) as a fourth all-round view camera.

In at least one embodiment, cameras can have a field of view that covers sections of an area behind the vehicle 1200 contains (e.g. reversing cameras), can be used for parking assistance, for all-round visibility, for rear collision warnings and for creating and updating an occupancy grid. In at least one embodiment, a wide variety of cameras may be used, including, but not limited to, cameras that are also suitable as the front-facing camera (s) (e.g., long-range cameras) 1298 and / or medium-range camera (s) 1276 , Stereo camera (s) 1268 , Infrared camera (s) 1272 etc.) as described herein.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the inference and / or training logic 915 in the system 12B can be used for inference or prediction operations at least in part on the basis of weighting parameters calculated using training operations for neural networks, functions and / or architectures of neural networks or use cases for neural networks described herein.

12C Figure 12 is a block diagram illustrating an exemplary system architecture for the autonomous vehicle 1200 out 12A illustrates, according to at least one embodiment. In at least one embodiment, any of the components, features, and systems of the vehicle are 1200 in 12C than over a bus 1202 connected illustrated. In at least one embodiment, the bus 1202 contain without restriction a CAN data interface (herein alternatively referred to as “CAN bus”). In at least one embodiment, a CAN can be a network within the vehicle 1200 to assist in controlling various features and functions of the vehicle 1200 is used, such as applying brakes, accelerating, braking, steering, wipers, etc. In at least one embodiment, the bus may 1202 be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g. a CAN ID). In at least one embodiment, the bus 1202 can be read to determine steering wheel angle, speed over ground, engine revolutions per minute ("RPMs"), button positions and / or other vehicle status indicators. In at least one embodiment, the bus 1202 be a CAN bus that conforms to ASIL B.

In at least one embodiment, FlexRay and / or Ethernet protocols can also be used in addition to or as an alternative to CAN. In at least one embodiment, there can be any number of buses that make up the bus 1202 which may include, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses can be used to perform different functions and / or used for redundancy. For example, a first bus can be used for the functionality of the collision avoidance and a second bus can be used for the actuation control. In at least one embodiment, each bus on the bus can 1202 with any components of the vehicle 1200 communicate and two or more buses of the bus 1202 can communicate with corresponding components. In at least one embodiment, any number of system (s) on chip ("SoC (s)") 1204 (such as the SoC 1204 (A) and SoC 1204 (B) , each of the control (s) 1236 and / or each computer within the vehicle has access to the same input data (e.g. inputs from sensors of the vehicle 1200 ) and be connected to a common bus such as the CAN bus.

In at least one embodiment, the vehicle can 1200 one or more control (s) 1236 include, such as those referred to herein with respect to 12A are described. In at least one embodiment, the controller (s) 1236 used for a variety of functions. In at least one embodiment, the controller (s) 1236 to any of various other components and systems of the vehicle 1200 be coupled and to control the vehicle 1200 , the artificial intelligence of the vehicle 1200 , the infotainment for the vehicle 1200 and / or other functions.

In at least one embodiment, the vehicle can 1200 any number of SoCs 1204 include. In at least one embodiment, each of the SoCs 1204 without restriction central processing units ("CPU (s)") 1206 , Graphics processing units ("GPU (s)") 1208 , Processor (s) 1210 , Cache (s) 1212 , one or more accelerators 1214 , one or more data stores 1216 and / or include other components and features not illustrated. In at least one embodiment, the SoC (s) can 1204 to control the vehicle 1200 in a variety of platforms and systems be used. For example, in at least one embodiment, the SoC (s) 1204 in a system (e.g. system of the vehicle 1200 ) with a high definition ("HD") card 1222 combined, the map updates and / or updates via the network interface 1224 from one or more servers (in 12C not shown).

In at least one embodiment, the CPU (s) can 1206 Include a CPU cluster or CPU complex (alternatively referred to herein as "CCPLEX"). In at least one embodiment, the CPU (s) can 1206 contain multiple cores and / or level two ("L2") caches. For example, in at least one embodiment, the CPU (s) 1206 Include eight cores in a coherent multiprocessor configuration. In at least one embodiment, the CPU (s) can 1206 Include four dual core clusters, each cluster having a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, the CPU (s) can 1206 (e.g. CCPLEX) must be configured to support simultaneous cluster operations so that any combination of clusters of the CPU (s) 1206 can be active at any given time.

In at least one embodiment, one or more of the CPU (s) 1206 Implement power management capabilities that include, without limitation, one or more of the following features: individual blocks of hardware can be automatically clocked when idle to conserve dynamic power; Each core clock can be controlled if such a core is not actively executing any instructions due to the execution of Wait-for-Interrupt (“WFI”) / Wait-for-Event (“WFE”) instructions; each core can be independently power driven; each core cluster can be independently clock controlled if all cores are clock controlled or power controlled; and / or each core cluster can be independently power driven if all cores are power driven. In at least one embodiment, the CPU (s) can 1206 further implement an advanced algorithm for managing performance states, in which permitted performance states and expected wake-up times are specified and the hardware / microcode determines which best performance state to enter for a core, a cluster and a CCPLEX. In at least one embodiment, the processing cores may support simplified power state entry sequences in software, offloading work on microcode.

In at least one embodiment, the GPU (s) can 1208 Include an integrated GPU (alternatively referred to herein as "iGPU"). In at least one embodiment, the GPU (s) can 1208 be programmable and efficient for parallel workloads. In at least one embodiment, the GPU (s) can 1208 use an extended tensor instruction set. In at least one embodiment, the GPU (s) can 1208 include one or more streaming microprocessors, each streaming microprocessor may include a level one ("L1") cache (e.g., an L1 cache with a storage capacity of at least 96 KB), and two or more streaming -Microprocessors can share an L2 cache (e.g. an L2 cache with a storage capacity of 512 KB). In at least one embodiment, the GPU (s) can 1208 Include at least eight streaming microprocessors. In at least one embodiment, the GPU (s) can 1208 Use computational application programming interface (s) - API (s). In at least one embodiment, the GPU (s) can 1208 use one or more parallel computing platforms and / or programming models (e.g. the CUDA model from NVIDIA).

In at least one embodiment, one or more of the GPU (s) 1208 be performance-optimized for the best computing power in automotive and embedded use cases. For example, in one embodiment the GPU (s) could 1208 be made on a Fin Field Effect Transistor ("FinFET") circuit. In at least one embodiment, each streaming microprocessor may include a number of mixed precision processing cores partitioned into multiple blocks. For example and without limitation, 64 PF32 cores and 32 PF64 cores could be partitioned into four processing blocks. In at least one embodiment, each processing block could have 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two NVIDIA mixed precision tensor cores for deep leaming matrix arithmetic, a level zero ("LO") instruction cache , a warp planner, an allocation unit and / or a 64 KB register bank. In at least one embodiment, streaming microprocessors may include independent parallel integer and floating point data paths to enable efficient execution of workloads with a mixture of computation and addressing computations. In at least one embodiment, streaming microprocessors can include independent thread scheduling capability to allow for finer-grain synchronization and cooperation between parallel threads. In at least one embodiment, streaming microprocessors may incorporate a combined L1 data cache and shared memory unit to improve computational performance while simplifying programming.

In at least one embodiment, one or more of the GPU (s) 1208 may include high bandwidth memory ("HBM") and / or a 16 GB HBM2 memory subsystem to provide, in some examples, a peak memory bandwidth of approximately 900 GB / second. In at least one embodiment, a synchronous graphics random access memory (“SGRAM”) can be used in addition or as an alternative to HBM memory, such as a synchronous random access memory of the graphics double data rate type five (graphics double data rate type five - "GDDR5").

In at least one embodiment, the GPU (s) can 1208 include uniform storage technology. In at least one embodiment, address translation services ("ATS") support may be used to enable the GPU (s) to 1208 directly on side tables of CPU (s) 1206 access. In at least one embodiment, if the memory management unit ("MMU") of a GPU of the GPU (s) 1208 suffers an error, an address translation request to the CPU (s) 1206 be transmitted. As a reaction to this, 2 CPUs of the CPU (s) 1206 in at least one embodiment, search for a virtual-to-physical mapping for an address in their side tables and send the translation back to the GPU (s) 1208 transfer. In at least one embodiment, the uniform memory technology can use a single uniform virtual address space for memory for both the CPU (s) 1206 as well as the GPU (s) 1208 enable programming of the GPU (s) 1208 and porting applications to the GPU (s) 1208 be simplified.

In at least one embodiment, the GPU (s) can 1208 contain any number of access counters that indicate the frequency of access by the GPU (s) 1208 on other processors' memory. In at least one embodiment, the hit counter (s) can help ensure that pages of memory are moved to physical memory of a processor that accesses pages most frequently, thereby improving efficiency for areas of memory shared by multiple processors.

In at least one embodiment, one or more of the SoC (s) 1204 any number of cache (s) 1212 including those described herein. In at least one embodiment, the cache (s) could 1212 For example, a level three ("L3") cache contain both the CPU (s) 1206 as well as the GPU (s) 1208 is available (e.g. with the CPU (s) 1206 and GPU (s) 1208 connected is). In at least one embodiment, the cache (s) can 1212 include a write-back cache that can keep track of the states of lines, such as by using a cache coherency protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, an L3 cache may include 4MB of memory or more, depending on the embodiment, although smaller cache sizes may be used.

In at least one embodiment, one or more of the SoC (s) 1204 one or more accelerators 1214 (e.g. hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoC (s) can 1204 include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB SRAM) can enable a hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, a hardware acceleration cluster can be used to power the GPU (s) 1208 to add and some tasks of the GPU (s) 1208 outsource (e.g. more cycles of the GPU (s) 1208 free to perform other tasks). In at least one embodiment, the accelerator (s) could 1214 for targeted workloads (e.g. perception, convolutional neural networks ("CNNs"), recurrent neural networks (recurrent neural networks - "RNNs"), etc.) that are stable enough to be suitable for acceleration to be. In at least one embodiment, a CNN may include region-based or regional convolutional neural networks (“RCNNs”) and fast RCNNs (such as used for object detection) or some other type of CNN.

In at least one embodiment, the accelerator (s) can 1214 (e.g. hardware acceleration clusters) contain one or more deep learning accelerators ("DLA"). DLA (s), in at least one embodiment, may include, without limitation, one or more tensor processing units ("TPUs") that may be configured to perform an additional ten trillion operations per second for deep learning applications and inference provide. In at least one embodiment, the TPUs can be accelerators that perform of image processing functions (e.g. for CNNs, RCNNs, etc.) are configured and optimized. In at least one embodiment, the DLA (s) can be further optimized for a specific set of types of neural networks and floating point operations, as well as for inferencing. In at least one embodiment, the design of the DLA (s) can provide more computing power per millimeter than a typical general-purpose GPU, and it typically far exceeds the computing power of a CPU. In at least one embodiment, the TPU (s) can perform multiple functions including a single instance convolution function that supports, for example, INT8, INT16, and FP16 data types for both features and weights, as well as post processor functions. In at least one embodiment, the DLA (s) can quickly and efficiently perform neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, and without limitation: using a CNN for the identification and detection of objects of data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for the detection and identification and detection of emergency vehicles using data from microphones; a CNN for facial recognition and identification of vehicle owners using data from camera sensors; and / or a CNN for security and / or security related events.

In at least one embodiment, the DLA (s) can perform any function of the GPU (s) 1208 and by using an inference accelerator a designer can for example either DLA (s) or GPU (s) 1208 aim for any function. For example, in at least one embodiment, a designer can focus on processing CNNs and floating point operations on the DLA (s) and other functions on the GPU (s) 1208 and / or accelerator (s) 1214 left.

In at least one embodiment, the accelerator (s) can 1214 a programmable vision accelerator ("PVA"), which may alternatively be referred to herein as a machine vision accelerator. In at least one embodiment, the PVA can accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 1238 , autonomous driving, augmented reality (“AR”) applications and / or virtual reality (“VR”) applications can be designed and configured. In at least one embodiment, the PVA can provide a balance between computing power and flexibility. In at least one embodiment, each PVA may, for example and without limitation, include any number of Reduced Instruction Set Computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of Include vector processors.

In at least one embodiment, RISC cores can interact with image sensors (e.g., image sensors from any of the cameras described herein), image signal processor (s), and so on. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, RISC cores can use any of a number of protocols, depending on the embodiment. In at least one embodiment, RISC cores can run a real-time operating system (“RTOS”). In at least one embodiment, RISC cores may be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC cores could include an instruction cache and / or tightly coupled RAM.

In at least one embodiment, DMA can enable the components of the PVA to independently of the CPU (s) 1206 access system memory. In at least one embodiment, DMA can support any number of features used to provide optimization of a PVA, including but not limited to support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, DMA can support up to six or more dimensions of addressing, which can include, without limitation, block width, block height, block depth, horizontal block grading, vertical block grading, and / or depth grading.

In at least one embodiment, vector processors can be programmable processors that can be configured to efficiently and flexibly perform programming for machine vision algorithms and to provide signal processing capabilities. In at least one embodiment, a PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, a PVA core can include a processor subsystem, DMA engine (s) (e.g., two DMA engines), and / or other peripheral devices. In at least one embodiment, a vector processing subsystem may operate as the primary processing engine of a PVA and a Vector processing unit ("VPU"), an instruction cache and / or vector memory (z. B. "VMEM"). In at least one embodiment, the VPU core may include a digital signal processor, such as a digital single instruction multiple data (“SIMD”) very long instruction word (“VLIW”) signal processor. In at least one embodiment, a combination of SIMD and VLIW can increase throughput and speed.

In at least one embodiment, each of the vector processors may include an instruction cache and be coupled to dedicated memory. Therefore, in at least one embodiment, each of the vector processors can be configured to operate independently of other vector processors. In at least one embodiment, vector processors included in a particular PVA can be configured to employ data parallelism. For example, in at least one embodiment, a plurality of vector processors contained in a single PVA may execute a common machine vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors contained in a specific PVA can simultaneously execute different machine vision algorithms on an image or also execute different algorithms on sequential images or sections of an image. In at least one embodiment, any number of PVAs can be included in a hardware acceleration cluster and any number of vector processors can be included in each PVA, among other things. In at least one embodiment, the PVA can contain additional memory for error correction code (“ECC”) in order to increase the overall system security.

In at least one embodiment, the accelerator (s) can 1214 Include an on-chip machine vision network and static random-access memory ("SRAM") to provide high bandwidth, low latency SRAM for the accelerator (s) 1214 provide. In at least one embodiment, on-chip memory can include at least 4 MB SRAM, which includes, for example and without limitation, eight field-configurable memory blocks that can be accessed by both a PVA and a DLA. In at least one embodiment, each pair of memory blocks can contain an interface for an advanced peripheral bus (“APB”), a configuration circuit, a controller and a multiplexer. Any type of memory can be used in at least one embodiment. In at least one embodiment, a PVA and a DLA can access storage through a backbone that provides high-speed access to storage for a PVA and a DLA. In at least one embodiment, a backbone may include an on-chip machine vision network that interconnects a PVA and a DLA with memory (e.g., using an APB).

In at least one embodiment, an on-chip machine vision network may include an interface that, prior to transmitting any control signal / address / data, determines that both a PVA and a DLA are providing operational and valid signals. In at least one embodiment, an interface can provide separate phases and separate channels for transmitting control signals / addresses / data as well as burst-like communication for continuous data transmission. In at least one embodiment, an interface with the standards International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 conform, although other standards and protocols may be used.

In at least one embodiment, one or more of the SoC (s) 1204 include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator can be used to quickly and efficiently determine positions and dimensions of objects (e.g., within a world model), to generate real-time visualization simulations, for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulating SONAR systems, for general wave propagation simulation, for comparison with LIDAR data for the purpose of localization and / or for other functions and / or for other uses.

In at least one embodiment, the accelerator (s) can 1214 have a wide range of uses for autonomous driving. In at least one embodiment, a PVA can be used for important processing stages in ADAS and in autonomous vehicles. In at least one embodiment, a PVA's capabilities fit well with algorithmic domains that require predictable, low-performance, low-latency processing. In other words, a PVA shows good computing power for semi-dense or dense regular calculations, even on small data sets that could require predictable runtimes with low latency and low performance. In at least one embodiment, such as in the vehicle 1200 , the PVAs could be designed in such a way that they execute classic machine vision algorithms, as they can be efficient in object detection and in operating on integer mathematics.

For example, in accordance with at least one embodiment of the technology, a PVA is used to perform stereo machine vision. In at least one embodiment, although not intended to be limiting, a semi-global matching based algorithm may be used in some examples. In at least one embodiment, applications for autonomous driving at level 3-5 use spontaneous motion estimation / stereo matching (e.g. structure of motion, pedestrian detection, lane detection, etc.). In at least one embodiment, a PVA can perform stereo machine vision functions on inputs from two monocular cameras.

In at least one embodiment, a PVA can be used to perform dense optical flow. For example, in at least one embodiment, a PVA could process raw RADAR data (e.g., using a fast 4D Fourier transform) to provide processed RADAR data. In at least one embodiment, a PVA is used for runtime in-depth processing, for example by processing raw runtime data to provide processed runtime data.

In at least one embodiment, a DLA can be used to implement any type of network to improve control and driving safety, including, for example and without limitation, a neural network that provides a measure of confidence for each object detection. In at least one embodiment, the confidence can be represented or interpreted as a probability or as the provision of a relative “weighting” of each detection in comparison to other detections. In at least one embodiment, a confidence measure enables a system to make further decisions about which detections should be considered true positive detections and not false positive detections. In at least one embodiment, a system can set a threshold for confidence and only consider detections that exceed the threshold as true positive detections. In one embodiment in which an automatic emergency braking (“AEB”) system is used, false positive detections would result in the vehicle automatically performing emergency braking, which of course is undesirable. In at least one embodiment, high-confidence detections can be viewed as triggers for AEB. In at least one embodiment, a DLA can execute a neural network for regression of the confidence value. In at least one embodiment, the neural network may use as its input at least a subset of parameters, such as the dimensions of the bounding box, the ground plane estimate obtained (e.g. from another subsystem), the output of IMU sensor (s) 1266 that comes with the orientation of the vehicle 1200 correlates, the distance, the 3D location estimates of the object, which are provided by the neural network and / or other sensors (e.g. LIDAR sensor (s) 1264 or RADAR sensor (s) 1260 ) as well as others.

In at least one embodiment, one or more of the SoC (s) 1204 one or more data stores 1216 (e.g. memory). In at least one embodiment, the data memory (s) can be 1216 to chip internal memory of the SoC (s) 1204 act that can store neural networks on the GPU (s) 1208 and / or a DLA. In at least one embodiment, the capacity of the data storage device (s) 1216 be large enough to store multiple instances of neural networks for redundancy and security. In at least one embodiment, the data store (s) can 1216 Include L2 or L3 cache (s).

In at least one embodiment, one or more of the SoC (s) 1204 any number of processor (s) 1210 (e.g. embedded processors). In at least one embodiment, the processor (s) can 1210 include a booting and power management processor that may be a dedicated processor and subsystem to handle booting power and management functions and related security enforcement. In at least one embodiment, the booting and power management processor may be part of a booting sequence of the SoC (s) 1204 and provide runtime performance management services. In at least one embodiment, a booting power and management processor can program clock and voltage, assist with transitions of the system to a low power state, manage thermal and temperature sensors of the SoC (s) 1204 and / or management of performance states of the SoC (s) 1204 provide. In at least one embodiment, each temperature sensor can be implemented as a ring oscillator, the output frequency of which is proportional to the temperature, and the SoC (s) 1204 can use ring oscillators to measure temperatures from CPU (s) 1206 , GPU (s) 1208 and / or accelerator (s) 1214 to detect. If it is determined that Temperatures exceed a threshold, in at least one embodiment, a booting and power management processor can then enter a temperature fault routine and the SoC (s) 1204 put in a state with lower power and / or the vehicle 1200 put into a mode of driving to a safe stop (e.g. the vehicle 1200 to a secure hold).

In at least one embodiment, the processor (s) can 1210 also include a set of embedded processors that can serve as an audio processing engine, which can be an audio subsystem that allows full hardware support for multi-channel audio across multiple interfaces and a wide and flexible range of audio I / O interfaces . In at least one embodiment, an audio processing engine is a dedicated processor core having a digital signal processor with dedicated RAM.

In at least one embodiment, the processor (s) can 1210 also include an always-on processor engine that can provide necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, without limitation, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controls), various I / O control peripherals, and routing logic.

In at least one embodiment, the processor (s) can 1210 further include a security cluster engine which includes, without limitation, a dedicated processor subsystem for handling security management for automotive applications. In at least one embodiment, a security cluster engine may include, without limitation, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timer, interrupt controller, etc.), and / or routing logic. In a security mode, in at least one embodiment, two or more cores can operate in lockstep mode and function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, the processor (s) can 1210 further include a real-time camera engine which may include, without limitation, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, the processor (s) can 1210 further include a high dynamic range signal processor which may include, without limitation, an image signal processor which is a hardware engine that is part of a camera processing pipeline.

In at least one embodiment, the processor (s) can 1210 a video image composer, which may be a processing block (e.g. implemented on a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image for the window of a playback program. In at least one embodiment, a video composer can apply lens distortion correction to the far-sighted camera (s) 1270 , All-round camera (s) 1274 and / or in-cabin surveillance camera sensor (s). In at least one embodiment, the in-cabin surveillance camera sensor (s) are preferably monitored by a neural network that is located on another instance of the SoC 1204 runs and is configured to detect events in the cabin and react accordingly. In at least one embodiment, an in-cab system can perform lip reading to activate the cellular service and make a call, dictate e-mails, change a destination of the vehicle, activate or change or change an infotainment system of the vehicle and its settings without restriction provide voice-activated surfing on the Internet. In at least one embodiment, certain functions are available to a driver when a vehicle is being operated in an autonomous mode and are otherwise deactivated.

In at least one embodiment, a video compositor may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment in which motion occurs in a video, the noise suppression weights the spatial information accordingly by reducing the weighting of the information provided by adjacent individual images. In at least one embodiment where an image or a portion of an image does not include motion, the temporal noise reduction performed by the video image composer may use information from a previous image to reduce noise in a current image.

In at least one embodiment, a video image composer can also be configured in such a way that it carries out stereo rectification on the input stereo lens single images. In at least one embodiment, a video compositor may also be responsible for the user interface composition be used when a desktop of the operating system is in use and the GPU (s) 1208 are not required to continuously render new surfaces. When the GPU (s) 1208 are switched on and are actively performing 3D rendering, in at least one embodiment a video image composer can be used to control the GPU (s) 1208 offload to improve computing power and responsiveness.

In at least one embodiment, one or more SoCs of the SoC (s) 1204 also include a serial mobile industry processor interface ("MIPI") camera interface for receiving video and input from cameras, a high speed interface, and / or a video input block that can be used for a camera and related pixel input functions. In at least one embodiment, one or more of the SoC (s) 1204 further include input / output controller (s) that can be controlled by software and used to receive I / O signals that are not assigned to a particular role.

In at least one embodiment, one or more SoCs of the SoC (s) 1204 also include a wide variety of peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders ("Codecs"), power management, and / or other devices. In at least one embodiment, the SoC (s) can 1204 used to collect data from cameras (e.g. connected via gigabit multimedia serial link and Ethernet channels), sensors (e.g. LIDAR sensor (s) 1264 , RADAR sensor (s) 1260 etc., which may be connected via Ethernet channels), data from the bus 1202 (e.g. the speed of the vehicle 1200 Steering wheel position etc.), data from GNSS sensor (s) 1258 (e.g. connected via an Ethernet bus or a CAN bus) etc. In at least one embodiment, one or more SoCs of the SoC (s) 1204 also contain dedicated mass storage controllers with high computing power, which can contain their own DMA engines and which can be used to control CPU (s) 1206 Relieve routine data management tasks.

In at least one embodiment, the SoC (s) can 1204 be an end-to-end platform with a flexible architecture that spans automation levels 3-5 and thus provides a comprehensive functional security architecture that uses machine vision and ADAS techniques for diversity and redundancy and uses them efficiently and a platform for one provides flexible, reliable stacks of driving software along with deep learning tools. In at least one embodiment, the SoC (s) can 1204 be faster, more reliable and even more energy-efficient and space-efficient than conventional systems. For example, in at least one embodiment, the accelerator (s) 1214 when using the CPU (s) 1206 , GPU (s) 1208 and data memory (s) 1216 are combined to provide a fast, efficient platform for autonomous vehicles of levels 3-5.

In at least one embodiment, machine vision algorithms can be executed on CPUs that can be configured using a high level programming language such as C to execute a wide variety of processing algorithms over a wide variety of visual data. However, in at least one embodiment, the CPUs are often unable to meet the computing power requirements of many machine vision applications, such as execution time and power consumption. In at least one embodiment, many CPUs are incapable of executing in real time complex object detection algorithms used in in-vehicle ADAS applications and in practical Level 3-5 autonomous vehicles.

The embodiments described herein make it possible for several neural networks to be carried out simultaneously and / or sequentially and for the results to be combined with one another in order to enable autonomous driving functionality of levels 3-5. For example, in at least one embodiment, a CNN running on a DLA or a discrete GPU (e.g., GPU (s) 1220 ), contain text and word recognition that enable the reading and understanding of traffic signs, including signs for which a neural network has not been specially trained. In at least one embodiment, a DLA may further include a neural network capable of identifying, interpreting, and providing a semantic understanding of a character and communicating that semantic understanding to path planning modules running on a CPU complex.

In at least one embodiment, several neural networks can be carried out simultaneously, as for driving at level 3, 4 or 5. In at least one embodiment, for example, a warning sign with the words "Caution: Flashing lights indicate icing “can be interpreted together with an electric light by several neural networks independently or together. In at least one embodiment, such a warning sign can itself be identified as a traffic sign by a first neural network used (e.g. a neural network that has been trained) and a text “Flashing lights indicate icing” can be identified by a second neural network used be interpreted that a path planning software of the vehicle (which is preferably executed on a CPU complex) informs that if flashing lights are detected, there is icing. In at least one embodiment, a flashing light can be identified by operating a third deployed neural network over a number of individual images, which informs path planning software of the vehicle of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, such as within a DLA and / or on GPU (s) 1208 .

In at least one embodiment, a facial recognition and vehicle owner identification CNN may use data from camera sensors to determine the presence of an authorized driver and / or owner of the vehicle 1200 to identify. In at least one embodiment, an always-on sensor processing engine can be used to unlock a vehicle when an owner approaches a driver's door and turns on lights, and to deactivate such vehicle in a security mode when an owner exits such vehicle. In this way the SoC (s) 1204 Security against theft and / or carjacking ready.

In at least one embodiment, a CNN can use microphones to detect and identify emergency vehicles 1296 used to detect and identify sirens from emergency vehicles. In at least one embodiment, the SoC (s) use 1204 a CNN for classifying ambient and city sounds as well as classifying visual data. In at least one embodiment, a CNN running on a DLA is trained to identify a relative approach speed of an emergency vehicle (e.g., by using a Doppler effect). In at least one embodiment, a CNN may also be trained to identify emergency vehicles that are specific to a local area in which a vehicle is operating, as indicated by the GNSS sensor (s). 1258 identified. In at least one embodiment, when a CNN is operating in Europe, it tries to detect European sirens, and in North America, a CNN tries to identify only North American sirens. In at least one embodiment, as soon as an emergency vehicle is detected, a control program can be used to use the ultrasonic sensor (s) 1262 execute an emergency vehicle safety routine to slow a vehicle, pull to a roadside, park a vehicle, and / or idle a vehicle until the emergency vehicles have passed.

In at least one embodiment, the vehicle can 1200 CPU (s) 1218 (e.g. discrete CPU (s) or dCPU (s)) that are connected to the SoC (s) via high-speed interconnection (e.g. PCIe) 1204 can be coupled. In at least one embodiment, the CPU (s) can 1218 for example include an X86 processor. The CPU (s) 1218 can be used to perform any of a variety of functions including, for example, relaying potentially inconsistent results between ADAS sensors and SoC (s) 1204 and / or monitoring the status and condition of the controller (s) 1236 and / or an infotainment system on a chip ("Infotainment SoC") 1230 .

In at least one embodiment, the vehicle can 1200 GPU (s) 1220 (e.g. discrete GPU (s) or dGPU (s)) connected to the SoC (s) via high-speed interconnection (e.g. NVLINK channel from NVIDIA) 1204 can be coupled. In at least one embodiment, the GPU (s) can 1220 provide additional functionality for artificial intelligence, such as by running redundant and / or different neural networks, and they can be used to train and / or update neural networks based at least in part on inputs (e.g. sensor data) from sensors of a vehicle 1200 be used.

In at least one embodiment, the vehicle can 1200 also the network interface 1224 include, without limitation, wireless antenna (s) 1226 may include (e.g. one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, the network interface 1224 can be used to provide wireless connectivity to internet cloud services (e.g. to server (s) and / or other network devices), to other vehicles and / or to computing devices (e.g. to passenger client devices) enable. In at least one embodiment, a direct link between the vehicle can be used to communicate with other vehicles 120 and another vehicle and / or an indirect link (e.g. via networks and via the Internet) can be established. In at least one embodiment, direct links can be provided using a vehicle-to-vehicle communication link. In at least one embodiment, a Vehicle-to-vehicle communication link the vehicle 1200 Information about vehicles in the vicinity of the vehicle 1200 provide (e.g. vehicles in front of, next to and / or behind the vehicle 1200 ). In at least one embodiment, such aforementioned functionality can be part of a cooperative adaptive speed control functionality of the vehicle 1200 being.

In at least one embodiment, the network interface 1224 contain a SoC, which provides a modulation and demodulation functionality and it to the controller (s) 1236 enables communication via wireless networks. In at least one embodiment, the network interface 1224 Include a high frequency front end for upconverting from baseband to high frequency and down converting from high frequency to baseband. In at least one embodiment, frequency conversions can be performed in any technically feasible manner. Frequency conversions could be performed, for example, by well known processes and / or using overlay processes. In at least one embodiment, the high-frequency front-end functionality can be provided by a separate chip. In at least one embodiment, the network interfaces can include wireless functionality for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN and / or other wireless protocols.

In at least one embodiment, the vehicle can 1200 furthermore one or more data memories 1228 include the chip-external (e.g. outside of the SoC (s) 1204 lying) memory. In at least one embodiment, the data store (s) can 1228 include, without limitation, one or more storage elements including RAM, SRAM, dynamic random-access memory ("DRAM"), video random-access memory ("VRAM"), flash memory, hard drives, and / or other components and / or devices that can store at least one bit of data.

In at least one embodiment, the vehicle can 1200 also GNSS sensor (s) 1258 (e.g. GPS and / or assisted GPS sensors) to aid with functions for mapping, perception, generation of the occupancy grid and / or path planning. In at least one embodiment, any number of GNSS sensor (s) 1258 including, for example and without limitation, a GPS using a USB connector with an ethernet-to-serial bridge (e.g., RS-232 bridge).

In at least one embodiment, the vehicle can 1200 furthermore RADAR sensor (s) 1260 include. In at least one embodiment, the RADAR sensor (s) can 1260 through the vehicle 1200 can be used for vehicle detection with a long range, even in darkness and / or bad weather conditions. In at least one embodiment, the RADAR functional safety level can be ASIL B. In at least one embodiment, the RADAR sensor (s) can 1260 a CAN bus and / or the bus 1202 (e.g. to transmit the data generated by the RADAR sensor (s) 1260 generated data) to control and access object tracking data, with Ethernet channels being accessed to access raw data in some examples. In at least one embodiment, a wide variety of RADAR sensor types can be used. For example and without limitation, the RADAR sensor (s) 1260 be suitable for use as a front, rear and side RADAR. In at least one embodiment, one or more sensors are the RADAR sensor (s) 1260 a pulse Doppler RADAR sensor.

In at least one embodiment, the RADAR sensor (s) can 1260 include different configurations such as long range and narrow field of view, short range and wide field of view, short range side coverage, etc. In at least one embodiment, the long range RADAR can be used for adaptive cruise control functionality. In at least one embodiment, long range RADAR systems can provide a wide field of view realized by two or more independent scans, such as within a range of 250 meters. In at least one embodiment, the RADAR sensor (s) can 1260 help distinguish between static and moving objects, and through the ADAS system 1238 can be used for emergency braking and forward collision warning. In at least one embodiment, the sensor (s) can 1260 included in a long-range RADAR system, including, without limitation, a monostatic multimodal RADAR with several (e.g. six or more) fixed RADAR antennas and a high-speed CAN and FlexRay interface. In at least one embodiment with six antennas, four central antennas can generate a focused beam pattern that is designed to encompass the surroundings of the vehicle 1200 at higher Record speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, two further antennas can expand the field of view, which makes it possible to detect vehicles that are in a lane of the vehicle 1200 drive in or leave it, to be detected quickly.

For example, in at least one embodiment, medium-range RADAR systems can include a range of up to 160 m (front) or 80 m (rear) and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, short-range RADAR systems can use any number of RADAR sensor (s) without limitation. 1260 that are designed for installation at both ends of a rear bumper. In at least one embodiment, when the RADAR sensor system is installed at both ends of a rear bumper, it can generate two beams that constantly monitor blind spots in a rearward direction and beside a vehicle. In at least one embodiment, short range RADAR systems can be integrated into the ADAS system 1238 can be used to detect the blind spot and / or to assist you in changing lanes.

In at least one embodiment, the vehicle can 1200 further ultrasonic sensor (s) 1262 include. In at least one embodiment, the ultrasonic sensor (s) can 1262 at a front, a rear and / or side of the vehicle 1200 can be positioned, used for the parking aid and / or to create and update an occupancy grid. In at least one embodiment, a wide variety of ultrasonic sensor (s) 1262 can be used and different ultrasonic sensor (s) 1262 can be used for different detection ranges (e.g. 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensor (s) can 1262 operated at functional safety levels of ASIL B.

In at least one embodiment, the vehicle can 1200 LIDAR sensor (s) 1264 include. In at least one embodiment, the LIDAR sensor (s) can 1264 can be used for object and pedestrian detection, emergency braking, collision avoidance and / or for other functions. In at least one embodiment, the LIDAR sensor (s) can 1264 operated at the functional safety level ASIL B. In at least one embodiment, the vehicle can 1200 several LIDAR sensors 1264 (e.g. two, four, six, etc.) that can use an Ethernet channel (e.g. to provide data to a Gigabit Ethernet switch).

In at least one embodiment, the LIDAR sensor (s) can 1264 be able to provide a list of objects and their distances for a 360 degree field of view. In at least one embodiment, commercially available LIDAR sensor (s) 1264 for example, have an advertised range of approximately 100 m, with an accuracy of 2 cm to 3 cm, and with support for a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-protruding lidar sensors can be used. In such an embodiment, the LIDAR sensor (s) 1264 Include a small device that fits into a front, rear, side and / or corner of the vehicle 1200 can be embedded. In at least one embodiment, the LIDAR sensor (s) can 1264 in such an embodiment, provide a horizontal field of view of up to 120 degrees and a vertical field of view of up to 35 degrees with a range of 200 meters even for low reflectivity objects. In at least one embodiment, the front-mounted LIDAR sensor (s) 1264 be configured for a horizontal field of view between 45 degrees and 135 degrees.

In at least one embodiment, lidar technologies such as 3D flash lidar can also be used. In at least one embodiment, 3-D Flash LIDAR uses a laser flash as a source of transmission to the surroundings of the vehicle 1200 to illuminate up to about 200 m. In at least one embodiment, a flash LIDAR unit includes, without limitation, a receptor that records the laser pulse transit time and the reflected light at each pixel, which in turn represents a range of the vehicle 1200 corresponds to objects. In at least one embodiment, flash LIDAR can enable highly precise and distortion-free images of the environment to be generated with each laser flash. In at least one embodiment, four flash lidar sensors can be used, one on each side of the vehicle 1200 . In at least one embodiment, 3D flash lidar systems include, without limitation, a solid state, 3D staring array lidar camera with no moving parts other than a fan (e.g., a non-scanning lidar device). In at least one embodiment, the flash LIDAR device can use a 5 nanosecond class I laser pulse (eye-safe) per image and capture the reflected laser light as a 3D range point cloud and jointly registered intensity data.

In at least one embodiment, the vehicle can 1200 furthermore IMU sensor (s) 1266 include. In at least one embodiment, the IMU sensor (s) can 1266 in a center of a rear axle of the vehicle 1200 be arranged. In at least one embodiment, the IMU sensor (s) can 1266 for example, and without limitation, accelerometer (s), magnetometer (s), gyroscope (s), magnetic compass, magnetic compass (s), and / or other types of sensors. In at least one embodiment, such as in six-axis applications, the IMU sensor (s) can 1266 include, without limitation, accelerometers and gyroscopes. In at least one embodiment, such as in nine-axis applications, the IMU sensor (s) can 1266 include, without limitation, accelerometers, gyroscopes, and magnetometers.

In at least one embodiment, the IMU sensor (s) can 1266 be implemented as a miniaturized GPS-based inertial navigation system (GPS-Aided Inertial Navigation System - "GPS / INS") with high computing power, the inertial sensors of micro-electro-mechanical systems (micro-electro-mechanical systems - "MEMS"), a highly sensitive GPS receiver and advanced Kalman filter algorithms combined to provide estimates of position, speed and attitude. In at least one embodiment, the IMU sensor (s) can 1266 it to the vehicle 1200 allow you to estimate your course without the need for input from a magnetic sensor by observing changes in speed directly from a GPS and feeding it to the IMU sensor (s) 1266 be correlated. In at least one embodiment, the IMU sensor (s) can 1266 and GNSS sensor (s) 1258 be combined in a single integrated unit.

In at least one embodiment, the vehicle can 1200 Microphone (s) 1296 include those in and / or around the vehicle 1200 are placed around. In at least one embodiment, the microphone (s) can 1296 can be used, among other things, for the detection and identification of emergency vehicles.

In at least one embodiment, the vehicle can 1200 also include any number of camera types, including stereo camera (s) 1268 , Foresight camera (s) 1270 , Infrared camera (s) 1272 , All-round camera (s) 1274 , Long-range camera (s) 1298 , Medium-range camera (s) 1276 and / or other types of cameras. In at least one embodiment, cameras can be used to capture image data around the entire periphery of the vehicle 1200 around to capture. What types of cameras are used depends, in at least one embodiment, on the vehicle 1200 away. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around the vehicle 1200 around to provide. In at least one embodiment, a number of cameras used can differ depending on the embodiment. In at least one embodiment, the vehicle could 1200 for example, six cameras, seven cameras, ten cameras, twelve cameras, or some other number of cameras. In at least one embodiment, cameras may support Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet communication, for example and without limitation. In at least one embodiment, each camera could be as already discussed herein with respect to FIG 12A and 12B described in more detail.

In at least one embodiment, the vehicle can 1200 further vibration sensor (s) 1242 include. In at least one embodiment, the vibration sensor (s) can 1242 Vibrations from components of the vehicle 1200 such as axis (s). For example, in at least one embodiment, changes in vibrations may indicate a change in the road surface. When two or more vibration sensors 1242 are used, in at least one embodiment, the differences between the vibrations can be used to determine the friction or slip of the road surface (e.g. if there is a difference in vibration between a powered axle and a freely rotating axle).

In at least one embodiment, the vehicle can 1200 the ADAS system 1238 include. In at least one embodiment, the ADAS system 1238 in some examples include, without limitation, a SoC. In at least one embodiment, the ADAS system 1238 without restriction any number and combination of a system for autonomous / adaptive / automatic cruise control ("ACC"), a system for cooperative adaptive cruise control ("CACC"), a system for Forward crash warning ("FCW"), an automatic system for emergency braking ("AEB"), a system for lane departure warning ("LDW"), a system for lane keep assist ("LKA"), a system for blind spot warning (blind spot warning - "BSW"), a system for rear cross-traffic warning ("RCTW"), a system for collision warning ("CW"), a system for lane centering ("LC") ) and / or other systems, features and / or functions.

In at least one embodiment, the ACC system can RADAR sensor (s) 1260 , LIDAR sensor (s) 1264 and / or use any number of camera (s). In at least one embodiment, the ACC system can include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, a longitudinal ACC system monitors and controls the distance to another vehicle that is immediately in front of the vehicle 1200 located and it represents the speed of the vehicle 1200 automatically to maintain a safe distance from vehicles in front. In at least one embodiment, a lateral ACC system maintains a distance and advises the vehicle 1200 to change lanes if necessary. In at least one embodiment, a cross ACC is related to other ADAS applications, such as LC and CW.

In at least one embodiment, a CACC system uses information from other vehicles via the network interface 1224 and / or the wireless antenna (s) 1226 can be received by other vehicles via a wireless link or indirectly via a network connection (e.g. via the Internet). In at least one embodiment, direct links can be provided through a vehicle-to-vehicle ("V2V") communication link, while indirect links can be provided through an infrastructure-to-vehicle (infrastructure-to-vehicle - " I2V “-) communication link can be provided. In general, V2V communication provides information about vehicles immediately ahead (e.g. vehicles immediately in front of and in the same lane as the vehicle 1200 located), while I2V communication provides information about further traffic ahead. In at least one embodiment, a CACC system can include either or both of I2V and V2V information sources. In at least one embodiment, a CACC system may be given information about vehicles in front of the vehicle 1200 be more reliable and it has the potential to improve the smoothness of traffic flow and reduce congestion on the road.

In at least one embodiment, an FCW system is designed in such a way that it warns a driver of a danger so that such a driver can take corrective action. In at least one embodiment, an FCW system uses a front-facing camera and / or RADAR sensor (s) 1260 that are coupled, i.e. electrically coupled, to a dedicated processor, DSP, FPGA and / or ASIC to provide driver feedback, such as a display, a loudspeaker and / or a vibrating component. In at least one embodiment, an FCW system can provide a warning, such as in the form of a sound, a visual warning, a vibration, and / or a quick brake pulse.

In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or another object and it can automatically apply the brakes if a driver does not take a corrective measure within a predetermined time or distance parameter. In at least one embodiment, the AEB system can include front-facing camera (s) and / or RADAR sensor (s) 1260 that are coupled to a dedicated processor, DSP, FPGA and / or ASIC. When an AEB system detects a hazard, in at least one embodiment it typically first warns a driver to take corrective action to avoid a collision, and if that driver does not take corrective action, this AEB system can automatically apply the brakes operate in an effort to prevent or at least mitigate impact of a predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake assist and / or braking due to an impending collision.

In at least one embodiment, an LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to warn the driver when the vehicle is on 1200 crossed the lane markings. In at least one embodiment, an LDW system is not activated when a driver indicates intentionally leaving the lane, such as by activating the blinker. In at least one embodiment, an LDW system may use front and side cameras that are coupled, i.e. electrically coupled, to a dedicated processor, DSP, FPGA, and / or ASIC to provide driver feedback, such as a display , a loudspeaker and / or a vibrating component. In at least one embodiment, an LKA system is a variation of an LDW system. In at least one embodiment, an LKA system provides steering input or braking to the vehicle 1200 to correct in case the vehicle 1200 begins to leave its lane.

In at least one embodiment, a BSW system detects and warns a driver of vehicles in a blind spot of an automobile. In at least one embodiment, the BSW system can provide a visual, audible and / or tactile alarm to indicate that the threading into or changing of lanes is unsafe. In at least one embodiment, a BSW system can provide an additional warning when a driver is using a blinker. In at least one embodiment, a BSW system can include rear-facing camera (s) and / or RADAR sensor (s) 1260 that are coupled to a dedicated processor, DSP, FPGA and / or ASIC, i.e. electrically coupled to a feedback from the driver, such as a display, a loudspeaker and / or a vibrating component.

In at least one embodiment, an RCTW system can provide visual, audible, and / or tactile notification when an object is detected out of range of a rearview camera when the vehicle 1200 drives backwards. In at least one embodiment, an RCTW system includes an AEB system to ensure that vehicle brakes are applied to avoid a crash. In at least one embodiment, an RCTW system may have one or more rear-facing RADAR sensor (s) 1260 that are coupled to a dedicated processor, DSP, FPGA and / or ASIC, i.e. electrically coupled, to provide driver feedback, such as a display, speaker and / or vibrating component.

In at least one embodiment, traditional ADAS systems can be prone to false positives that can be annoying and distracting to the driver, but typically not catastrophic, as traditional ADAS systems warn a driver and allow that driver to decide whether to there really is a security condition and act accordingly. In at least one embodiment, the vehicle decides 1200 in case of conflicting results, whether the result of a primary computer or a secondary computer (e.g. a first controller or a second controller of the controllers) 1236 ) must be observed. In at least one embodiment, the ADAS system 1238 for example a backup and / or secondary computer that provides perceptual information to a rationality module of a backup computer. In at least one embodiment, a rationality monitor of a backup computer can run various redundant software on hardware components in order to detect errors in perception and in dynamic driving tasks. In at least one embodiment, the outputs from the ADAS system 1238 a supervisory MCU. In at least one embodiment, if outputs from a primary computer and outputs from a secondary computer contradict each other, a monitoring MCU determines how to resolve the contradiction to ensure safe operation.

In at least one embodiment, a primary computer can be configured to provide a monitoring MCU with a confidence score indicating a confidence of that primary computer for a selected outcome. In at least one embodiment, if this confidence score exceeds a threshold, this monitoring MCU can follow the lead of that primary computer, regardless of whether that secondary computer provides a contradicting or inconsistent result. In at least one embodiment where a confidence score does not meet a threshold and the primary and secondary computers report different results (e.g., a contradiction), a monitoring MCU can mediate between the computers to determine an appropriate result.

In at least In one embodiment, a supervisory MCU may be configured to run neural network (s) trained and configured to condition based at least in part on outputs from a primary computer and outputs from a secondary computer determine under which this secondary computer is providing false positives. In at least one embodiment, neural network (s) in a supervisory MCU can learn when and when output from a secondary computer can and cannot be trusted. For example, in at least one embodiment, if this secondary computer is a RADAR-based FCW system, neural network (s) in a monitoring MCU can learn when an FCW system identifies metallic objects that are not actually a hazard, such as a drain grate or manhole cover that triggers an alarm. In at least one embodiment, when a secondary computer is a camera-based LDW system, a neural network in a surveillance MCU can learn to override the LDW when cyclists or pedestrians are present and lane departure is indeed a safest maneuver. In at least one embodiment, a supervisory MCU may include at least one of a DLA or a GPU capable of running neural network (s) with associated memory. In at least one embodiment, a monitoring MCU can be a component of one or more SoC (s) 1204 include and / or be included as such.

In at least one embodiment, the ADAS system 1238 include a secondary computer that performs ADAS functionality using traditional machine vision rules. In at least one embodiment, this secondary computer can use classic machine vision rules (if-then) and the presence of a neural network (s) in a surveillance MCU can improve reliability, safety, and computing power. For example, in at least one embodiment, the diverse implementation and deliberate non-identity make an overall system more fault tolerant, particularly to errors caused by the functionality of software (or software-hardware interfaces). For example, if in at least one embodiment there is a software bug or bug in the software running on a primary computer and non-identical software code running on a secondary computer provides a consistent overall result, then a monitoring MCU may take a Have greater confidence that an overall result is correct and that a bug in software or hardware on that primary computer does not cause a material failure.

In at least one embodiment, an output of the ADAS system 1238 be fed into a perception block of a primary computer and / or into a block for dynamic driving tasks of a primary computer. If the ADAS system 1238 For example, indicating a forward crash warning due to an object immediately ahead, a awareness block in at least one embodiment may use this information in identifying objects. In at least one embodiment, a secondary computer can have its own neural network that is trained and thus reduces a risk of false positives, as described herein.

In at least one embodiment, the vehicle can 1200 also an infotainment SoC 1230 (e.g. an in-vehicle infotainment system (IVI system)). Although illustrated and described as a SoC, the infotainment SoC 1230 in at least one embodiment, not being a SoC and including, without limitation, two or more discrete components. In at least one embodiment, the infotainment SoC 1230 include, without limitation, any combination of hardware and software that can be used to power the vehicle 1200 Audio (e.g. music, a personal digital assistant, navigation instructions, news, radio, etc.), video (e.g. TV, films, streaming, etc.), telephone (e.g. hands-free calling), network connectivity (e.g. E.g. LTE, WiFi etc.) and / or information services (e.g. navigation systems, reverse parking aid, a radio data system, vehicle-related information such as fuel level, total distance traveled, brake fuel level, oil level, door opening / closing, air filter information, etc.). The infotainment SoC 1230 could for example radios, turntables, navigation systems, video playback devices, USB and Bluetooth connectivity, carputer, in-car entertainment, WiFi, audio controls on the steering wheel, a hands-free voice control element, a heads-up display - " HUD ”), an HMI display 1234 , a telematics device, a control panel (e.g. for controlling and / or interacting with various components, features and / or systems) and / or other components. In at least one embodiment, the infotainment SoC 1230 also used to identify user (s) of the vehicle 1200 Provide information (e.g. visual and / or acoustic), such as information from the ADAS system 1238 , Information on autonomous driving, such as planned vehicle maneuvers, trajectories, information on the surroundings (e.g. intersection information, vehicle information, road information, etc.) and / or other information.

In at least one embodiment, the infotainment SoC 1230 any amount and type of GPU functionality include. In at least one embodiment, the infotainment SoC 1230 over the bus 1202 with other devices, systems and / or components of the vehicle 1200 communicate. In at least one embodiment, the infotainment SoC 1230 be coupled to a supervisory MCU so that a GPU of an infotainment system can perform some self-driving functions if the primary controller (s) 1236 (e.g. primary and / or backup computer of the vehicle 1200 ) stand out. In at least one embodiment, the infotainment SoC 1230 the vehicle 1200 place in a mode of driving to a safe stop as described herein.

In at least one embodiment, the vehicle can 1200 also an instrument cluster 1232 (e.g. a digital dashboard, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, the combination instrument 1232 include, without limitation, a controller and / or a supercomputer (e.g., a discrete controller or supercomputer). In at least one embodiment, the combination instrument 1232 include, without limitation, any number and combination of a set of measurement equipment such as speedometer, fuel level, oil pressure, tachometer, odometer, turn signal, gear stick position indicator, seat belt warning light (s), parking brake warning light (s), engine malfunction light (s), information about supplemental restraint systems (e.g., airbags), lighting controls, safety system controls, navigational information, etc. In some examples, information may be displayed and / or from the infotainment SoC 1230 and the instrument cluster 1232 shared. In at least one embodiment, the combination instrument 1232 as part of the infotainment SoC 1230 be included or vice versa.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the inference and / or training logic 915 in the system 12C can be used for inference or prediction operations at least in part on the basis of weighting parameters calculated using training operations for neural networks, functions and / or architectures of neural networks or use cases described herein for neural networks.

12D is an illustration of a system 1276 for communication between cloud-based server (s) and the autonomous vehicle 1200 out 12A according to at least one embodiment. In at least one embodiment, the system 1276 without restriction the server (s) 1278 , the network (s) 1290 and any number and type of vehicles, including the vehicle 1200 , include. In at least one embodiment, the server (s) can 1278 a multitude of GPUs without limitation 1284 (A) -1284 (H) (collectively referred to herein as GPUs 1284 designated), PCIe switches 1282 (A) -1282 (D) (herein together as PCIe switches 1282 designated) and / or CPUs 1280 (A) -1280 (B) (herein collectively referred to as CPUs 1280 labeled). In at least one embodiment, the GPUs can 1284 , CPUs 1280 and PCIe switches 1282 be interconnected with high-speed interconnects such as, for example and without limitation, the NVLink interfaces 1288 developed by NVIDIA and / or PCIe connections 1286 . In at least one embodiment, the are GPUs 1284 connected via an NVLink and / or NVSwitch SoC and the GPUs 1284 and the PCIe switches 1282 connected via PCIe interconnections. Although eight GPUs 1284 , two CPUs 1280 and four PCIe switches 1282 are illustrated, this is not intended to be limiting. In at least one embodiment, each of the server (s) can 1278 any number of GPUs without limitation 1284 , CPUs 1280 and / or PCIe switches 1282 in any combination. For example, in at least one embodiment, the server (s) 1278 eight, sixteen, thirty-two, and / or more GPUs respectively 1284 include.

In at least one embodiment, the server (s) can 1278 via the network (s) 1290 and receive image data from vehicles representative of images showing unexpected or changed road conditions, such as recently commenced road works. In at least one embodiment, the server (s) can 1278 via the network (s) 1290 and neural networks on the vehicles 1292 , updated or otherwise, and / or map information 1294 transmitted, including, without limitation, information related to traffic and road conditions. In at least one embodiment, updates to the map information 1294 updates for the HD card without restriction 1222 contain, such as information regarding construction sites, potholes, diversions, floods and / or other obstacles. In at least one embodiment, the neural networks 1292 and / or map information 1294 have resulted from new training and / or experiences presented in data received from any number of vehicles in an environment and / or based at least in part on training carried out in a data center (e.g. under Use of the server (s) 1278 and / or other servers).

In at least one embodiment, the server (s) can 1278 can be used to train machine learning models (e.g. neural networks) based at least in part on training data. In at least one embodiment, the training data can be generated by vehicles and / or generated in a simulation (e.g. using a game engine). In at least one embodiment, any amount of training data is tagged (e.g., if the associated neural network benefits from supervised learning) and / or subjected to other preprocessing. In at least one embodiment, any set of training data is not tagged and / or preprocessed (e.g., if the neural network associated therewith does not require supervised learning). In at least one embodiment, once the machine learning models are trained, the machine learning models are used by vehicles (e.g. via the network (s) 1290 to vehicles) and / or the machine learning models can be used by the server (s) 1278 used to remotely monitor vehicles.

In at least one embodiment, the server (s) can 1278 Receive data from vehicles and apply the data to current real-time neural networks for intelligent real-time inference. In at least one embodiment, the server (s) can 1278 Include deep learning supercomputers and / or dedicated AI computers powered by the GPU (s) 1284 such as the DGX and DGX station machines developed by NVIDIA. In at least one embodiment, the server (s) can 1278 however, include a deep learning infrastructure using CPU-powered data centers.

In at least one embodiment, the deep learning infrastructure of the server (s) 1278 be able to and use that ability to infer the state of processors, software and / or associated hardware in the vehicle, quickly and in real time 1200 to evaluate and verify. For example, in at least one embodiment, the deep learning infrastructure can receive periodic updates from the vehicle 1200 received, such as a sequence of images and / or objects that represent the vehicle 1200 localized in this sequence of images (e.g. via machine vision and / or other machine learning techniques for object classification). In at least one embodiment, the deep learning infrastructure can run its own neural network to identify objects and compare them to objects passed by the vehicle 1200 identified, and if the results do not match and the deep learning infrastructure concludes that the AI in the vehicle 1200 malfunctions, the server (s) can 1278 a signal to the vehicle 1200 transmitted to a fail-safe computer in the vehicle 1200 instructs to take control, notify passengers, and perform a safe parking maneuver.

In at least one embodiment, the server (s) can 1278 GPU (s) 1284 and include one or more programmable inference accelerators (e.g., TensorRT-3 devices from NVIDIA). In at least one embodiment, a combination of GPU-powered servers and inference acceleration can enable real-time responsiveness. In at least one embodiment, such as when computing power is less critical, servers powered by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, the hardware structure (s) 915 used to perform one or more embodiments. Details regarding the hardware structure (s) 915 are herein in connection with 9A and / or 9B provided.

COMPUTER SYSTEMS

13th FIG. 13 is a block diagram illustrating an example computer system that may be an interconnected device and component system, a system on a chip (SOC), or a combination thereof formed with a processor that may include execution units for executing an instruction, in accordance with at least one embodiment. In at least one embodiment, a computer system 1300 a component, such as a processor, without limitation 1302 , to use execution units including logic to perform algorithms on process data in accordance with the present disclosure, such as in the embodiment described herein. In at least one embodiment, the computer system can 1300 Processors include, such as the PENTIUM® processor family, the Xeon ™, Itanium®, XScale ™, and / or StrongARM ™, Intel® Core ™, or Intel® Nervana ™ microprocessors available from Intel Corporation of Santa Clara, California although other systems (including personal computers having other microprocessors, engineering workstations, set top boxes, and the like) can be used. In at least one embodiment, the computer system can 1300 run a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces can be used.

Embodiments can be used in other devices such as handheld devices and embedded applications. Some examples of portable devices are cell phones, internet protocol devices, digital cameras, personal digital assistants ("PDAs"), and portable personal computers. In at least one embodiment, embedded applications can include a microcontroller, a digital signal processor ("DSP"), a system on a chip, network computers ("NetPCs"), set-top boxes, network hubs, switches for a wide area network (wide area network - "WAN") or any other system that can perform one or more instructions in accordance with at least one embodiment.

In at least one embodiment, the computer system can 1300 without limitation the processor 1302 include, without limitation, one or more execution units 1308 to perform training and / or inferencing a machine learning model in accordance with the techniques described herein. In at least one embodiment, the computer system is 1300 a single processor desktop or server system, but in another embodiment the computer system may 1300 be a multiprocessor system. In at least one embodiment, the processor can 1302 without limitation a microprocessor for a Complex Instruction Set Computer (“CISC”), a microprocessor for Reduced Instruction Set Computing (“RISC”), a Very Long Instruction Word (“VLIW”) microprocessor, a processor that implements a combination of instruction sets, or any other processing device such as a digital signal processor. In at least one embodiment, the processor can 1302 to a processor bus 1310 be coupled of the data signals between the processor 1302 and other components in the computer system 1300 can transfer.

In at least one embodiment, the processor can 1302 an internal level 1 ( _" L1") cache memory ("cache") without restriction 1304 include. In at least one embodiment, the processor can 1302 have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory can be external to the processor 1302 condition. Other embodiments may also include a combination of both internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, a register bank 1306 store different types of data in various registers including, without limitation, integer registers, floating point registers, status registers, and an instruction pointer register.

The execution unit is located in at least one embodiment 1308 including, without limitation, the logic for performing integer and floating point operations, also in the processor 1302 . In at least one embodiment, the processor can 1302 also contain read only memory ("ROM") for microcode ("µcode"), which stores microcode for certain macro instructions. In at least one embodiment, the execution unit 1308 Logic for handling a packed instruction set 1309 include. In at least one embodiment, by including the packed instruction set 1309 into an instruction set of a general purpose processor along with associated circuitry for executing instruction operations used by many multimedia applications using packed data in the processor 1302 be performed. In one or more embodiments, many multimedia applications can be run faster and more efficiently by using the full width of a processor's data bus to perform operations on packed data, eliminating the need to transfer smaller data units over that processor's data bus. to perform one or more operations on one data item at a time.

In at least one embodiment, the execution unit 1308 also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, the computer system can 1300 without limitation a memory 1320 include. In at least one embodiment, the memory 1320 a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other storage device. In at least one embodiment, the memory 1320 Instructions) 1319 and / or data 1321 store represented by data signals transmitted by the processor 1302 can be executed.

In at least one embodiment, a system logic chip can be attached to the processor bus 1310 and the memory 1320 be coupled. In at least one embodiment, a system logic chip may, without limitation, be a memory controller hub ("MCH") 1316 include and the processor 1302 with the MCH 1316 via the processor bus 1310 communicate. In at least one embodiment, the MCH 1316 the memory 1320 a storage path 1318 with high bandwidth for instruction and data storage as well as for the storage of graphic commands, data and textures. In at least one embodiment, the MCH 1316 Data signals between the processor 1302 , the memory 1320 and other components in the computer system 1300 route and data signals between the processor bus 1310 , the memory 1320 and a system I / O interface 1322 bridge. In at least one embodiment, a system logic chip can have a graphics port for coupling to a Provide graphics control. In at least one embodiment, the MCH 1316 through a storage path 1318 with high bandwidth to the memory 1320 be coupled and a graphics / video card 1312 through an Accelerated Graphics Port (“AGP”) interconnection 1314 to the MCH 1316 be coupled.

In at least one embodiment, the computer system can 1300 the system I / O interface 1322 as a proprietary hub interface bus to connect the MCH 1316 to an I / O control hub (I / O controller hub - "ICH") 1330 to pair. In at least one embodiment, the ICH 1330 provide direct connections to some I / O devices through a local I / O bus. In at least one embodiment, a local I / O bus may, without limitation, be a high speed I / O bus for connecting peripheral devices to storage 1320 , a chipset and the processor 1302 include. Examples can include audio control without limitation 1329 , a firmware hub ("Flash BIOS") 1328 , a wireless transceiver 1326 , a data store 1324 , an older I / O controller 1323 , the user input and keyboard interfaces 1325 contains a serial expansion port 1327 , such as a Universal Serial Bus ("USB") port, and network control 1334 include. In at least one embodiment, the data memory 1324 a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device.

Illustrated in at least one embodiment 13th a system that includes interconnected hardware devices, or "chips," whereas 13th in other embodiments may illustrate an exemplary SoC. In at least one embodiment, the in 13th illustrated devices may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or a combination thereof. In at least one embodiment, there are one or more components of the computer system 1300 interconnected using Compute Express Link (CXL) interconnects.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the inference and / or training logic 915 in the system 13th can be used for inference or prediction operations at least in part on the basis of weighting parameters calculated using training operations for neural networks, functions and / or architectures of neural networks or use cases described herein for neural networks.

14th Fig. 3 is a block diagram showing an electronic device 1400 for the benefit of a processor 1410 illustrated according to at least one embodiment. In at least one embodiment, the electronic device can 1400 for example, without limitation, a notebook, tower server, rack server, blade server, laptop, desktop, tablet, mobile device, phone, embedded computer, or any other suitable electronic device .

In at least one embodiment, the electronic device can 1400 without limitation the processor 1410 that is communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor is 1410 coupled using a bus or interface, such as an I ² C bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface - “SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (version 1 , 2, 3 etc.) or a universal asynchronous receiver / transmitter (“UART”) bus. Illustrated in at least one embodiment 14th a system that includes interconnected hardware devices, or "chips," whereas 14th in other embodiments may illustrate an exemplary SoC. In at least one embodiment, the in 14th illustrated devices may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components are made up 14th interconnected using Compute Express Link (CXL) interconnects.

In at least one embodiment, can 14th an ad 1424 , a touch screen 1425 , a touchpad 1430 , a unit for near field communications ("NFC") 1445 , a sensor hub 1440 , a thermal sensor 1446 , an express chipset (Express Chipset - "EC") 1435 , a Trusted Platform Module ("TPM") 1438 , BIOS / firmware / flash memory ("BIOS, FW flash") 1422 , a DSP 1460 , a drive 1420 such as a solid state disk ("SSD") or a Hard disk drive ("HDD"), a unit for a wireless local area network ("WLAN") 1450 , a bluetooth unit 1452 , a unit for a wireless wide area network ("WWAN") 1456 , a unit for a global positioning system (GPS) 1455 , a camera ("USB 3.0 camera") 1454 such as a USB 3.0 camera and / or a low-power double data rate ("LPDDR") storage unit ("LPDDR3") 1415 implemented in an LPDDR3 standard, for example. These components can each be implemented in any suitable manner.

In at least one embodiment, other components can be communicative to the processor through components described herein 1410 be coupled. In at least one embodiment, an accelerometer can be used 1441 , an ambient light sensor ("ALS") 1442 , a compass 1443 and a gyroscope 1444 communicative to the sensor hub 1440 be coupled. In at least one embodiment, a thermal sensor 1439 , a fan 1437 , a keyboard 1436 and a touchpad 1430 communicative to the EC 1435 be coupled. In at least one embodiment, speakers 1463 , Headphone 1464 and a microphone ("micro") 1465 communicatively to an audio unit ("audio codec and class D amplifier") 1462 be coupled, which in turn communicatively to the DSP 1460 can be coupled. In at least one embodiment, the audio unit can 1462 include, for example and without limitation, an audio encoder / decoder ("Codec") and a Class D amplifier. In at least one embodiment, a SIM card ("SIM") 1457 communicative to the WWAN unit 1456 be coupled. In at least one embodiment, components such as the WLAN unit 1450 and the bluetooth unit 1452 as well as the WWAN unit 1456 be implemented in a Next Generation Form Factor ("NGFF").

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the inference and / or training logic 915 in the system 14th can be used for inference or prediction operations at least in part on the basis of weighting parameters calculated using training operations for neural networks, functions and / or architectures of neural networks or use cases described herein for neural networks.

15th illustrates a computer system 1500 according to at least one embodiment. In at least one embodiment, the computer system is 1500 configured to implement various processes and methods described in this disclosure.

In at least one embodiment, the computer system comprises 1500 without restriction at least one central processing unit ("CPU") 1502, which is connected to a communication bus 1510 implemented using any suitable protocol such as Peripheral Component Interconnect (PCI), Peripheral Component Interconnect Express (PCI-Express), Accelerated Graphics Port (AGP), HyperTransport, or any other bus - or point-to-point communication protocol (s). In at least one embodiment, the computer system includes 1500 a main memory without restriction 1504 and control logic (e.g. implemented as hardware, software, or a combination thereof) and data are in main memory 1504 which may take the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1522 an interface to other computing devices and networks ready to transfer data from other systems to the computer system 1500 to receive and transmit to them.

In at least one embodiment, the computer system includes 1500 without limitation, input devices in at least one embodiment 1508 , a parallel processing system 1512 and display devices 1506 implemented using a conventional cathode ray tube ("CRT"), liquid crystal display ("LCD"), light emitting diode ("LED") display, plasma display, or other suitable display technology could be. In at least one embodiment, user inputs are from input devices 1508 such as keyboard, mouse, touchpad, microphone, etc. received. In at least one embodiment, each module described herein can reside on a single semiconductor platform to form a processing system.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least In one embodiment, the inference and / or training logic 915 in the system 15th can be used for inference or prediction operations at least in part on the basis of weighting parameters calculated using training operations for neural networks, functions and / or architectures of neural networks or use cases described herein for neural networks.

16 illustrates a computer system 1600 according to at least one embodiment. In at least one embodiment, the computer system includes 1600 without limitation a computer 1610 and a USB stick 1620 . In at least one embodiment, the computer can 1610 include, without limitation, any number and type of processor (s) (not shown) and memory (not shown). In at least one embodiment, the computer includes 1610 without limitation a server, a cloud instance, a laptop and a desktop computer.

In at least one embodiment, the USB stick contains 1620 one processing unit without restriction 1630 , a USB interface 1640 and USB interface logic 1650 . In at least one embodiment, the processing unit can 1630 any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit can 1630 include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, the processing unit comprises 1630 an application specific integrated circuit ("ASIC") optimized to perform any amount and type of operations associated with machine learning. For example, in at least one embodiment, is the processing unit 1630 a Tensor Processing Unit ("TPC") optimized to perform machine learning inference operations. In at least one embodiment, the processing unit is 1630 a vision processing unit ("VPU") optimized for performing machine vision and machine learning inference operations.

In at least one embodiment, the USB interface can 1640 be any type of USB plug or USB socket. For example, in at least one embodiment is the USB interface 1640 a USB 3.0 Type-C socket for data and power. In at least one embodiment, the USB interface is 1640 a USB 3.0 Type A plug. In at least one embodiment, the USB interface logic 1650 involve any amount and type of logic that allows the processing unit 1630 allows via the USB connector 1640 an interface with devices (e.g. the computer 1610 ) to build.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the inference and / or training logic 915 in the system 16 can be used for inference or prediction operations at least in part on the basis of weighting parameters calculated using training operations for neural networks, functions and / or architectures of neural networks or use cases described herein for neural networks.

17A illustrates an example architecture that uses a variety of GPUs 1710 (1) -1710 (N) over high speed links 1740 (1) -1740 (N) (e.g. buses, point-to-point interconnections, etc.) communicatively to a variety of multi-core processors 1705 (1) -1705 (M) is coupled. In at least one embodiment, the links support high speed links 1740 (1) -1740 (N) a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s or higher. In at least one embodiment, various interconnection protocols may be used including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In different figures, “N” and “M” represent positive integers, the values of which can vary from figure to figure.

Additionally, and in at least one embodiment, there are two or more of the GPUs 1710 over high speed links 1729 (1) -1729 (2) interconnected, which may be implemented using similar or different protocols / links than those used for the high-speed links 1740 (1) -1740 (N) be used. Similarly, two or more of the multi-core processors 1705 over a high speed link 1728 which can be symmetric multi-processor (SMP) buses operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, all communication between the various in 17A system components shown can be achieved using similar protocols / links (e.g. via a common interconnection structure).

In at least one embodiment, each is a multi-core processor 1705 each via storage interconnections 1726 (1) -1726 (M) communicatively to a processor memory 1701 (1) -1701 (M) paired and any GPU 1710 (1) -1710 (N) each via GPU memory interconnections 1750 (1) -1750 (N) communicative to the GPU memory 1720 (1) -1720 (N) coupled. In at least one embodiment, the memory interconnects 1726 and 1750 use similar or different memory access technologies. With the processor memories 1701 (1) -1701 (M) and the GPU memories 1720 For example, it can be, without limitation, volatile memory such as dynamic random access memory (DRAM) (including stacked DRAMs), graphics DDR-SDRAM (GDDR) (e.g. GDDR5, GDDR6), or high-bandwidth memory - HBM) and / or non-volatile memories such as 3D XPoint or Nano-Ram. In at least one embodiment, a portion of the processor memory 1701 volatile memory and another section of non-volatile memory (e.g. using a two-level memory (2LM) hierarchy).

As described herein, various multi-core processors 1705 and GPUs 1710 although physically to a specific memory 1701 or. 1720 be coupled and / or implemented a uniform memory architecture in which a virtual system address space (also referred to as “effective address space”) is distributed over different physical memories. For example, the processor memory 1701 (1) -1701 (M) each include 64 GB of system memory address space and the GPU memory 1720 (1) -1720 (N) each have 32 GB of system memory address space, resulting in a total of 256 GB of addressable memory when M = 2 and N = 4. Other values for N and M are possible.

17B illustrates additional details for interconnection between a multi-core processor 1707 and a graphics accelerator module 1746 according to an exemplary embodiment. In at least one embodiment, the graphics accelerator module 1746 include one or more GPU chips integrated on a line card that over a high speed link 1740 (e.g. a PCIe bus, NVLink, etc.) to the processor 1707 is coupled. In at least one embodiment, the graphics accelerator module 1746 alternatively on a housing or chip with the processor 1707 be integrated.

In at least one embodiment, the processor includes 1707 a variety of cores 1760A-1760D , each with a translation lookaside buffer ("TLB") 1761A-1761D and one or more caches 1762A-1762D . In at least one embodiment, the cores 1760A-1760D include various other components for executing instructions and processing data that are not illustrated. In at least one embodiment, the caches 1762A-1762D Include level 1 (L1) and level 2 (L2) caches. You can also have one or more shared caches 1756 in the caches 1762A-1762D be included and from sets of kernels 1760A-1760D shared. One embodiment of the processor 1707 includes, for example, 24 cores, each with its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared between two adjacent cores. In at least one embodiment, the processor is 1707 and the graphics accelerator module 1746 with the system memory 1714 connected to the processor memory 1701 (1) -1701 (M) out 17A may include.

In at least one embodiment, consistency is maintained for data and instructions that are in different caches 1762A-1762D , 1756 and system memory 1714 are stored via inter-core communication via a coherence bus 1764 maintain. For example, in at least one embodiment, each cache may have cache coherency logic / circuitry associated therewith to respond to detected reads or writes to particular cache lines over the coherency bus 1764 to communicate. In at least one embodiment, a cache snooping protocol is used over the coherence bus 1764 implemented to control cache access via snooping.

In at least one embodiment, a proxy circuit couples 1725 the graphics accelerator 1746 communicative to the coherence bus 1764 what it is the graphics accelerator 1746 allows to peer the cores on a cache coherency protocol 1760A-1760D to participate. In particular, in at least one embodiment, there is an interface 1735 Connectivity with the proxy circuit 1725 over a high speed link 1740 ready and an interface 1737 connects the graphics accelerator module 1746 with the high speed link 1740 .

In at least one embodiment, an accelerator integration circuit provides 1736 Cache management, memory access, context management and interrupt management services on behalf a variety of graphics processing engines 1731 (1) -1731 (N) of the graphics accelerator 1746 ready. In at least one embodiment, the graphics processing engines 1731 (1) -1731 (N) each comprise a separate graphics processing unit (GPU). In at least one embodiment, the graphics processing engines 1731 (1) -1731 (N) alternatively, include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), scanners, and blit engines. In at least one embodiment, the graphics accelerator module 1746 a GPU with a variety of graphics processing engines 1731 (1) -1731 (N) his or the graphics processing engines 1731 (1) -1731 (N) can be individual GPUs that are integrated on a common housing, a line card or a chip.

In at least one embodiment, includes the accelerator integration circuit 1736 a memory management unit (MMU) 1739 to perform various memory management functions, such as virtual to physical memory translations (also known as effective to real memory translations) and memory access protocols to access system memory 1714 . The MMU 1739 may also include, in at least one embodiment, an address translation buffer (TLB) (not shown) for caching translations from virtual / effective to physical / real addresses. In at least one embodiment, a cache 1738 Commands and data for efficient access by the graphics processing engines 1731 (1) -1731 (N) to save. In at least one embodiment, the 1738 and in the graphics memory 1733 (1) -1733 (M) stored data with the core caches 1762A-1762D , 1756 and the system memory 1714 kept coherent, possibly using a retrieval unit 1744 . As mentioned, this can be done via the proxy circuit 1725 on behalf of the cache 1738 and the memory 1733 (1) -1733 (M) achieved (e.g., sending updates to the cache 1738 with regard to modifications / accesses to cache lines in the processor caches 1762A-1762D , 1756 and receiving updates from the cache 1738 ).

In at least one embodiment, a set of registers stores 1745 Context data for threads passed by the graphics processing engines 1731 (1) -1731 (N) and a context management circuit 1748 manages thread contexts. For example, the context management circuit 1748 Perform backup and restore operations to back up and restore contexts of different threads during context switches (for example, when backing up a first thread and saving a second thread so that a second thread can be executed by a graphics processing engine). For example, the context management circuit 1748 store current register values in a designated region in memory upon context switch (e.g. identified by a context pointer). It can then restore the register values when returning to a context. In at least one embodiment, an interrupt management circuit receives and processes 1747 interrupts received from system devices.

In one implementation, virtual / effective addresses are provided by a graphics processing engine 1731 through the MMU 1739 in real / physical addresses in the system memory 1714 translated. In at least one embodiment, the accelerator integration circuit supports 1736 multiple (e.g. 4, 8, 16) graphics accelerator modules 1746 and / or other accelerator devices. The graphics accelerator module 1746 may, in at least one embodiment, be dedicated to a single application running on the processor 1707 running or shared by multiple applications. In at least one embodiment, a virtualized graphics execution environment is shown in which the resources of the graphics processing engines 1731 (1) -1731 (N) shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources may be divided into "slices" that are allocated to different VMs and / or applications based on processing requirements and priorities associated with VMs and / or applications.

In at least one embodiment, the accelerator integration circuit functions 1736 as a bridge to a system for the graphics accelerator module 1746 and it provides address translation and system memory cache services. In addition, the accelerator integration circuit 1736 in at least one embodiment, provide virtualization devices for a host processor in order to virtualize the graphics processing engines 1731 (1) -1731 (N) Manage interruptions and memory management.

Since, in at least one embodiment, the hardware resources of the graphics processing engines 1731 (1) -1731 (N) are explicitly mapped to a real address space assigned to the host processor 1707 any host processor can directly address these resources using an effective address value. In at least one embodiment, is a function of the accelerator integration circuit 1736 the physical separation of the graphics processing engines 1731 (1) -1731 (N) so that they appear as independent units to a system.

In at least one embodiment, there are one or more graphics memories 1733 (1) -1733 (M) each to each of the graphics processing engines 1731 (1) -1731 (N) coupled and N = M. In at least one embodiment, the graphics memories store 1733 (1) -1733 (M) Instructions and data passed by each of the graphics processing engines 1731 (1) -1731 (N) are processed. In at least one embodiment, it can be the graphics memories 1733 (1) -1733 (M) volatile memories such as DRAMs (including stacked DRAMs), GDDR memories (e.g. GDDR5, GDDR6) or HBM, and / or non-volatile memories such as 3D XPoint or Nano-Ram.

In one embodiment, to reduce traffic over the high speed link 1740 Distortion techniques are used to ensure that it is in the graphics memory 1733 (1) -1733 (M) Stored data is data that is most commonly used by the graphics processing engines 1731 (1) -1731 (N) and preferably not through the cores 1760A-1760D used (at least not often). Similarly, in at least one embodiment, a warping mechanism attempts to extract data from the cores (and preferably not from the graphics processing engines 1731 (1) -1731 (N) ) are needed within the caches 1762A-1762D , 1756 and system memory 1714 to keep.

17C Figure 12 illustrates another exemplary embodiment in which the accelerator integration circuit 1736 into the processor 1707 is integrated. In this embodiment, the graphics processing engines communicate 1731 (1) -1731 (N) directly through the high speed link 1740 with the accelerator integration circuit 1736 through the interface 1737 and the interface 1735 (which in turn can be any form of bus or interface protocol). In at least one embodiment, the accelerator integration circuit 1736 perform operations similar to those relating to 17B but possibly with a higher throughput since they are in close proximity to the coherence bus 1764 and the caches 1762A-1762D , 1756 is located. At least one embodiment supports different programming models, including a dedicated process programming model (without virtualization of the graphics accelerator module) and shared programming models (with virtualization), which may include programming models enabled by the accelerator integration circuit 1736 and programming models that are controlled by the graphics accelerator module 1746 being controlled.

In at least one embodiment, the graphics processing engines are 1731 (1) -1731 (N) dedicated to a single application or process under a single operating system. In at least one embodiment, a single application may have different application needs about the graphics processing engine 1731 (1) -1731 (N) steer and thus provide a virtualization within a VM / partition.

In at least one embodiment, the graphics processing engines 1731 (1) -1731 (N) shared by multiple VM / application partitions. In at least one embodiment, shared models can use a system hypervisor to run the graphics processing engines 1731 (1) -1731 (N) virtualize and enable access by any operating system. Single-partition systems with no hypervisor have the graphics processing engines 1731 (1) -1731 (N) in at least one embodiment owned by an operating system. In at least one embodiment, an operating system can run the graphics processing engines 1731 (1) -1731 (N) virtualize to provide access to any process or application.

In at least one embodiment, the graphics accelerator module selects 1746 or a single graphics processing engine 1731 (1) -1731 (N) select a process item using a process identifier. In at least one embodiment, the process elements are in system memory 1714 is stored and addressable using the technique described herein for translating effective addresses to real addresses. In at least one embodiment, a process identifier can be an implementation-specific value that is provided to a host process when it is contextualized with the graphics processing engine 1731 (1) -1731 (N) registered (that is, calling the system software to add a process item to a list associated with the process item). In at least one embodiment, the lower 16 bits of a process identifier can be an offset of a process element within a list linked to the process element.

17D illustrates an exemplary accelerator integration disk 1790 . In at least one embodiment, a “slice” comprises a predetermined portion of the processing resources of the accelerator integration circuit 1736 . In at least one embodiment, an application is an effective address space 1782 within system memory 1714 , the process elements 1783 saves. In at least one embodiment, process elements 1783 in response to GPU calls 1781 of applications 1780 that is on the processor 1707 are saved. In at least one embodiment, contains a process element 1783 the process status for the corresponding application 1780 . In at least one embodiment, a in the process element 1783 included work descriptor (WD) 1784 be a single task requested by an application or contain a pointer to a queue of tasks. In at least one embodiment, the WD is 1784 a pointer to a job request queue in the effective address space 1782 an application.

In at least one embodiment, the graphics accelerator module 1746 and / or the individual graphics processing engines 1731 (1) -1731 (N) shared by all or a subset of the processes in a system. In at least one embodiment, an infrastructure for setting up the process states and for sending a WD 1784 to a graphics accelerator 1746 to start a task in a virtualized environment.

In at least one embodiment, a programming model with a dedicated process is implementation-specific. In at least one embodiment, in this model, a single process owns the graphics accelerator module 1746 or a single graphics processing engine 1731 . When the graphics accelerator 1746 is owned by a single process, in at least one embodiment a hypervisor initializes the accelerator integration circuit 1736 for a owning partition and an operating system initializes the accelerator integration circuit 1736 for an owning process if the graphics accelerator 1746 assigned.

In at least one embodiment, a WD retrieval unit calls during operation 1791 in the accelerator integration disk 1790 the next WD 1784 which includes an indication of the work done by one or more graphics processing engines of the graphics accelerator 1746 is to be done. In at least one embodiment, data from the WD 1784 in the registers 1745 stored and through the MMU 1739 , the interrupt management circuit 1747 and / or the context management circuit 1748 used as illustrated. One embodiment of the MMU 1739 includes, for example, a segment / page scroller for accessing segment / page tables 1786 within the virtual address space 1785 of an OS. In at least one embodiment, the interrupt management circuit 1747 from the graphics accelerator 1746 received interruption events 1792 process. In performing graphics operations, in at least one embodiment, one is performed by a graphics processing engine 1731 (1) -1731 (N) effective address generated 1793 through the MMU 1739 translated into a real address.

In at least one embodiment, registers 1745 for any graphics processing engine 1731 (1) -1731 (N) and / or any graphics accelerator module 1746 duplicated and they can be initialized by a hypervisor or an operating system. Each of these duplicated registers can, in at least one embodiment, be in an accelerator integration disk 1790 be included. Exemplary registers that can be initialized by a hypervisor are shown in Table 1. Table 1 - Registers initialized by hypervisor Register no description 1 Disk control register 2 Area pointer for planned processes for real addresses (real address - RA) 3 Authority Mask Override Register 4th Break vector table entry offset 5 Break vector table entry limit 6th Status register 7th Logical partition ID 8th Real Address Hypervisor Accelerator Usage Record Pointers (RA) 9 Memory description register

Exemplary registers that can be initialized by an operating system are shown in Table 2. Table 2 - Registers initialized by the operating system Resister no description 1 Process and thread identification 2 Context Backup / Restore Pointers for Effective Addresses (EA) 3 Accelerator Usage Record Pointer for Virtual Addresses (VA) 4th Virtual Address (VA) Memory Segment Table Pointers 5 Authority mask 6th Work descriptor

In at least one embodiment, each is a WD 1784 specific for a concrete graphics accelerator module 1746 and / or the graphics processing engines 1731 (1) -1731 (N) . In at least one embodiment, it contains all of the information necessary for a graphics processing engine 1731 (1) -1731 (N) required to do work, or it can be a pointer to a location where an application has established a command queue of work to be completed.

17E illustrates additional details for an exemplary embodiment of a shared model. This embodiment includes a real hypervisor address space 1798 , in which a process element list 1799 is saved. In at least one embodiment, the real hypervisor address space can be accessed 1798 through a hypervisor 1796 accessed by the graphics accelerator engines for the operating system 1795 virtualized.

In at least one embodiment, shared programming models enable all or a subset of processes from all or a subset of partitions in a system to have a graphics accelerator module 1746 use. In at least one embodiment, there are two programming models that use the graphics accelerator module 1746 is shared by several processes and partitions, namely shared via time slices and shared via directed graphics.

In at least one embodiment, the system has hypervisor in this model 1796 the graphics accelerator 1746 and it provides its function to all operating systems 1795 to disposal. So a graphics accelerator 1746 the virtualization through the system hypervisor 1796 supports the graphics acceleration module in at least one embodiment 1746 comply with certain requirements, such as (1) an application's task request must be autonomous (that is, the state does not need to be maintained between tasks), or the graphics accelerator 1746 must provide a mechanism for backing up and restoring context, (2) the graphics accelerator 1746 guarantees that an application's task request will be completed within a specified amount of time, including any translation errors, or the graphics accelerator 1746 provides a capability to anticipate the processing of a task and (3) the graphics accelerator module 1746 fairness between processes must be guaranteed when operating in a directed shared programming model.

In at least one embodiment it is required that the application 1780 a system call of the operating system 1795 with a graphics accelerator type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the type of graphics acceleration module describes a targeted acceleration function for a system call. In at least one embodiment, the type of graphics acceleration module can be a system-specific value. In at least one embodiment, the WD is specific to the Graphics accelerator 1746 formatted and it can be in the form of a command from the graphics accelerator 1746 , an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure to be used by the graphics accelerator 1746 Describe the work to be done.

In at least one embodiment, an AMR value is an AMR condition to be used for a current process. In at least one embodiment, a value that is passed to an operating system is similar to an application that sets an AMR. If in at least one embodiment implementations of the accelerator integration circuit 1736 (not shown) and the graphics accelerator module 1746 do not support a User Authority Mask Override Register (UAMOR), an operating system can apply a current UAMOR value to an AMR value before committing an AMR in a hypervisor call. In at least one embodiment, the hypervisor 1796 optionally apply a current value for an Authority Mask Override Register (AMOR) prior to an AMR in the process element 1783 is placed. In at least one embodiment, CSRP is one of the registers 1745 that is an effective address of a range in the effective address space 1782 an application for the graphics accelerator 1746 for backing up and restoring the context state. In at least one embodiment, this pointer is optional if no state has to be saved between tasks or when a task is preempted. In at least one embodiment, the context backup / restore area may be pinned system storage.

When receiving a system call, the operating system may 1795 verify that the application 1780 is registered and has the authority to use the graphics accelerator 1746 got. In at least one embodiment, the operating system calls 1795 then the hypervisor 1796 with the information shown in Table 3. Table 3 - OS to hypervisor call parameters Parameter no. Description: 1 A work descriptor (WD) 2 An Authority Mask Register (AMR) value (possibly masked) 3 A context save / restore area pointer (CSRP) for effective addresses (EA) 4th A process ID (PID) and optionally a thread ID (TID) 5 An accelerator utilization record pointer (AURP) for virtual addresses (VA) 6th Virtual address of a storage segment table pointer (SSTP) 7th A logical interrupt service number (LISN)

In at least one embodiment, the hypervisor verifies 1796 when receiving a hypervisor call that the operating system 1795 is registered and has the authority to use the graphics accelerator 1746 got. In at least one embodiment, the hypervisor sets 1796 then the process element 1783 into a list linked to the process element for a corresponding type of graphics accelerator 1746 one. In at least one embodiment, a process element can include the information shown in Table 4. Table 4 - Process Element Information Element no. description 1 A work descriptor (WD) 2 An Authority Mask Register (AMR) value (possibly masked). 3 A context save / restore area pointer (CSRP) for effective addresses (EA) 4th A process ID (PID) and optionally a thread ID (TID) 5 An accelerator usage record pointer (AURP) for virtual addresses (VA) 6th Virtual address of a memory segment table pointer (SSTP) 7th A Logical Interrupt Service Number (LISN) 8th Interrupt vector table derived from hypervisor call parameters 9 A value of the state register (SR) 10 A logical partition ID (LPID) 11th A Hypervisor Accelerator Usage Record Pointer for Real Addresses (RA) 12th Storage Descriptor Register (SDR)

In at least one embodiment, the hypervisor initializes a plurality of registers 1745 the accelerator integration disk 1790 .

As in 17F illustrates, in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space that is used to access the physical processor memory 1701 (1) -1701 (N) and the GPU memory 1720 (1) -1720 (N) is used. In this implementation, operations take advantage of the GPUs 1710 (1) -1710 (N) are executed, an identical virtual / effective memory address space for access to the processor memory 1701 (1) -1701 (M) and vice versa, which simplifies programmability. In at least one embodiment, a first portion of a virtual / effective address space becomes processor memory 1701 (1) allocated, a second section to the second processor memory 1701 (N) , a third section is the GPU memory 1720 (1) and so forth. In at least one embodiment, this creates an entire virtual / effective memory space (sometimes referred to as the effective address space) over each of the processor memories 1701 and GPU memory 1720 distributed, which allows any processor or GPU to access any physical memory with a virtual address mapped to that memory.

In at least one embodiment, the distortion / coherence management circuit provides 1794A - 1794E within one or more MMUs 1739A - 1739E the cache coherence between caches of one or more host processors (e.g. 1705 ) and GPUs 1710 safe and implements warping techniques that specify physical memories in which certain types of data should be stored. Although, in at least one embodiment, multiple instances of the distortion / coherence management circuitry 1794A - 1794E in 17F As illustrated, the distortion / coherence circuitry may be within an MMU of one or more host processors 1705 and / or within the accelerator integration circuit 1736 be implemented.

One embodiment enables GPU memory 1720 mapped as part of system memory and accessed using shared virtual memory (SVM) technology without, however, suffering the computational penalties associated with full system cache coherence. In at least one embodiment, that provides a capability on GPU memory 1720 accessed as system memory with no onerous cache coherency overhead, provides a beneficial operating environment for GPU offload. In at least one embodiment, this arrangement enables the host processor software 1705 without setting up operands and accessing calculation results without the overhead of traditional I / O DMA data copies. In at least one embodiment, such traditional copies involve driver calls, interrupts, and memory mapped I / O accesses (MMIO accesses), all of which are inefficient in terms of simple memory accesses. In at least one embodiment, an ability without cache coherency overheads on GPU memory can be provided 1720 access can be critical to the execution time of an offloaded calculation. In cases with significant streaming write memory traffic, the Example of cache coherence overhead is an effective write bandwidth used by a GPU 1710 is seen to reduce significantly in at least one embodiment. In at least one embodiment, operand setup efficiency, results access efficiency, and GPU computation efficiency may play a role in determining the effectiveness of a GPU offload.

In at least one embodiment, the selection of GPU distortion and host processor distortion is driven by a distortion tracker data structure. In at least one embodiment, for example, a distortion table can be used, which can be a page-granular structure (e.g. controlled with a granularity of a memory page) that includes 1 or 2 bits per GPU-bound memory page. In at least one embodiment, a warp table can be stored in a stolen memory area of one or more GPU memories 1720 can be implemented with or without a warp cache in a GPU 1710 (e.g. to temporarily store frequently / recently used entries in a distortion table). Alternatively, in at least one embodiment, an entire warpage table can be kept within a GPU.

In at least one embodiment, prior to the actual access to a GPU memory, a distortion table entry is accessed, which occurs with each access to the GPU-bound memory 1720 is associated, thereby causing the following operations. In at least one embodiment, local requests are made by a GPU 1710 that find their side in the GPU distortion, directly to a corresponding GPU memory 1720 forwarded. In at least one embodiment, local requests from a GPU, which find their side in the host distortion, are made to the processor 1705 forwarded (e.g., over a high speed link as described herein). In at least one embodiment, requests from the processor include 1705 finding a requested page in the host processor skew, issue a request like a normal read of memory. Alternatively, requests directed to a GPU warp side can be made to a GPU 1710 to get redirected. In at least one embodiment, a GPU can then convert a page to host processor distortion if it is not currently using a page. In at least one embodiment, a page distortion state may be changed by either a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a purely hardware-based mechanism.

A mechanism for changing the distortion state, in at least one embodiment, employs an API call (e.g. OpenCL), which in turn calls the device driver of a GPU, which in turn sends a message to a GPU (or queues a command descriptor), which instructs them to change a warp state and perform a cache flush operation on a host on some transitions. In at least one embodiment, a cache flush operation is used for a transition from warping the host processor 1705 used to distort the GPU, but not for an opposite transition.

In one embodiment, cache coherency is maintained by causing GPU warped pages to be processed by the host processor 1705 temporarily cannot be cached. To access these pages, in at least one embodiment, the processor 1705 Access from the GPU 1710 request that may or may not grant access immediately. To communication between the processor 1705 and the GPU 1710 Therefore, in at least one embodiment, it is advantageous to ensure that GPU-warped pages are those generated by a GPU but not the host processor 1705 , are required and vice versa.

The hardware structure (s) 915 are used to perform one or more embodiments. Details regarding a hardware structure (s) 915 can be used herein in conjunction with 9A and / or 9B may be provided.

18th illustrates example integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

18th Figure 3 is a block diagram showing an exemplary integrated circuit 1800 as a system on a chip that can be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, the integrated circuit 1800 one or more application processor (s) 1805 (e.g. CPUs), at least one graphics processor 1810 and it can also have an image processor 1815 and / or a video processor 1820 any of which can be a modular IP core. In at least one embodiment, the integrated circuit includes 1800 Peripheral or bus logic that a USB controller 1825 , a UART controller 1830 , an SPI / SDIO controller 1835 and an I ² 2S / I ² 2C controller 1840 contains. In at least one embodiment, the integrated circuit can 1800 a display device 1845 involve being connected to one or more of a high definition multimedia interface (HDMI) controller 1850 and a Mobile Industry Processor Interface (MIPI) display interface 1855 is coupled. In at least one embodiment, the storage may be by a flash memory subsystem 1860 may be provided that includes flash memory and a flash memory controller. In at least one embodiment, a memory interface can be via a memory controller 1865 be provided for accessing SDRAM or SRAM storage devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1870 .

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the inference and / or training logic 915 in the integrated circuit 1800 can be used for inference or prediction operations at least in part on the basis of weighting parameters calculated using training operations for neural networks, functions and / or architectures of neural networks or use cases described herein for neural networks.

19A-19B 10 illustrate example integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

19A-19B are block diagrams illustrating example graphics processors for use within a SoC in accordance with embodiments described herein. 19A illustrates an exemplary graphics processor 1910 an integrated circuit as a system on a chip, which can be manufactured using one or more IP cores, according to at least one embodiment. 19B illustrates an additional exemplary graphics processor 1940 an integrated circuit as a system on a chip, which can be manufactured using one or more IP cores, according to at least one embodiment. In at least one embodiment, the graphics processor is 1910 out 19A a low-performance graphics processor core. In at least one embodiment, the graphics processor is 1940 out 19B a graphics processor core with higher computing power. In at least one embodiment, each of the graphics processors 1910 , 1940 a variant of the graphics processor 1810 out 18th being.

In at least one embodiment, includes the graphics processor 1910 a vertex processor 1905 and one or more fragment processor (s) 1915A-1915N (e.g. 1915A , 1915B , 1915C , 1915D until 1915N-1 and 1915N ). In at least one embodiment, the graphics processor 1910 execute different shader programs using separate logic so that the vertex processor 1905 is optimized for executing operations for vertex shader programs while one or more fragment processor (s) 1915A-1915N Perform shading operations on fragments (e.g. pixels) for fragment or pixel shader programs. In at least one embodiment, the vertex processor performs 1905 performs a vertex processing stage of a 3-D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the fragment processor (s) use 1915A-1915N Primitive and vertex data processed by the vertex processor 1905 to produce an image memory which is displayed on a display device. In at least one embodiment, the fragment processor (s) are 1915A-1915N optimized for running fragment shader programs such as those provided in an OpenGL API that can be used to perform operations similar to a pixel shader program such as those provided in a Direct 3D API.

In at least one embodiment, includes the graphics processor 1910 additional one or more memory management units (MMUs) 1920A-1920B , Cache (s) 1925A-1925B and circuit interconnection (s) 1930A-1930B . In at least one embodiment, one or more MMU (s) 1920A-1920B the mapping from virtual to physical addresses for the graphics processor 1910 ready, including for the vertex processor 1905 and / or the fragment processor (s) 1915A-1915N that can reference vertex or image / texture data stored in memory, in addition to that in one or more cache (s) 1925A-1925B stored vertex or image / texture data. In at least one embodiment, one or more MMU (s) 1920A-1920B synchronized with other MMUs within a system, including one or more MMUs connected to one or more application processor (s) 1805 , Image processors 1815 and / or video processors 1820 out 18th are associated so that each processor 1805-1820 can participate in a shared or uniform virtual storage system. In at least one embodiment, one or more circuit interconnection (s) enable 1930A-1930B the graphics processor 1910 to form interfaces with other IP cores within the SoC either via an internal bus of the SoC or via a direct connection.

In at least one embodiment, includes the graphics processor 1940 one or more shader core (s) 1955A-1955N (e.g. 1955A , 1955B , 1955C , 1955D , 1955E , 1955F until 1955N-1 and 1955N ), as in 19B demonstrated what provides a unified core shader architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or computational shaders. In at least one embodiment, a number of the shader cores can vary. In at least one embodiment, includes the graphics processor 1940 an intermediate core task manager 1945 that acts as a thread arbiter to execute threads of one or more shader cores 1955A-1955N to be allocated, as well as a tiling unit 1958 for speeding up tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in the image space, for example to take advantage of the local spatial coherence within a scene or to optimize the use of internal caches.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the inference and / or training logic 915 in the integrated circuit 19A and or 19B can be used for inference or prediction operations at least in part on the basis of weighting parameters calculated using training operations for neural networks, functions and / or architectures of neural networks or use cases described herein for neural networks.

20A-20B illustrate additional example graphics processor logic in accordance with embodiments described herein. 20A illustrates a graphics core 2000 which, in at least one embodiment, is within the graphics processor 1810 out 18th can be included and, in at least one embodiment, a uniform shader core 1955A-1955N as in 19B can be. 20B illustrates a highly parallel general-purpose graphics processing unit ("GPGPU") 2030 , which is suitable in at least one embodiment for use on a multi-chip module.

In at least one embodiment, the graphics core includes 2000 a shared instruction cache 2002 , a texture unit 2018 and a cache / shared memory 2020 that are the execution resources within the graphics core 2000 are common. In at least one embodiment, the graphics core 2000 several slices 2001A-2001N or one partition for each core and a graphics processor can contain multiple instances of the graphics core 2000 include. In at least one embodiment, the disks 2001A-2001N Support logic that includes a local instruction cache 2004A-2004N , a thread scheduler 2006A-2006N , a thread arbiter 2008A-2008N and a set of registers 2010A-2010N contains. In at least one embodiment, the disks 2001A-2001N a set of additional function units (AFUs 2012A-2012N ), Floating-point units (FPUs 2014A-2014N) , arithmetic-logical units for integers (ALUs 2016A-2016N ), Address computational units (ACUs 2013A-2013N ), Double-precision floating-point units (DPFPUs 2015A-2015N ) and matrix processing units (MPUs 2017A-2017N ) include.

In at least one embodiment, the FPUs 2014A-2014N Perform single-precision (32-bit) and half-precision (16-bit) floating point operations while the DPFPUs 2015A-2015N Perform double-precision (64-bit) floating point operations. In at least one embodiment, the ALUs 2016A-2016N Perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and be configured for mixed precision operations. In at least one embodiment can use the MPUs 2017A-2017N also be configured for mixed precision matrix operations, including floating point and 8-bit half precision integer operations. In at least one embodiment, the MPUs 2017A-2017N perform a variety of matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix to matrix multiplication (GEMM). In at least one embodiment, the AFUs 2012A-2012N Perform additional logical operations that are not supported by floating point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the inference and / or training logic 915 in the graphics core 2000 can be used for inference or prediction operations at least in part on the basis of weighting parameters calculated using training operations for neural networks, functions and / or architectures of neural networks or use cases described herein for neural networks.

20B Illustrates, in at least one embodiment, a General Purpose Processing Unit (GPGPU) 2030 which can be configured so that highly parallel arithmetic operations can be performed by an array of graphics processing units. In at least one embodiment, the GPGPU 2030 directly with other instances of the GPGPU 2030 be linked to create a multi-GPU cluster to improve training speed for deep neural networks. In at least one embodiment, the GPGPU includes 2030 a host interface 2032 to enable connection to a host processor. In at least one embodiment, is the host interface 2032 a PCI-Express interface. In at least one embodiment, the host interface can 2032 be a provider-specific communication interface or communication structure. In at least one embodiment, the GPGPU receives 2030 Commands from a host processor and it uses a global scheduler 2034 to send threads of execution associated with these commands to a set of compute clusters 2036A-2036H to distribute. In at least one embodiment, the computing clusters use 2036A-2036H a cache memory 2038 together. In at least one embodiment, the cache memory 2038 as a higher-level cache for cache memory within the computing cluster 2036A-2036H serve.

In at least one embodiment, the GPGPU includes 2030 Storage 2044A-2044B that has a set of memory controls 2042A-2042B to the computing cluster 2036A-2036H is coupled. In at least one embodiment, the memory 2044A-2044B include various types of storage devices including dynamic random access memory (DRAM) or graphics random access memory such as synchronous graphics random access memory (SGRAM) including graphics double data rate (GDDR) memory.

In at least one embodiment, the computing clusters include 2036A-2036H a set of graphics cores each, such as the graphics core 2000 out 20A , which may include several types of integer and floating point logic units that can perform arithmetic operations to a range of accuracies, including those suitable for machine learning calculations. For example, in at least one embodiment, at least a subset of the floating point units in each of the compute clusters 2036A-2036H be configured to perform 16-bit or 32-bit floating point operations, while another subset of the floating point units can be configured to perform 64-bit floating point operations.

In at least one embodiment, multiple instances of the GPGPU 2030 be configured to work as a compute cluster. In at least one embodiment, the communication carried out by the compute clusters varies 2036A-2036H is used for synchronization and data exchange, depending on the embodiment. In at least one embodiment, several instances of the GPGPU are communicating 2030 via the host interface 2032 . In at least one embodiment, the GPGPU includes 2030 an I / O hub 2039 who owns the GPGPU 2030 with a GPU link 2040 couples that have a direct connection to other instances of the GPGPU 2030 enables. In at least one embodiment, the GPU link is 2040 Coupled to a dedicated GPU-to-GPU bridge, communication and synchronization between multiple instances of the GPGPU 2030 enables. In at least one embodiment, the GPU link is 2040 coupled to high speed interconnection to transmit and receive data to and from other GPGPUs or parallel processors. In at least one embodiment, there are multiple instances of the GPGPU 2030 in separate data processing systems and they communicate over a network device to which the host interface 2032 can be accessed. In at least one embodiment, the GPU may link 2040 be configured to connect to a host processor in addition to or as an alternative to the host interface 2032 is made possible.

In at least one embodiment, the GPGPU 2030 be configured to train neural networks. In at least one embodiment, the GPGPU 2030 can be used within an inference platform. In at least one embodiment in which the GPGPU 2030 is used for inference, the GPGPU 2030 fewer compute clusters 2036A-2036H include than in the case that the GPGPU 2030 is used to train a neural network. In at least one embodiment, the memory 2044A-2044B Associated storage technology distinguish between inference and training configurations, the training configurations being dedicated to storage technologies with higher bandwidth. In at least one embodiment, an inference configuration of the GPGPU 2030 Support inference-specific instructions. In at least one embodiment, an inference configuration can, for example, provide support for one or more 8-bit integer scalar product instructions that can be used during the inference operations for deployed neural networks.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the inference and / or training logic 915 in the GPGPU 2030 can be used for inference or prediction operations at least in part on the basis of weighting parameters calculated using training operations for neural networks, functions and / or architectures of neural networks or use cases described herein for neural networks.

21 Figure 3 is a block diagram showing a computing system 2100 illustrated according to at least one embodiment. In at least one embodiment, the computing system includes 2100 a processing subsystem 2101 that has one or more processor (s) 2102 and a system memory 2104 that communicate over an interconnection path that includes a storage hub 2105 may include. In at least one embodiment, the storage hub 2105 be a separate component within a chipset component or in one or more processor (s) 2102 be integrated. In at least one embodiment, the storage hub is 2105 via a communication link 2106 with an I / O subsystem 2111 coupled. In at least one embodiment, the I / O subsystem includes 2111 an I / O hub 2107 who made it to the computing system 2100 can enable inputs from one or more input device (s) 2108 to recieve. In at least one embodiment, the I / O hub can 2107 there is a display controller, which is in one or more processor (s) 2102 may be included, enable one or more display device (s) 2110A Provide expenses. In at least one embodiment, one or more can be connected to the I / O hub 2107 coupled display device (s) 2110A include a local, internal, or embedded display device.

In at least one embodiment, the processing subsystem includes 2101 one or more parallel processor (s) 2112 over a bus or other communication link 2113 to the storage hub 2105 are coupled. In at least one embodiment, the communication link can 2113 use any of any number of standards-based communication link technologies or protocols, such as, but not limited to, PCI Express or a vendor-specific communication interface or communication structure. In at least one embodiment, one or more parallel processor (s) 2112 a computationally focused parallel or vector processing system that may include a large number of processing cores and / or processing clusters, such as a many-integrated core (MIC) processor. In at least one embodiment, some or all of the parallel processor (s) 2112 a graphics processing subsystem that sends pixels to one or more display devices 2110A that can output via the I / O hub 2107 are coupled. In at least one embodiment, the parallel processor (s) can 2112 also contain a display controller and a display interface (not shown) for a direct connection to one or more display device (s) 2110B to enable.

In at least one embodiment, a system storage device 2114 with the I / O hub 2107 be connected to a storage mechanism for the computing system 2100 provide. In at least one embodiment, an I / O switch 2116 used to provide an interface mechanism that allows connections between the I / O hub 2107 and other components, such as an AC adapter 2118 and / or a wireless network adapter 2119 that can be integrated into a platform, as well as various other devices that can be connected via one or more expansion device (s) 2120 can be added. In at least one embodiment, the network adapter 2118 one Ethernet adapter or other wired network adapter. In at least one embodiment, the wireless network adapter 2119 include one or more Wi-Fi, Bluetooth, near field communication (NFC), or other network device that includes one or more wireless radios.

In at least one embodiment, the computing system can 2100 include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and the like that also connect to the I / O hub 2107 can be connected. In at least one embodiment, the communication paths that various components in 21 interconnect, implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect) based protocols (e.g. PCI-Express) or other bus or point-to-point communication interfaces and / or protocol (s) such as NV-Link high-speed interconnection, or interconnection protocols.

In at least one embodiment, the parallel processor (s) include 2112 Circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU). In at least one embodiment, the parallel processor (s) include 2112 Circuits optimized for general purpose processing. In at least one embodiment, the components of the computing system 2100 be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, the parallel processor (s) 2112 , the storage hub 2105 , the processor (s) 2102 and the I / O hub 2107 be integrated into an integrated circuit as a system on a chip (SoC). In at least one embodiment, the components of the computing system 2100 be integrated into a single package to form a system in package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 2100 be integrated in a multi-chip module (multi-chip module - MCM), which can be interconnected with other multi-chip modules to form a modular computing system.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the inference and / or training logic 915 in the system of FIG. 2100 can be used for inference or prediction operations based at least in part on weighting parameters calculated using training operations for neural networks, functions and / or architectures of neural networks or use cases for neural networks described herein.

PROCESSORS

22A illustrates a parallel processor 2200 according to at least one embodiment. In at least one embodiment, various components of the parallel processor 2200 can be implemented using one or more integrated circuits, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor is 2200 a variant of one or more parallel processor (s) 2112 , in the 21 are shown according to an exemplary embodiment.

In at least one embodiment, the parallel processor includes 2200 a parallel processing unit 2202 . In at least one embodiment, the parallel processing unit includes 2202 an I / O base 2204 that enables communication with other devices, including other instances of the parallel processing unit 2202 . In at least one embodiment, the I / O device can 2204 be connected directly to other devices. In at least one embodiment, the I / O device is 2204 using a hub or switch interface, such as a storage hub 2205 connected to other devices. In at least one embodiment, connections form between the storage hub 2205 and the I / O base 2204 a communication link 2213 . In at least one embodiment, the I / O device is 2204 with a host interface 2206 and a memory matrix 2216 connected to the host interface 2206 Receives commands directed to performing processing operations and the storage crossbar 2216 Receives commands directed to performing memory operations.

In at least one embodiment, if the host interface 2206 a command buffer via the I / O base 2204 receives that host interface 2206 Working operations for performing these Commands to a front end 2208 judge. In at least one embodiment, the front end is 2208 with a planner 2210 coupled that is configured to send commands or other work items to a processing cluster array 2212 distributed. In at least one embodiment, the planner provides 2210 make sure the processing cluster array 2212 is properly configured and in a valid state prior to assigning tasks to a cluster of a processing cluster array 2212 be distributed. In at least one embodiment, the planner is 2210 implemented via firmware logic that runs on a microcontroller. In at least one embodiment, the microcontroller is an implemented scheduler 2210 configurable to perform complex planning and work-sharing operations with coarse and fine granularity, enabling rapid preemption and context switching of threads running on the processing array 2212 are executed. In at least one embodiment, the host software may schedule workloads on the processing cluster array 2212 via one of several graphics processing paths. In at least one embodiment, the workloads can then be programmed through the logic of the planner 2210 inside a microcontroller that controls the planner 2210 automatically to the processing array cluster 2212 be distributed.

In at least one embodiment, the processing cluster array 2212 contain up to "N" processing clusters (e.g. cluster 2214A , Cluster 2214B to cluster 2214N) , where "N" represents a positive integer (which may be a different integer "N" than used in other figures). In at least one embodiment, each cluster can 2214A-2214N of the processing cluster array 2212 running a large number of concurrent threads. In at least one embodiment, the planner can 2210 the clusters 2214A-2214N of the processing cluster array 2212 Allocate work using different planning and / or work distribution algorithms that may vary depending on the workload that will arise for each type of program or computation. In at least one embodiment, the planning can be done dynamically by the planner 2210 are handled or partially supported by compiler logic during compilation of the program logic necessary for execution by the processing cluster array 2212 configured. In at least one embodiment, different clusters 2214A-2214N of the processing cluster array 2212 assigned to process different types of programs or to perform different types of calculations.

In at least one embodiment, the processing cluster array 2212 Be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster is array 2212 configured to perform general-purpose parallel computation operations. In at least one embodiment, the processing cluster array 2212 for example, include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

In at least one embodiment, the processing cluster is array 2212 configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2212 include additional logic to aid in performing such graphics processing operations including, but not limited to, texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2212 Be configured to run graphics processing-related shader programs such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2202 Submit data from system memory via I / O base 2204 for processing. In at least one embodiment, the transmitted data can be stored in an on-chip memory (e.g. the parallel processor memory 2222 ) can be saved during processing and then written back to system memory.

When the parallel processing unit 2202 is used to perform graphics processing, the planner can 2210 In at least one embodiment, it can be configured to split a processing workload into tasks of approximately equal size in order to better distribute graphics processing operations across multiple clusters 2214A-2214N of the processing cluster array 2212 to enable. In at least one embodiment, portions of the processing cluster array 2212 be configured to perform different types of processing. For example, in at least one embodiment, a first section can be configured to perform vertex shading and topology generation, a second section can be configured to perform tessellation and geometry shading, and a third section can be configured to that it performs pixel shading or other screen space operations to produce a rendered image for display. In at least one embodiment, can Intermediate data passed by one or more of the clusters 2214A-2214N are produced, stored in buffers to allow the intermediate data for further processing between the clusters 2214A-2214N be transmitted.

In at least one embodiment, the processing cluster array 2212 processing tasks to be carried out via the scheduler 2210 received by the frontend 2208 Receives commands that define processing tasks. In at least one embodiment, the processing tasks can include indexes of the data to be processed, e.g. B. surface (patch) data, primitive data, vertex data and / or pixel data, as well as state parameters and commands that define how the data should be processed (e.g. which program should be executed). In at least one embodiment, the planner can 2210 be configured in such a way that it retrieves the indices corresponding to the tasks, or it can use indices from the frontend 2208 receive. In at least one embodiment, the front end can 2208 be configured to ensure that the processing cluster array 2212 configured to a valid state before a workload specified by incoming command buffers (e.g. batch buffers, push buffers, etc.) is initiated.

In at least one embodiment, each of one or more instances of the parallel processing unit 2202 with a parallel processor memory 2222 be coupled. In at least one embodiment, the parallel processor memory 2222 via the storage matrix 2216 the memory requests are accessed from the processing cluster array 2212 as well as from the I / O base 2204 can receive. In at least one embodiment, the storage matrix can 2216 via a memory interface 2218 on the parallel processor memory 2222 access. In at least one embodiment, the memory interface can 2218 multiple partition units (e.g. partition unit 2220A , Partition unit 2220B to partition unit 2220N) each to a section (e.g. memory unit) of the parallel processor memory 2222 can be coupled. In at least one embodiment, a number of the partition units 2220A-2220N configured to be equal to a number of storage units such that a first partition unit 2220A a corresponding first storage unit 2224A has a second partition unit 2220B a corresponding storage unit 2224B and an N-th partition unit 2220N a corresponding N-th storage unit 2224N having. In at least one embodiment, a number of the partition units 2220A-2220N not be equal to a number of the storage units.

In at least one embodiment, the storage units 2224A-2224N include various types of storage devices including dynamic random access memory (DRAM) or graphics random access memory such as synchronous graphics random access memory (SGRAM) including graphics double data rate (GDDR) memory. In at least one embodiment, the storage units 2224A-2224N also include 3D stacks, including, but not limited to, high bandwidth memory (HBM). In at least one embodiment, rendering targets, such as image buffers or texture maps, can be accessed via the storage units 2224A-2224N be saved away what it is the partition units 2220A-2220N allows sections of each rendering target to be written in parallel using the available bandwidth of the parallel processor memory 2222 to use efficiently. In at least one embodiment, a local instance of the parallel processor memory 2222 in favor of a uniform memory design that uses system memory in conjunction with local cache memory.

In at least one embodiment, any of the clusters 2214A-2214N of the processing cluster array 2212 Process data residing in any of the storage devices 2224A-2224N within the parallel processor memory 2222 to be written. In at least one embodiment, the storage matrix can 2216 be configured to have output from each cluster 2214A-2214N to any partition unit 2220A-2220N or to another cluster 2214A-2214N that can perform additional processing on an output. In at least one embodiment, each cluster can 2214A-2214N through the storage matrix 2216 with the memory interface 2218 communicate to read from or write to various external storage devices. In at least one embodiment, the storage crossbar has 2216 a connection to the storage interface 2218 to communicate with I / O base 2204 and connect to a local instance of parallel processor memory 2222 what it is the processing units within the different processing clusters 2214A-2214N allows to communicate with system memory or other memory that is not local to the parallel processing unit 2202 is. In at least one embodiment, the storage matrix can 2216 Use virtual channels to flow traffic between clusters 2214A-2214N and partition units 2220A-2220N to separate.

In at least one embodiment, several instances of the parallel processing unit 2202 be provided on a single expansion card or multiple expansion cards be interconnected. In at least one embodiment, different instances of the parallel processing unit 2202 be configured to work together even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2202 Include floating point units with higher precision with respect to other instances. In at least one embodiment, systems that include one or more instances of the parallel processing unit 2202 or the parallel processor 2200 may be implemented in a variety of configurations and form factors including, but not limited to, desktop, laptop, or portable personal computers, servers, workstations, game consoles, and / or embedded systems.

22B Fig. 3 is a block diagram of a partition unit 2220 according to at least one embodiment. In at least one embodiment, the partition unit is 2220 an instance of one of the partition units 2220A-2220N out 22A . In at least one embodiment, the partition unit includes 2220 an L2 cache 2221 , an image storage interface 2225 and a ROP 2226 (raster operations unit). In at least one embodiment, the L2 cache is 2221 a read / write cache configured to perform load and save operations from the storage crossbar 2216 and the ROP 2226 be received. In at least one embodiment, read errors and urgent write back requests are identified by the L2 cache 2221 to the image storage interface 2225 issued for processing. In at least one embodiment, updates can also be made via the image storage interface 2225 sent to an image buffer for processing. In at least one embodiment, the image storage interface forms 2225 an interface with one of the storage units in the parallel processor memory, such as the storage units 2224A-2224N out 22nd (e.g. within the parallel processor memory 2222 ).

In at least one embodiment, the ROP is 2226 a processing unit that performs raster operations such as stencil, z-test, blending, etc. In at least one embodiment, the ROP 2226 then processed graphics data which is stored in graphics memory. In at least one embodiment, the ROP includes 2226 Compression logic to compress depth or color data written to memory and to decompress depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic using one or more of a plurality of compression algorithms. In at least one embodiment, a type of compression can be implemented by the ROP 2226 will vary based on statistical properties of the data to be compressed. For example, in at least one embodiment, delta color compression is performed on depth and color data on a tile basis.

In at least one embodiment, the ROP is 2226 within each processing cluster (e.g. cluster 2214A-2214N out 22A) instead of within the partition unit 2220 contain. In at least one embodiment, read and write requests for pixel data rather than pixel fragment data are made through the storage crossbar 2216 transfer. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of the one or more display device (s) 2110 out 21 , for further processing by the processor (s) 2102 routed or for further processing by one of the processing entities within the parallel processor 2200 out 22A be routed.

22C Figure 3 is a block diagram of a processing cluster 2214 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is an instance of one of the processing clusters 2214A-2214N out 22A . In at least one embodiment, the processing cluster 2214 be configured to execute many threads in parallel, where "thread" refers to an instance of a specific program that is executed on a specific set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuing techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) techniques are used to support the parallel execution of large numbers of generally synchronized threads using a common instruction unit configured to carry instructions to a set of processing engines within each of the processing clusters.

In at least one embodiment, the operation of the processing cluster 2214 through a pipeline manager 2232 which distributes the processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager receives 2232 Instructions from the planner 2210 out 22A and manages the execution of these instructions via a graphics multiprocessor 2234 and / or a texture unit 2236 . In at least one embodiment, the graphics processor is multiprocessor 2234 an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, different types of SIMT parallel processors with different architectures can be used within the processing cluster 2214 be included. In at least one embodiment, one or more instances of the graphics multiprocessor 2234 within a processing cluster 2214 be included. In at least one embodiment, the graphics multiprocessor 2234 Process data and a data matrix 2240 can be used to distribute processed data to one of several possible destinations, including other shader units. In at least one embodiment, the pipeline manager 2232 facilitate the distribution of processed data by setting targets for processed data to be distributed via the data matrix 2240 pretends.

In at least one embodiment, each graphics multiprocessor can 2234 within the processing cluster 2214 contain an identical set of functional execution logic (e.g. arithmetic logic units, load storage units, etc.). In at least one embodiment, functional execution logic may be configured in a pipelined manner, wherein new instructions can be issued before previous instructions are completed. In at least one embodiment, the functional execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, bit shifting, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware can be used to perform different operations, and any combination of functional units can be present.

In at least one embodiment, they provide the processing cluster 2214 In at least one embodiment, a set of threads executed by a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program on different input data. In at least one embodiment, each thread within a thread group of a different processing engine within a graphics multiprocessor 2234 be assigned. In at least one embodiment, a thread group can contain fewer threads than a number of processing engines within the graphics multiprocessor 2234 . When a thread group contains fewer threads than a number of processing engines, in at least one embodiment one or more of the processing engines can be inactive during the cycles in which this thread group is processed. In at least one embodiment, a thread group can also contain more threads than a number of processing engines within the graphics multiprocessor 2234 . When a thread group has more threads than a number of processing engines within the graphics multiprocessor 2234 includes, the processing can be performed over successive clock cycles in at least one embodiment. In at least one embodiment, several thread groups can run concurrently on a graphics multiprocessor 2234 are executed.

In at least one embodiment, the graphics include multiprocessor 2234 an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2234 do without an internal cache and use a cache memory (e.g. L1 cache 2248 ) within the processing cluster 2214 use. In at least one embodiment, each graphics processor has a multiprocessor 2234 also access to L2 caches within partition units (e.g. partition units 2220A-2220N out 22A) by all processing clusters 2214 shared and used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2234 also access global off-chip memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory associated with the parallel processing unit 2202 external, can be used as global storage. In at least one embodiment, the processing cluster includes 2214 multiple instances of the graphics multiprocessor 2234 and it can share common instructions and data held in the L1 cache 2248 can be stored.

In at least one embodiment, each processing cluster 2214 an MMU 2245 (Storage Management Unit) configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2245 within the memory interface 2218 out 22A condition. In at least one embodiment, the MMU includes 2245 a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile, and optionally a cache line index. In at least one embodiment, the MMU 2245 Contain address translation buffers (TLB) or caches that are located within the graphics multiprocessor 2234 or L1 cache 2248 or processing clusters 2214 can be located. In at least one embodiment, a physical address is processed to distribute the surface data access locally in order to enable efficient request interleaving between the partition units. In at least one embodiment, a cache line index can be used to determine whether a request for a cache line is a hit or an error.

In at least one embodiment, a processing cluster 2214 be configured so that each graphics multiprocessor 2234 to a texture unit 2236 is coupled to perform texture mapping operations, e.g. For determining texture sample positions, reading texture data and filtering texture data. In at least one embodiment, the texture data is obtained from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2234 read and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, there are each graphics multiprocessor 2234 processed tasks to the data matrix 2240 off to a processed task to another processing cluster 2214 for further processing or to provide a processed task via the memory matrix 2216 store in L2 cache, parallel processor local memory, or system memory. In at least one embodiment, a preROP 2242 (Pre-raster operation unit) configured to receive data from the graphics multiprocessor 2234 receives and routes data to ROP units that may reside in the partition units described herein (e.g. partition units 2220A-2220N out 22A) . In at least one embodiment, the preROP unit 2242 Perform optimizations for color mixing, organizing pixel color data, and performing address translations.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the inference and / or training logic 915 in the graphics processing cluster 2214 can be used for inference or prediction operations at least in part on the basis of weighting parameters calculated using training operations for neural networks, functions and / or architectures of neural networks or use cases described herein for neural networks.

22D shows a graphics multiprocessor 2234 according to at least one embodiment. In at least one embodiment, the graphics processor is multiprocessor 2234 with the pipeline manager 2232 of the processing cluster 2214 coupled. In at least one embodiment, the graphics multiprocessor 2234 an execution pipeline containing an instruction cache 2252 , an instruction unit 2254 , an address mapping unit 2256 , a register bank 2258 , one or more cores 2262 a universal graphics processing unit (GPGPU) and one or more load / store units 2266 includes, but is not limited to. In at least one embodiment, the are GPGPU cores 2262 and the load / store units 2266 via a memory and cache interconnection 2268 with the cache memory 2272 and shared storage 2270 coupled.

In at least one embodiment, the instruction cache receives 2252 a stream of instructions to be executed from the pipeline manager 2232 . In at least one embodiment, the instructions are in the instruction cache 2252 cached and by an instruction unit 2254 assigned for execution. In at least one embodiment, the instruction unit 2254 Assign instructions as thread groups (e.g. warps), with each thread belonging to the thread group of a different execution unit within the GPGPU cores 2262 is assigned. In at least one embodiment, an instruction can access any of a local, shared, or global address space by specifying an address within a uniform address space. In at least one embodiment, the address mapping unit 2256 can be used to translate addresses in a uniform address space into a unique memory address, to which the load / store units 2266 can be accessed.

In at least one embodiment, the register bank provides 2258 a set of registers for functional units of the graphics multiprocessor 2234 ready. In at least one embodiment, the Register bank 2258 a temporary data memory for operands that are linked with data paths of functional units (e.g. GPGPU cores 2262 , Load / storage units 2266 ) of the graphics multiprocessor 2234 are connected. In at least one embodiment, the register bank is 2258 divided between the individual functional units in such a way that each functional unit has a dedicated section of the register bank 2258 is assigned. In at least one embodiment, the register bank is 2258 divided into different warps, which are generated by the graphics multiprocessor 2234 are executed.

In at least one embodiment, the GPGPU cores 2262 each contain floating point units (FPUs) and / or arithmetic-logic units (ALUs) for integers, which are used to execute instructions of the graphics multiprocessor 2234 be used. In at least one embodiment, the GPGPU cores 2262 have a similar architecture or differ in terms of architecture. In at least one embodiment, a first portion includes the GPGPU cores 2262 a single precision FPU and an integer ALU, while a second section of the GPGPU cores includes a double precision FPU. In at least one embodiment, FPUs can implement the IEEE 754-2008 standard for floating point arithmetic or enable floating point arithmetic with variable precision. In at least one embodiment, the graphics multiprocessor 2234 additionally contain one or more fixed function or special function units in order to carry out specific functions, such as operations for copying rectangles or pixel blending. In at least one embodiment, one or more of the GPGPU cores 2262 also contain fixed or special function logic.

In at least one embodiment, the include GPGPU cores 2262 SIMD logic capable of executing a single instruction on multiple data records. In at least one embodiment, the GPGPU cores 2262 Physically execute SIMD4, SIMD8 and SIMD16 instructions and execute SIMD1, SIMD2 and SIMD32 instructions logically. In at least one embodiment, SIMD instructions for GPGPU cores may be generated at compile time by a shader compiler or generated automatically when executing programs written for single program multiple data (SPMD) or SIMT architectures and were compiled. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel through a single SIMD8 logic unit.

In at least one embodiment, the memory and cache interconnection is 2268 an interconnection network that includes each functional unit of the graphics multiprocessor 2234 with the register bank 2258 and shared storage 2270 connects. In at least one embodiment, the memory and cache interconnection is 2268 a crossbar interconnection that makes it the load / store unit 2266 enables load and store operations between the shared memory 2270 and the register bank 2258 to implement. In at least one embodiment, the register bank 2258 at the same frequency as the GPGPU cores 2262 work so that the data transfer between the GPGPU cores 2262 and the register bank 2258 can have very low latency. In at least one embodiment, the shared memory 2270 used to enable inter-thread communication on functional units within the graphics multiprocessor 2234 are executed. In at least one embodiment, the cache memory 2272 For example, it can be used as a data cache to temporarily store texture data between functional units and the texture unit 2236 be communicated. In at least one embodiment, the shared memory 2270 can also be used as a program-managed cache. In at least one embodiment, threads running on the GPGPU cores 2262 executed, in addition to the automatically cached data that is stored within the cache memory 2272 programmatically store data within shared memory.

In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to host / processor cores to expedite graphics operations, machine learning operations, pattern analysis operations, and various functions of a general purpose GPU (GPGPU). In at least one embodiment, a GPU may be communicatively coupled to the host processor (s) via a bus or other interconnect (e.g., a high speed interconnect such as PCIe or NVLink). In at least one embodiment, a GPU can be integrated as cores in a housing or chip and communicatively coupled to cores via an internal processor bus / an interconnection that is internal to a housing or chip. In at least one embodiment, regardless of a manner in which a GPU is connected, the processor cores can assign work to such a GPU in the form of sequences of commands that are contained in a Work descriptor are included. In at least one embodiment, this GPU then uses dedicated circuit / logic to efficiently process these commands / instructions.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the inference and / or training logic 915 in the graphics multiprocessor 2234 can be used for inference or prediction operations at least in part on the basis of weighting parameters calculated using training operations for neural networks, functions and / or architectures of neural networks or use cases described herein for neural networks.

23 illustrates a multi-GPU computing system 2300 according to at least one embodiment. In at least one embodiment, the multi-GPU computing system can 2300 a processor 2302 include that via a host interface switch 2304 to multiple universal graphics processing units (GPGPUs) 2306A-D is coupled. In at least one embodiment, the host is an interface switch 2304 a PCI Express switch device that runs the processor 2302 to a PCI-Express bus via which the processor 2302 with the GPGPUs 2306A-D can communicate. In at least one embodiment, the GPGPUs 2306A-D via a set of high-speed point-to-point GPU-to-GPU links 2316 be interconnected. In at least one embodiment, the GPU-to-GPU links are 2316 with each of the GPGPUs 2306A-D connected via a dedicated GPU link. In at least one embodiment, the P2P-GPU links enable 2316 direct communication between each of the GPGPUs 2306A-D without communication over the host interface bus 2304 is required with the processor 2302 connected is. In at least one embodiment, the GPU-to-GPU traffic goes to the P2P-GPU links 2316 the host interface bus remains 2304 for system memory access or for communicating with other instances of the multi-GPU computing system 2300 available, for example, via one or more network devices. While in at least one embodiment the GPGPUs 2306A-D with the processor 2302 via the host interface switch 2304 are connected, includes the processor 2302 in at least one embodiment, direct support for P2P-GPU links 2316 and can directly with the GPGPUs 2306A-D be connected.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the inference and / or training logic 915 in the multiple GPU computing system 2300 can be used for inference or prediction operations at least in part on the basis of weighting parameters calculated using training operations for neural networks, functions and / or architectures of neural networks or use cases described herein for neural networks.

24 Figure 3 is a block diagram of a graphics processor 2400 according to at least one embodiment. In at least one embodiment, includes the graphics processor 2400 a ring interconnection 2402 , a pipeline front end 2404 , a media engine 2437 and graphics cores 2480A-2480N . In at least one embodiment, the ring interconnection couples 2402 the graphics processor 2400 to other processing units, including other graphics processors or one or more general purpose processing cores. In at least one embodiment, the graphics processor is 2400 one of many processors integrated into a multi-core processing system.

In at least one embodiment, the graphics processor receives 2400 Batches of commands via the ring interconnection 2402 . In at least one embodiment, incoming commands are sent through a command streamer 2403 in the pipeline front end 2404 interpreted. In at least one embodiment, includes the graphics processor 2400 Scalable execution logic for performing 3D geometry processing and media processing via the graphics core (s) 2480A-2480N . In at least one embodiment, the command streamer is conducting 2403 the geometry pipeline 2436 Commands for 3D geometry processing commands too. In at least one embodiment, the command streamer is conducting 2403 for at least some media processing commands commands a video front end 2434 to that with the media engine 2437 is coupled. In at least one embodiment, the media engine includes 2437 a video quality engine (VQE) 2430 for video and image post-processing and an engine for encoding / decoding in multiple formats (multi-format encode / decode - MFX) 2433 for providing hardware-accelerated encoding and decoding of media data. In at least one embodiment create the geometry pipeline 2436 and the media engine 2437 in each case execution threads for thread execution resources, which by at least one graphics core 2480 are provided.

In at least one embodiment, includes the graphics processor 2400 scalable thread execution resources with the graphics cores 2480A-2480N (which can be modular and are sometimes referred to as core disks), each with several partial cores 2450A-50N , 2460A-2460N (sometimes referred to as core dividing disks). In at least one embodiment, the graphics processor 2400 any number of graphics cores 2480A exhibit. In at least one embodiment, includes the graphics processor 2400 a graphics core 2480A , the at least one first partial core 2450A and a second partial core 2460A having. In at least one embodiment, the graphics processor is 2400 a low-performance processor with a single sub-core (e.g. 2450A ). In at least one embodiment, includes the graphics processor 2400 multiple graphics cores 2480A-2480N each of which has a set of first partial cores 2450A-2450N and a set of second sub-cores 2460A-2460N contains. In at least one embodiment, each sub-core includes the first sub-cores 2450A-2450N at least a first set of execution units 2452A-2452N and media / texture scanners 2454A-2454N . In at least one embodiment, each sub-core includes the second sub-cores 2460A-2460N at least a second set of execution units 2462A-2462N and scanners 2464A-2464N . In at least one embodiment, the partial cores use 2450A-2450N , 2460A-2460N a set of shared resources at a time 2470A-2470N together. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the inference and / or training logic 915 in the graphics processor 2400 can be used for inference or prediction operations at least in part on the basis of weighting parameters calculated using training operations for neural networks, functions and / or architectures of neural networks or use cases described herein for neural networks.

25th Figure 3 is a block diagram showing the microarchitecture for a processor 2500 , which may include logic circuitry for performing instructions, according to at least one embodiment. In at least one embodiment, the processor can 2500 Perform instructions including x86 instructions, ARM instructions, specialized instructions for application specific integrated circuits (ASICs), etc. In at least one embodiment, the processor may 2500 Registers for storing packed data include such as 64 bit wide MMX ™ registers in microprocessors equipped with MMX technology from Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available in both integer and floating point form, can operate with packed data elements using single instruction multiple data ("SIMD") and streaming SIMD extensions - ("SSE" -) instructions go hand in hand. In at least one embodiment, 128-bit wide XMM registers relating to SSE2, SSE3, SSE4, AVX, or beyond technology (commonly referred to as "SSEx") can hold such packed data operands. In at least one embodiment, the processor can 2500 Perform instructions to speed up machine learning or deep learning algorithms, training, or inferencing.

In at least one embodiment, the processor includes 2500 an in-order front end ("front end") 2501 for fetching instructions to be executed and preparing instructions to be used later in a processor pipeline. In at least one embodiment, the front end can 2501 contain multiple units. In at least one embodiment, an instruction prefetcher calls 2526 Instructions from memory and feeds the instructions into an instruction decoder 2528 one that in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder decodes 2528 a received instruction into one or more operations called "micro-instructions" or "micro-operations" (also known as "micro-ops" or "µops") that a machine can perform. In at least one embodiment, the instruction decoder parses 2528 an instruction in an opcode and corresponding data and control fields that can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, a trace cache 2530 decoded µops in program-ordered sequences or processes in a µop queue 2534 put together for execution. When the trace cache 2530 encounters a complex instruction, in at least one embodiment, a microcode ROM 2532 the µops necessary to complete an operation are ready.

In at least one embodiment, some instructions can be converted into a single micro-op while others require multiple micro-ops to complete a full operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder can 2528 on the microcode ROM 2532 access to perform this instruction. In at least one embodiment, an instruction can be split into a small number of micro-ops for processing in the instruction decoder 2528 can be decoded. In at least one embodiment, an instruction can be stored within the microcode ROM 2532 should be saved if a series of micro-ops should be required to accomplish such an operation. In at least one embodiment, the trace cache is related 2530 to a programmable logic array ("PLA") for the entry point to determine a correct microinstruction pointer for reading microcode sequences to one or more instructions from the microcode ROM 2532 complete according to at least one embodiment. In at least one embodiment, the front end can 2501 a machine after the microcode ROM 2532 Finished sequencing micro-ops for an instruction, fetching micro-ops from the trace cache 2530 resume.

In at least one embodiment, the engine can be executed in a different order ("out-of-order engine") 2503 Prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has a number of buffers to smooth and reorder the flow of instructions to optimize computational performance as they pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine comprises 2503 an assigner / register renamer without restriction 2540 , a memory µop queue 2542 , an integer / floating point µop queue 2544 , a storage planner 2546 , a quick planner 2502 , a slow / general floating point planner ("slow / general FP planner") 2504 and a simple floating point planner ("simple FP planner") 2506 . In at least one embodiment, you'll be the quick planner 2502 , the slow / general floating point planner 2504 and the simple floating point planner 2506 here also collectively as “µop-Planner 2502 , 2504 , 2506 " designated. In at least one embodiment, the allocator / register renamer 2540 Machine buffers and resources that each µop needs for execution. In at least one embodiment, the allocator / register renamer designates 2540 logical registers into entries in a register bank. In at least one embodiment, the allocator / register renamer 2540 also add an entry for each µop in one of two µop queues, namely in the memory µop queue 2542 for memory operations and the integer / floating point µop queue 2544 for non-memory operations, before the memory scheduler 2546 and the µop planners 2502 , 2504 , 2506 . In at least one embodiment, the µop planners determine 2502 , 2504 , 2506 when a µop is ready to execute based on the readiness of its dependent input register operand sources and the availability of the execution resources that µops need to complete their operation. In at least one embodiment, the quick planner can 2502 schedule on each half of the master clock cycle, during the slow / general floating point schedule 2504 and the simple floating point planner 2506 can schedule once per main processor clock cycle. In at least one embodiment, the µop planners mediate 2502 , 2504 , 2506 Allocation ports to schedule µops for execution.

In at least one embodiment, the execution block includes 2511 an integer register bank / bypass network without restriction 2508 , a floating point register bank / a bypass network ("FP register bank / bypass network") 2510 , Address generation units ("AGUs") 2512 and 2514 , fast arithmetic-logical units (ALUs) ("fast ALUs") 2516 and 2518 , a slow arithmetic-logical unit ("slow ALU") 2520 , a floating point ALU ("FP") 2522 and a floating point movement unit ("FP movement") 2524 . In at least one embodiment, the integer register bank / bypass network 2508 and the floating point register bank / bypass network 2510 also referred to herein as “register banks 2508 , 2510 " designated. In at least one embodiment, the AGUs 2512 and 2514 , the fast ALUs 2516 and 2518 who have favourited the slow ALU 2520 who have favourited Floating-point ALU 2522 and the floating point movement unit 2524 also referred to herein as “execution units 2512 , 2514 , 2516 , 2518 , 2520 , 2522 and 2524 " designated. In at least one embodiment, the execution block 2511 include, without limitation, any number (including zero) and any type of register banks, bypass networks, address generation units, and execution units in any combination.

In at least one embodiment, the register nets 2508 , 2510 between the µop planners 2502 , 2504 , 2506 and the execution units 2512 , 2514 , 2516 , 2518 , 2520 , 2522 and 2524 arranged being. In at least one embodiment, the integer register bank / bypass network 2508 Integer operations. In at least one embodiment, the floating point register bank / bypass network maintains 2510 Floating point operations. In at least one embodiment, each of the register nets 2508 , 2510 contain, without restriction, a bypass network that can bypass recently completed results that have not yet been written to a register bank or pass them on to new dependent µops. In at least one embodiment, the register nets 2508 , 2510 communicate data with each other. In at least one embodiment, the integer register bank / bypass network 2508 include, without limitation, two separate banks of registers, one bank of registers for low-order data with thirty-two bits and a second register bank for high-order data with thirty-two bits. In at least one embodiment, the floating point register bank / bypass network 2510 contain 128-bit wide entries without restriction, since floating point instructions typically have operands with a width of 64 to 128 bits.

In at least one embodiment, the execution units 2512 , 2514 , 2516 , 2518 , 2520 , 2522 , 2524 Follow instructions. In at least one embodiment, the register nets store 2508 , 2510 Integer and floating point data operand values that microinstructions require to be executed. In at least one embodiment, the processor can 2500 any number and combination of execution units without restriction 2512 , 2514 , 2516 , 2518 , 2520 , 2522 , 2524 include. In at least one embodiment, the floating point ALU 2522 and the floating point movement unit 2524 Perform floating point, MMX, SIMD, AVX, and SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, the floating point ALU 2522 include, without limitation, a 64-bit by 64-bit floating point divider for performing division, square root, and remainder micro-ops. In at least one embodiment, instructions that involve a floating point value can be handled with floating point hardware. In at least one embodiment, ALU operations can be directed to the fast ALUs 2516 , 2518 be handed over. In at least one embodiment, the fast ALUs 2516 , 2518 perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most of the complex integer operations go to the slow ALU 2520 , since the slow ALU 2520 may include, without limitation, integer execution hardware for long latency-type operations such as a multiplier, shifts, flag logic, and branch processing. In at least one embodiment, the load / store operations of a memory can be performed by the AGUs 2512 , 2514 are executed. In at least one embodiment, the fast ALU 2516 , the fast ALU 2518 and the slow ALU 2520 Perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU 2516 , the fast ALU 2518 and the slow ALU 2520 be implemented to support a variety of data bit sizes including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating point ALU 2522 and the floating point movement unit 2524 be implemented to support a range of operands having bits of varying widths, such as 128-bit packed data operands associated with SIMD and multimedia instructions.

In at least one embodiment, the µop planners share 2502 , 2504 , 2506 dependent operations before a parent load finishes executing. In at least one embodiment, the processor can 2500 because µops in the processor 2500 scheduled and executed speculatively, also include logic for handling memory errors. In at least one embodiment, if a data load in a data cache fails, there may be dependent operations in progress in a pipeline that exited a scheduler with temporarily incorrect data. In at least one embodiment, a retry mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations may need to be retried and independent operations may be allowed to complete. In at least one embodiment, the scheduler and a retry mechanism of at least one embodiment of a processor can also be configured to intercept instruction sequences for character string comparison operations.

In at least one embodiment, “registers” can refer to on-board processor storage locations that can be used as part of instructions to identify operands. In at least one embodiment, the registers may be those that may be usable from outside a processor (from a programmer's point of view). In at least one embodiment, the registers may not be limited to any particular type of circuit. Rather, in at least one embodiment, a register can store data, provide data and perform the functions described herein. In at least one embodiment, the herein can be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers 32- Bit integer data. A register bank from at least one embodiment also contains eight multimedia SIMD registers for packed data.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, portions of the or all of the inference and / or training logic 915 in the execution block 2511 and other memories or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein can be one or more of those in the execution block 2511 Use the illustrated ALUs. In addition, weighting parameters can be stored in on-chip or off-chip memory and / or in registers (shown or not shown), the ALUs of the execution block 2511 Configure to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

26th illustrates a deep learning application processor 2600 according to at least one embodiment. In at least one embodiment, the deep learning application processor uses 2600 Instructions that when executed by the deep learning application processor 2600 the deep learning application processor 2600 cause some or all of the processes and techniques described throughout this disclosure to be performed. In at least one embodiment, the deep learning is an application processor 2600 an application specific integrated circuit (ASIC). In at least one embodiment, the application processor performs 2600 Matrix multiplication operations either "hardwired" into hardware as the result of executing one or more instructions, or both. In at least one embodiment, the deep learning application processor includes 2600 processing cluster without restriction 2610 (1) -2610 (12) , cross-chip links (inter-chip links - "ICLs") 2620 (1) -2620 (12) , cross-chip controls (Inter-Chip Controllers - "ICCs") 2630 (1) -2630 (2) , High-bandwidth memory second generation ("HBM2") 2640 (1) -2640 (4) , Memory controllers ("Mem Ctrlrs") 2642 (1) -2642 (4) , a physical layer with high bandwidth memory ("HBM PHY") 2644 (1) -2644 (4) , a central management control processing unit ("management control CPU") 2650 , a serial peripheral interface, an integrated circuit and a universal input / output block ("SPI, I ² C, GPIO") 2660 , an Interconnect Express controller for peripheral components and a direct memory access block ("PCIe controller and DMA") 2670 and a sixteen-lane Interconnect Express port for peripheral components ("PCI-Express x 16") 2680 .

In at least one embodiment, the processing clusters 2610 Perform deep learning operations, including inference or prediction operations based on weighting parameters calculated using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2610 include any number and any type of processors without limitation. In at least one embodiment, the deep learning application processor 2600 any number and type of processing clusters 2600 include. In at least one embodiment, the cross-chip links are 2620 bidirectional. In at least one embodiment, the cross-chip links enable 2620 and the cross-chip controls 2630 multiple deep leaming application processors 2600 the exchange of information, including activation information, resulting from performing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2600 any number (including zero) and any type of ICLs 2620 and ICCs 2630 include.

In at least one embodiment, the HBM2s represent 2640 a total of 32 gigabytes (GB) of memory available. In at least one embodiment is HBM2 2640 (i) both with the memory controller 2642 (i) as well as the HBM PHY 2644 (i) associated, where "i" is an arbitrary integer. In at least one embodiment, any number of HBM2s 2640 Deploy any type and total amount of high-bandwidth storage with any number (including zero) and any type of storage controllers 2642 and HBM PHYs 2644 be associated. In at least one Embodiment can SPI, I ² C, GPIO 2660 , PCIe control and DMA 2670 and / or PCIe 2680 be replaced by any number and any type of blocks that enable any number and any type of communication standards in any technically feasible manner.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the deep learning application processor is used to train a machine learning model, such as a neural network, to run the deep learning application processor 2600 Predict or inference information provided. In at least one embodiment, the deep learning application processor is 2600 used to inference or predict information based on a trained machine learning model (e.g. neural network) that is being passed by another processor or system, or by the deep learning application processor 2600 was trained. In at least one embodiment, the processor can 2600 can be used to perform one or more of the neural network use cases described herein.

27 Figure 3 is a block diagram of a neuromorphic processor 2700 according to at least one embodiment. In at least one embodiment, the neuromorphic processor can 2700 one or more inputs from sources external to the neuromorphic processor 2700 receive. In at least one embodiment, these inputs can be sent to one or more neurons 2702 inside the neuromorphic processor 2700 be transmitted. In at least one embodiment, the neurons can 2702 and components thereof can be implemented using circuitry or logic including one or more arithmetic and logic units (ALUs). In at least one embodiment, the neuromorphic processor can 2700 without limitation, thousands or millions of instances of neurons 2702 but it can include any suitable number of neurons 2702 be used. In at least one embodiment, each instance of the neuron 2702 a neuron input 2704 and a neuron output 2706 include. In at least one embodiment, the neurons can 2702 Produce outputs that are sent to inputs of other instances of neurons 2702 can be transferred. For example, in at least one embodiment, the neuron inputs 2704 and the neuron outputs 2706 via synapses 2708 be interconnected.

In at least one embodiment, the neurons can 2702 and the synapses 2708 be interconnected in such a way that the neuromorphic processor 2700 works to be made by the neuromorphic processor 2700 process or analyze received information. In at least one embodiment, the neurons can 2702 an output pulse (or "Fire" or "Spike") is transmitted when the via the neuron input 2704 received inputs exceed a threshold. In at least one embodiment, the neurons can 2702 those at the neuron inputs 2704 sum or integrate received signals. For example, in at least one embodiment, the neurons 2702 be implemented as leaky Integrate-and-Fire neurons, where if a sum (referred to as a "membrane potential") exceeds a threshold value, the neuron 2702 generate an output (or "fire") using a transfer function such as a sigmoid or threshold function. In at least one embodiment, a leaking Integrate-and-Fire neuron can send signals to the neuron inputs 2704 are received, sum to a membrane potential and also apply a decay factor (or leak) to reduce a membrane potential. In at least one embodiment, a leaking Integrate-and-Fire neuron can fire if there are several input signals at the neuron inputs 2704 received fast enough to cross a threshold (ie, before a membrane potential dies down too far to fire). In at least one embodiment, the neurons can 2702 be implemented using circuitry or logic that receives inputs, integrates inputs into a membrane potential, and decays a membrane potential. In at least one embodiment, inputs can be averaged or any other suitable transfer function can be used. In addition, the neurons can 2702 in at least one embodiment, include, without limitation, comparator circuitry or logic that spikes an output spike at the neuron output 2706 generate if the result of applying a transfer function to the neuron input 2704 exceeds a threshold. In at least one embodiment, the neuron 2702 as soon as it fires, ignore previously received input information, for example by resetting a membrane potential to 0 or another suitable standard value. In at least one embodiment, the neuron 2702 as soon as the membrane potential has been reset to 0, resume normal operation after an appropriate period of time (or refractory period).

In at least one embodiment, the neurons can 2702 through the synapses 2708 be interconnected. In at least one embodiment, the synapses 2708 working to get signals from an output of a first neuron 2702 to an input of a second neuron 2702 transferred to. In at least one embodiment, the neurons can 2702 Information about more than one instance of the synapse 2708 transfer. In at least one embodiment, one or more instances of the neuron output 2706 via an instance of the synapse 2708 with an instance of the neuron input 2704 in the same neuron 2702 be connected. In at least one embodiment, an instance of the neuron 2702 having one over an instance of the synapse 2708 Output to be transmitted generated as a “presynaptic neuron” in relation to this instance of the synapse 2708 are designated. In at least one embodiment, an instance of the neuron 2702 having one over an instance of the synapse 2708 receives transmitted input, as a "postsynaptic neuron" in relation to this instance of the synapse 2708 are designated. As an instance of the neuron 2702 Input from one or more instances of the synapse 2708 can receive and also outputs via one or more instances of the synapse 2708 In at least one embodiment, a single instance of the neuron can transmit 2702 hence both a “presynaptic neuron” and a “postsynaptic neuron” in relation to different instances of the synapses 2708 being.

In at least one embodiment, the neurons can 2702 be organized in one or more layers. In at least one embodiment, each instance of the neuron 2702 a neuron output 2706 having one or more synapses 2708 to one or more neuron inputs 2704 can fan out. In at least one embodiment, the neuron outputs 2706 of neurons 2702 in a first shift 2710 with the neuron inputs 2704 of neurons 2702 in a second shift 2712 be connected. In at least one embodiment, the layer can 2710 referred to as the "feed forward layer". In at least one embodiment, each instance of the neuron can 2702 in an instance of the first layer 2710 to each instance of the neuron 2702 in the second shift 2712 fan out. In at least one embodiment, the first layer can 2710 can be referred to as a "fully connected feedforward layer". In at least one embodiment, each instance of the neuron can 2702 in an instance of the second layer 2712 to fewer than all instances of the neuron 2702 in a third shift 2714 fan out. In at least one embodiment, the second layer can 2712 can be referred to as a "sparsely connected feedforward layer". In at least one embodiment, the neurons can 2702 in the second shift 2712 to the neurons 2702 fan out into several other layers, including to the neurons 2702 which is also in the second layer 2712 condition. In at least one embodiment, the second layer can 2712 referred to as the "recurrent shift". In at least one embodiment, the neuromorphic processor can 2700 include, without limitation, any suitable combination of recurrent layers and feedforward layers, including, without limitation, both sparsely connected feedforward layers and fully connected feedforward layers.

In at least one embodiment, the neuromorphic processor can 2700 include, without limitation, a reconfigurable interconnection architecture or dedicated hard-wired interconnects to the synapse 2708 with the neurons 2702 connect to. In at least one embodiment, the neuromorphic processor can 2700 Include without restriction circuitry or logic that makes it possible to create synapses as required on the basis of the topology of the neural network and the neurons fan-in / out of different neurons 2702 assign. For example, in at least one embodiment, the synapses 2708 with the neurons 2702 using an interconnection structure such as a network on a chip or with dedicated links. In at least one embodiment, the synapse interconnects and components thereof can be implemented using circuitry or logic.

28 Figure 3 is a block diagram of a processing system in accordance with at least one embodiment. In at least one embodiment, the system includes 2800 one or more processors 2802 and one or more graphics processors 2808 and it can be a single processor desktop system, a multiprocessor workstation system, or a server system that has a large number of processors 2802 or processor cores 2807 having. In at least one The embodiment is the system 2800 a processing platform integrated into a system on a chip (SoC) integrated circuit for use in mobile, portable, or embedded devices.

In at least one embodiment, the system 2800 Include or be integrated with a server-based game platform, game console, including game and media console, mobile game console, portable game console, or online game console. In at least one embodiment, the system is 2800 a cell phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, the processing system 2800 also include, be coupled to, or integrated into a wearable device, such as a smartwatch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system is 2800 a television or set-top box device that includes one or more processors 2802 and has a graphical interface provided by one or more graphics processors 2808 is produced.

In at least one embodiment, include one or more processors 2802 one or more processor cores each 2807 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each is one or more processor cores 2807 configured to have a specific sequence of instructions 2809 processed. In at least one embodiment, the sequence of instructions 2809 Enable Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC) or arithmetic using a Very Long Instruction Word (VLIW). In at least one embodiment, the processor cores 2807 a different instruction sequence each time 2809 process, which may contain instructions to facilitate the emulation of other instruction sequences. In at least one embodiment, the processor core 2807 also include other processing devices such as a digital signal processor (DSP).

In at least one embodiment, the processor includes 2802 a cache memory 2804 . In at least one embodiment, the processor can 2802 have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is used by various components of the processor 2802 shared. In at least one embodiment, the processor uses 2802 also an external cache (e.g., a level 3 (L3) cache or last level cache (LLC)) (not shown) obtained from the processor cores using known cache coherency techniques 2807 can be shared. In at least one embodiment, is in the processor 2802 additionally a register bank 2806 that may contain different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). In at least one embodiment, the register bank 2806 Include universal registers or other registers.

In at least one embodiment, one or more processor (s) are 2802 with one or more interface bus (s) 2810 coupled to communication signals, such as address, data or control signals, between the processor 2802 and other components in the system 2800 transferred to. In at least one embodiment, the interface bus can 2810 be a processor bus, such as a version of a direct media interface (DMI) bus. In at least one embodiment, the interface bus is 2810 not limited to a DMI bus, but can include one or more peripheral component interconnect buses (e.g. PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor (s) include 2802 an integrated memory controller 2816 and a platform control hub 2830 . In at least one embodiment, the memory control enables 2816 communication between a storage device and other components of the system 2800 , while the platform controller hub (PCH) 2830 provides connections to I / O devices over a local I / O bus.

In at least one embodiment, a storage device 2820 a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or any other storage device that has adequate computing power to serve as process memory. In at least one embodiment, the storage device 2820 as system memory for the system 2800 work to data 2822 and instructions 2821 to save when using one or more processors 2802 run an application or process. In at least one embodiment, the memory controller is 2816 also to an optional external graphics processor 2812 coupled with one or more graphics processors 2808 in the processors 2802 can communicate to perform graphics and media operations. In at least one embodiment, a display device 2811 with the processor (s) 2802 be connected. In at least one embodiment, the display device 2811 include one or more of an internal display device, such as in a mobile electronic device or a laptop device, or an external display device connected through a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 2811 a head mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) or augmented reality (AR) applications.

In at least one embodiment, the platform control hub enables 2830 that peripheral devices with the storage device 2820 and the processor 2802 connected via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include audio control 2846 , a network controller 2834 , a firmware interface 2828 , a wireless transceiver 2826 , Touch sensors 2825 and a data storage device 2824 (e.g. hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 2824 be connected via a storage interface (e.g. SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g. PCI, PCI Express). In at least one embodiment, the touch sensors can 2825 Include touchscreen sensors, pressure sensors, or fingerprint sensors. In at least one embodiment, the wireless transceiver can 2826 a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long-Term-Evolution (LTE) transceiver. In at least one embodiment, the firmware interface enables 2828 communication with the system firmware and can, for example, be a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, the network controller 2834 enable a network connection to a wired network. In at least one embodiment, a network controller with high computing power (not shown) is connected to the interface bus 2810 coupled. In at least one embodiment, the audio controller is 2846 a multi-channel high definition audio control. In at least one embodiment, the system includes 2800 an optional legacy I / O controller 2840 for coupling older devices (e.g. Personal System 2 (PS / 2)) to the system 2800 . In at least one embodiment, the platform control hub 2830 also with one or more Universal Serial Bus (USB) controllers 2842 associated with input devices such as keyboard and mouse combinations 2843 , a camera 2844 or other USB input devices.

In at least one embodiment, an instance of the memory controller 2816 and the platform control hub 2830 into a discrete external graphics processor, such as the external graphics processor 2812 , be integrated. In at least one embodiment, the platform control hub 2830 and / or the memory controller 2816 external to one or more processor (s) 2802 being. For example, the system can 2800 in at least one embodiment, an external memory controller 2816 and a platform control hub 2830 that can be configured as a memory control hub and a peripheral control hub within a system chipset that is compatible with the processor (s) 2802 is in communication.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, portions of the or all of the inference and / or training logic 915 into the graphics processor 2800 be involved. For example, in at least one embodiment, the training and / or inference techniques described herein can use one or more of the ALUs embodied in a 3D pipeline. In addition, in at least one embodiment, the inference and / or training operations described herein can be performed using logic other than that in 9A or 9B logic illustrated. In at least one embodiment, weighting parameters can be stored in on-chip or off-chip memory and / or in registers (shown or not shown), the ALUs of the graphics processor 2800 Configure to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

29 Figure 3 is a block diagram of a processor 2900 , the one or more processor cores 2902A-2902N , an integrated memory controller 2914 and an integrated graphics processor 2908 has, according to at least one embodiment. In at least one embodiment, the processor can 2900 additional cores up to and including the additional core 2902N represented by dashed-line boxes. In at least one embodiment, each includes the processor cores 2902A-2902N one or more internal cache units 2904A-2904N . In at least one embodiment, each processor core also has access to one or more shared cache units 2906 on.

In at least one embodiment, the internal cache units provide 2904A-2904N and the shared cache units 2906 a cache memory hierarchy within the processor 2900 In at least one embodiment, the cache storage units 2904A-2904N at least one Instruction and data cache levels within each processor core and one or more intermediate level shared cache such as level 2 (L2), level 3 (L3), level 4 (L4), or other cache levels , with a highest cache level in front of the external storage being classified as LLC. In at least one embodiment, the cache coherency logic maintains coherency between different cache units 2906 and 2904A-2904N upright.

In at least one embodiment, the processor can 2900 also a set of one or more bus control units 2916 and a system agent kernel 2910 include. In at least one embodiment, bus control units manage 2916 a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core provides 2910 a management functionality for various processor components ready. In at least one embodiment, the system includes agent core 2910 one or more integrated memory controllers 2914 to manage access to various external storage devices (not shown).

In at least one embodiment, include one or more of the processor cores 2902A-2902N Simultaneous multi-threading support. In at least one embodiment, the system includes agent core 2910 Components for coordinating and operating the cores 2902A-2902N during multi-threaded processing. In at least one embodiment, the system agent core 2910 additionally contain a power control unit (PCU), the logic and components for regulating one or more power states of the processor cores 2902A-2902N and the graphics processor 2908 contains.

In at least one embodiment, the processor includes 2900 additionally the graphics processor 2908 for performing graphics processing operations. In at least one embodiment, the graphics processor is 2908 with shared cache units 2906 and the system agent kernel 2910 coupled to the one or more integrated memory controllers 2914 contains. In at least one embodiment, the system includes agent core 2910 also a display control 2911 to drive the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 2911 also be a separate module that has at least one interconnection with the graphics processor 2908 is coupled, or it can be in the graphics processor 2908 be integrated.

In at least one embodiment, a ring-based interconnection unit 2912 for coupling internal components of the processor 2900 used. In at least one embodiment, an alternative interconnection unit may be used, such as point-to-point interconnection, switched interconnection, or other techniques. In at least one embodiment, the graphics processor is 2908 via an I / O link 2913 with the ring interconnection 2912 coupled.

In at least one embodiment, the I / O link provides 2913 represent at least one of several types of I / O interconnection, including an in-chassis I / O interconnection, the communication between various processor components and an embedded memory module 2918 with high computing power, such as an eDRAM module. In at least one embodiment, each of the processor cores use 2902A-2902N and the graphics processor 2908 an embedded memory module 2918 as a shared last-level cache.

In at least one embodiment, the processor cores are 2902A-2902N homogeneous cores executing a common instruction set architecture. In at least one embodiment, the processor cores are 2902A-2902N heterogeneous with respect to instruction set architecture (ISA), with one or more of the processor cores 2902A-2902N execute a common set of instructions while one or more other cores of the processor cores 2902A-2902N execute a subset of a common instruction set or another instruction set. In at least one embodiment, the processor cores are 2902A-2902N heterogeneous in terms of microarchitecture, one or more cores having a relatively higher power consumption being coupled to one or more cores having a lower power consumption. In at least one embodiment, the processor can 2900 be implemented on one or more chips or as a SoC integrated circuit.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, portions of the or all of the inference and / or training logic 915 in the Graphics processor 2910 be involved. For example, in at least one embodiment, the training and / or inference techniques described herein may include one or more of the ALUs, graphics kernel (s) embodied in a 3D pipeline 2902 , shared logic, or other logic in 29 use. In addition, in at least one embodiment, the inference and / or training operations described herein can be performed using logic other than that in 9A or 9B logic illustrated. In at least one embodiment, weighting parameters can be stored in on-chip or off-chip memory and / or in registers (shown or not shown), the ALUs of the processor 2900 Configure to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

30th Figure 3 is a block diagram of a graphics processor 3000 , which can be a discrete graphics processing unit or a graphics processor integrated with a variety of processing cores. In at least one embodiment, the graphics processor is communicating 3000 via a memory mapped I / O interface with registers on the graphics processor 3000 and with commands stored in memory. In at least one embodiment, includes the graphics processor 3000 a memory interface 3014 to access memory. In at least one embodiment, the memory interface is 3014 an interface to local storage, one or more internal caches, one or more shared external caches and / or to system memory.

In at least one embodiment, includes the graphics processor 3000 also a display control 3002 to send display output data to a display device 3020 to drift. In at least one embodiment, the display includes control 3002 Hardware for one or more overlay levels for the display device 3020 and the composition of multiple layers of video or user interface elements. In at least one embodiment, the display device 3020 be an internal or external display device. In at least one embodiment, the display device is 3020 a head-mounted display device such as a virtual reality (VR) display device or an augmented reality (AR) display device. In at least one embodiment, includes the graphics processor 3000 a video codec engine 3006 for encoding, decoding, or transcoding media to, from, or between one or more media encoding formats, including, but not limited to, Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264 / MPEG-4 AVC as well as Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1 and Joint Photographic Experts Group (JPEG) formats such as JPEG and Motion JPEG (MJPEG).

In at least one embodiment, includes the graphics processor 3000 a block image transfer (BLIT) engine 3004 to perform two-dimensional (2D) raster operations, including, for example, bit-boundary block transfers. However, in at least one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE). 3010 accomplished. In at least one embodiment, the GPE is 3010 a computing engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

In at least one embodiment, the GPE includes 3010 a 3-D pipeline 3012 for performing 3-D operations such as rendering 3-dimensional images and scenes using processing functions operating on 3-D primitive shapes (e.g., rectangle, triangle, etc.). In at least one embodiment, the 3D pipeline includes 3012 programmable elements and fixed function elements that perform various tasks and / or execution threads for a 3D / media subsystem 3015 produce. While the 3D pipeline 3012 can be used to perform media operations includes the GPE 3010 also, in at least one embodiment, a media pipeline 3016 used to perform media operations such as video post-processing and image enhancement.

In at least one embodiment, the media pipeline includes 3016 Fixed-function or programmable logic units to perform one or more specialized media operations such as video decoding acceleration, video de-interleaving, and video encoding acceleration in place of, or on behalf of, the video codec engine 3006 . In at least one embodiment, the media pipeline includes 3016 additionally a thread generation unit to create threads for execution on the 3D / media subsystem 3015 to create. In at least one embodiment, created threads perform computations for media operations on one or more graphics execution units that are in the 3-D / media subsystem 3015 are included.

In at least one embodiment, the 3D / media subsystem includes 3015 Logic to execute threads through the 3D pipeline 3012 and the media pipeline 3016 be generated. In at least one embodiment, send the 3D pipeline 3012 and the media pipeline 3016 Thread execution requirements on the 3D / media subsystem 3015 , which includes thread arbitration logic for arbitrating and arbitrating various requests for available thread execution resources. In at least one embodiment, the execution resources include an array of graphics execution units for processing 3D and media threads. In at least one embodiment, the 3D / media subsystem includes 3015 one or more internal caches for thread instructions and data. In at least one embodiment, the subsystem includes 3015 also shared memory, including registers and addressable memory, to share data between threads and to store output data.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, portions of the or all of the inference and / or training logic 915 into the graphics processor 3000 be involved. For example, in at least one embodiment, the training and / or inference techniques described herein can be one or more of those in the 3-D pipeline 3012 use embodied ALUs. In addition, in at least one embodiment, the inference and / or training operations described herein can be performed using logic other than that in 9A or 9B logic illustrated. In at least one embodiment, weighting parameters can be stored in on-chip or off-chip memory and / or in registers (shown or not shown), the ALUs of the graphics processor 3000 Configure to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

31 Figure 3 is a block diagram of a graphics processing engine 3110 a graphics processor according to at least one embodiment. In at least one embodiment, the graphics processing engine (GPE) is 3110 a version of the in 30th shown GPE 3010 . In at least one embodiment, is a media pipeline 3116 optional and possibly not explicitly within the GPE 3110 contain. In at least one embodiment, a separate media and / or image processor is attached to the GPE 3110 coupled.

In at least one embodiment, the GPE is 3110 to a command streamer 3103 coupled or it includes one that is part of a 3D pipeline 3112 and / or the media pipeline 3116 provides an instruction stream. In at least one embodiment, the command streamer is 3103 coupled to memory, which may be system memory or one or more of internal cache memory and shared cache memory. In at least one embodiment, the command streamer receives 3103 Commands from memory and sends commands to the 3D pipeline 3112 and / or the media pipeline 3116 . In at least one embodiment, the instructions are instructions, primitives, or micro-operations that are fetched from a ring buffer, the instructions for the 3D pipeline 3112 and the media pipeline 3116 saves. In at least one embodiment, a ring buffer can additionally contain batch command buffers that store batches of a plurality of commands. In at least one embodiment, the instructions for the 3D pipeline 3112 also include references to data stored in memory such as, but not limited to, vertex and geometry data for the 3-D pipeline 3112 and / or image data and storage objects for the media pipeline 3116 . In at least one embodiment, process the 3D pipeline 3112 and the media pipeline 3116 Instructions and data by performing operations or one or more threads of execution to a graphics core array 3114 to share. In at least one embodiment, the graphics core array includes 3114 one or more blocks of graphics cores (e.g. graphics core (s) 3115A , Graphics core (s) 3115B ), with each block containing one or more graphics cores. In at least one embodiment, each graphics core contains a set of graphics execution resources, the universal and graphics-specific execution logic for performing graphics and arithmetic operations as well as logic for texture processing with a fixed function and / or for accelerating machine learning and artificial intelligence, including inference - and / or training logic 915 in 9A and 9B , contains.

In at least one embodiment, the 3D pipeline includes 3112 Fixed function logic and programmable logic to process one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, arithmetic shaders or other shader programs, by processing instructions and execution threads the graphics core array 3114 be allocated. In at least one embodiment, the graphics core array represents 3114 provide a unified block of execution resources for use in processing shader programs. In at least one embodiment contains a multi-purpose execution logic (e.g. execution units) within the graphics core (s) 3115A-3115B of the graphics core array 3114 Support for various 3D API shader languages and it can execute multiple simultaneous execution threads associated with multiple shaders.

In at least one embodiment, the graphics core array includes 3114 also execution logic for performing media functions such as video and / or image processing. In at least one embodiment, the execution units additionally contain general-purpose logic which can be programmed in such a way that, in addition to graphics processing operations, it carries out parallel general-purpose arithmetic operations.

In at least one embodiment, output data generated by threads running on the graphics core array 3114 executed, data in a unified return buffer (URB) 3118 output to memory. In at least one embodiment, the URB 3118 Store data for multiple threads. In at least one embodiment, the URB 3118 used to send data between different threads running on the graphics core array 3114 are executed. In at least one embodiment, the URB 3118 additionally for the synchronization between threads on the graphics core array 3114 and the fixed function logic within the shared function logic 3120 be used.

In at least one embodiment, the graphics core is an array 3114 scalable, so that the graphics core array 3114 contains a variable number of graphics cores, each of which has a variable number of execution units based on a target performance and computing power level of the GPE 3110 exhibit. In at least one embodiment, the execution resources are dynamically scalable so that the execution resources can be activated or deactivated as needed.

In at least one embodiment, the graphics core is an array 3114 to the shared functional logic 3120 coupled that includes multiple resources used by the graphics cores in the graphics core array 3114 shared. In at least one embodiment, the shared functions are created by the shared functional logic 3120 are embodied in hardware logic units, which are a specialized supplementary functionality for the graphics core array 3114 provide. In at least one embodiment, the shared functional logic includes 3120 a scanner unit 3121 , a math unit 3122 and logic 3123 for inter-thread communication (ITC), but is not limited to this. In at least one embodiment, one or more cache (s) are 3125 in the shared functional logic 3120 contained or linked to them.

In at least one embodiment, a shared function is used if there is a demand for a specialized function for inclusion in the graphics core array 3114 not enough. In at least one embodiment, a single instantiation of a specialized function in the shared function logic 3120 used and by other execution resources within the graphics core array 3114 shared. In at least one embodiment, specific shared functions can be used within the shared function logic 3120 created by the graphics core array 3114 are used intensively in the jointly used functional logic 3416 within the graphics core array 3114 be included. In at least one embodiment, the shared functional logic 3416 within the graphics core array 3114 some or all of the logic within the shared functional logic 3120 include. In at least one embodiment, all logic elements within the shared functional logic 3120 within the shared functional logic 3126 of the graphics core array 3114 be duplicated. In at least one embodiment, the functional logic is shared 3120 in favor of the jointly used functional logic 3126 within the graphics core array 3114 locked out.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, portions of the or all of the inference and / or training logic 915 into the graphics processor 3110 be involved. For example, in at least one embodiment, the training and / or inference techniques described herein can be one or more of those in the 3-D pipeline 3112 embodied ALUs, graphics core (s) 3115 , shared logic 3126 , shared logic 3120 or other logic in 31 use. In addition, in at least one embodiment, the inference and / or training operations described herein can be performed using logic other than that in 9A or 9B logic illustrated. In at least one embodiment, weighting parameters can be stored in on-chip or off-chip memory and / or in registers (shown or not shown), the ALUs of the graphics processor 3110 Configure to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

32 Figure 13 is a block diagram of hardware logic of a graphics processor core 3200 according to at least one embodiment described herein. In at least one embodiment, the graphics processing core is 3200 contained in a graphics core array. In at least one embodiment, it can be the graphics processor core 3200 , sometimes referred to as a core disk, are one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processing core is 3200 exemplary of a graphics core slice and a graphics processor, as described herein, may include multiple graphics core slices based on the desired performance and computing power envelopes. In at least one embodiment, each graphics core can 3200 a fixed function block 3230 include, the one with several partial cores 3201A-3201F is coupled, which are also referred to as sub-slices and contain modular blocks of universal and fixed function logic.

In at least one embodiment, the fixed function block includes 3230 a geometry and fixed functions pipeline 3236 by all partial cores in the graphics processor 3200 can be shared, for example in implementations with graphics processors with lower processing power and / or lower power. In at least one embodiment, the geometry and fixed function pipeline includes 3236 a 3D fixed-function pipeline, a video front-end unit, a thread producer and thread arbiter, and a unified return buffer manager who manages unified return buffers.

In at least one embodiment, the fixed function block includes 3230 also a graphics SoC interface 3237 , a graphics microcontroller 3238 and a media pipeline 3239 . In at least one embodiment, the graphics SoC provides the interface 3237 an interface between the graphics core 3200 and other processor cores within an integrated circuit as a system on a chip. In at least one embodiment, the graphics microcontroller is 3238 a programmable sub-processor that can be configured to perform various functions of the graphics processor 3200 managed, including thread allocation, scheduling and preemption. In at least one embodiment, the media pipeline includes 3239 Logic to facilitate decoding, encoding, preprocessing and / or post-processing of multimedia data, including image and video data. In at least one embodiment, implements the media pipeline 3239 Media operations via requirements for computing or scanning logic within the sub-cores 3201A-3201F .

In at least one embodiment, the SoC enables interface 3237 it to the graphics core 3200 to communicate with general purpose application processor cores (e.g. CPUs) and / or other components within a SoC, including memory hierarchy elements such as a shared last-level cache memory, system RAM, and / or embedded on-chip or in-package DRAM . In at least one embodiment, the SoC interface can 3237 also enable communication with fixed function devices within a SoC, such as camera imaging pipelines, and allow the use of and / or implement global atomic memory used by the graphics core 3200 and the CPUs can be shared within a SoC. In at least one embodiment, the graphics SoC interface can 3237 also power management controls for the graphics processor core 3200 and implement an interface between a clock domain of the graphics processor core 3200 and other clock domains within a SoC. In at least one embodiment, the SoC enables interface 3237 receiving command buffers from a command streamer and global thread arbiter configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. In at least one embodiment, media pipeline commands and instructions 3239 if media operations are to be performed, or to a geometry and fixed function pipeline (e.g. the geometry and fixed function pipeline 3236 and / or the geometry and fixed functions pipeline 3214 ) when graphics processing operations are to be performed.

In at least one embodiment, the graphics microcontroller can 3238 be configured to perform various planning and management tasks for the graphics core 3200 performs. In at least one embodiment, the graphics microcontroller can 3238 the planning of the graphics and / or computation workload on different graphics parallel engines within the arrays 3202A-3202F , 3204A-3204F of the execution units (EU) within the sub-cores 3201A-3201F execute. In at least one embodiment, host software may run on a CPU core of a SoC, including the graphics core 3200 , is running, submitting workloads to one of several GPU paths that include a Scheduling operation calls on an appropriate graphics engine. In at least one embodiment, the planning operations include determining what workload to run next, posting a workload to a command streamer, anticipating existing workloads running on an engine, monitoring the progress of a workload, and notifying the host Software when a workload is complete. In at least one embodiment, the graphics microcontroller can 3238 also states with low power or inactive states for the graphics core 3200 facilitate, taking the graphics core 3200 a capability is provided to register within the graphics core 3200 to back up and restore over state transitions with low performance independent of an operating system and / or graphics driver software on a system.

In at least one embodiment, the graphics core 3200 more or less than the illustrated partial cores 3201A-3201F have up to N modular partial cores. For each set of N sub-kernels, the graphics kernel can 3200 in at least one embodiment also shared functional logic 3210 , shared and / or cache memory 3212 , a geometry / fixed function pipeline 3214 as well as additional fixed function logic 3216 to speed up various graphics and arithmetic processing operations. In at least one embodiment, the shared functional logic 3210 Logic units (e.g. scanner, math and / or inter-thread communication logic) include those of N sub-cores within the graphics core 3200 can be used together. In at least one embodiment, the shared and / or cache memory 3212 Last level cache for N partial cores 3201A-3201F within the graphics core 3200 and also serve as shared storage that can be accessed by multiple sub-cores. In at least one embodiment, the geometry / fixed function pipeline 3214 instead of the geometry / fixed functions pipeline 3236 within the fixed function block 3230 be included and contain similar logic units.

In at least one embodiment, the graphics core includes 3200 additional fixed function logic 3216 , the various fixed function acceleration logic for use by the graphics core 3200 may include. In at least one embodiment, the includes additional fixed function logic 3216 an additional geometry pipeline for use in shading from position only. When shading from position only, there are at least two geometry pipelines, whereas a complete geometry pipeline within the geometry and fixed function pipelines 3214 , 3236 and a culling pipeline, which is an additional geometry pipeline that is within the additional fixed function logic 3216 may be included. In at least one embodiment, a culling pipeline is a stripped-down version of a full geometry pipeline. In at least one embodiment, a full pipeline and a culling pipeline can run different instances of an application, with each instance having a separate context. In at least one embodiment, the shading of position only can hide long runs of culling of discarded triangles, thereby allowing the shading to complete earlier in some cases. For example, in at least one embodiment, the culling pipeline logic may be within the additional fixed function logic 3216 Run position shaders in parallel with a main application and it generally produces critical results faster than a full pipeline because a culling pipeline retrieves and shades position attributes of vertices without rasterizing and rendering pixels in an image buffer. In at least one embodiment, a culling pipeline may use generated critical results to compute visibility information for all triangles, regardless of whether those triangles are being culled. In at least one embodiment, a full pipeline (which in this case can be referred to as a repeating pipeline) may consume visibility information to skip culled triangles to only shade visible triangles that will eventually be passed on to a screening phase.

In at least one embodiment, the additional fixed function logic 3216 also include machine learning accelerator logic such as fixed function matrix multiplication logic for implementations that include machine learning optimizations or inferencing machine learning.

In at least one embodiment, each includes graphics sub-core 3201A-3201F a set of execution resources that can be used to perform graphics, media, and computational operations in response to requests from graphics pipeline, media pipeline, or shader programs. In at least one embodiment, the graphics sub-cores include 3201A-3201F several EU Arrays 3202A-3202F , 3204A-3204F , Logic 3203A-3203F for thread allocation and inter-thread communication (thread dispatch / inter-thread communication - TD / IC), a 3D (e.g. texture) scanner 3205A-3205F , a media scanner 3206A-3206F , a shader processor 3207A-3207F and shared local memory (SLM) 3208A-3208F . In at least one embodiment, the include EU arrays 3202A-3202F , 3204A-3204F Several execution units each, which are universal graphics processing units that are capable of performing floating point and integer / fixed point logic operations in the service of a graphics, media or arithmetic operation, including graphics, media or arithmetic Shader programs. In at least one embodiment, the TD / IC logic performs 3203A-3203F local thread arbitration and thread control operations for execution units within a sub-core and it facilitates communication between threads executing on execution units of a sub-core. In at least one embodiment, the 3D scanner 3205A-3205F Read texture or other data related to 3D graphics into memory. In at least one embodiment, the 3-D scanners may read texture data differently based on a configured scan state and a texture format associated with a given texture. In at least one embodiment, the media scanners 3206A-3206F perform similar read operations based on a type and format associated with the media data. In at least one embodiment, each graphics sub-core can be 3201A-3201F alternatively contain a uniform 3D scanner and media scanner. In at least one embodiment, threads referring to execution units within each of the sub-cores 3201A-3201F running on the shared local storage 3208A-3208F within each sub-core to allow threads running within a thread group to run using a shared pool of on-chip memory.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, portions of the or all of the inference and / or training logic 915 into the graphics processor 3210 be involved. For example, in at least one embodiment, the training and / or inference techniques described herein can include one or more of the ALUs embodied in a 3D pipeline, the graphics microcontroller 3238 , the Geometry and Fixed Function Pipeline 3214 and 3236 or other logic in 32 use. In addition, in at least one embodiment, the inference and / or training operations described herein can be performed using logic other than that in 9A or 9B logic illustrated. In at least one embodiment, weighting parameters can be stored in on-chip or off-chip memory and / or in registers (shown or not shown), the ALUs of the graphics processor 3200 Configure to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

33A-33B illustrate thread execution logic 3300 that includes an array of processing elements of a graphics processor core, according to at least one embodiment. 33A illustrates at least one embodiment in which the thread execution logic 3300 is used. 33B illustrates exemplary internal details of a graphics execution unit 3308 according to at least one embodiment.

As in 33A illustrates the thread execution logic 3300 in at least one embodiment, a shader processor 3302 , a thread arbiter 3304 , an instruction cache 3306 , a scalable execution unit array including a variety of execution units 3307A-3307N and 3308A-3308N , a scanner 3310 , a data cache 3312 and a data port 3314 . In at least one embodiment, a scalable execution unit array may dynamically scale by adding one or more execution units (e.g., any of the execution units 3308A-N or 3307A-N ) can be activated or deactivated based on a workload's compute requirements, for example. In at least one embodiment, the scalable execution units are interconnected via an interconnection structure that is linked to each execution unit. In at least one embodiment, the thread includes execution logic 3300 one or more connections to memory, such as system memory or cache memory, through one or more of the instruction cache 3306 , the data port 3314 , the scanner 3310 and the execution units 3307 or 3308 . In at least one embodiment, each execution unit (e.g. 3307A ) an independent programmable universal computing unit that is able to execute several simultaneous hardware threads while several data elements are processed in parallel for each thread. In at least one embodiment, the array is the execution units 3307 and or 3308 scalable so that it contains any number of individual execution units.

In at least one embodiment, the execution units 3307 and or 3308 mainly used to run shader programs. In at least one embodiment, the shader processor 3302 process different shader programs and with the shader programs associated threads of execution through a thread arbiter 3304 to share. In at least one embodiment, the thread arbiter includes 3304 Logic for brokering thread initiation requests from graphics and media pipelines and instantiating requested threads on one or more execution units in the execution units 3307 and or 3308 . For example, in at least one embodiment, a geometry pipeline may dispatch vertex, tessellation, or geometry shaders to the thread execution logic for processing. In at least one embodiment, the thread arbiter may 3304 also process runtime thread creation requests from executing shader programs.

In at least one embodiment, the execution units support 3307 and or 3308 an instruction set that includes native support for many standard 3D graphics shader instructions so that shader programs from graphics libraries (such as Direct 3D and OpenGL) run with minimal translation. In at least one embodiment, the execution units support vertex and geometry processing (e.g. vertex programs, geometry programs and / or vertex shaders), pixel processing (e.g. pixel shaders, fragment shaders) and universal processing (e.g. computing and media shaders). In at least one embodiment, each of the execution units is 3307 and or 3308 , which contain one or more arithmetic-logic units (ALUs), capable of multi-issue-single-instruction-multiple-data (SIMD) execution and the multi-thread operation enables an efficient execution environment despite memory accesses with higher Latency. In at least one embodiment, each hardware thread within each execution unit has a dedicated high-bandwidth register bank and an independent thread state associated therewith. In at least one embodiment, multiple outputs per clock are executed on pipelines capable of single and double precision integer and floating point operations, SIMD branching ability, logical operations, transcendental operations, and other miscellaneous operations. In at least one embodiment, the dependency logic operates within the execution units 3307 and or 3308 that a waiting thread sleeps while it waits for data from memory or one of the shared functions until the requested data has been returned. In at least one embodiment, while a waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, in at least one embodiment, an execution unit may perform operations on a pixel shader, fragment shader, or other type of shader program, including another vertex shader, during a delay associated with a vertex shader operation, execute.

In at least one embodiment, each execution unit operates in the execution units 3307 and or 3308 of arrays of data elements. In at least one embodiment, the number of data elements is an “execution quantity” or the number of channels for an instruction. In at least one embodiment, an execution channel is a logical execution unit for accessing data elements, masking, and flow control within instructions. In at least one embodiment, the number of channels can be independent of a number of physical arithmetic and logic units (ALUs) or floating point units (FPUs) for a specific graphics processor. In at least one embodiment, the execution units support 3307 and or 3308 Integer and floating point data types.

In at least one embodiment, an instruction set of an execution unit contains SIMD instructions. In at least one embodiment, different data elements can be stored as a packed data type in a register and the execution unit processes different elements based on the data size of the elements. For example, in at least one embodiment, when operating on a 256-bit wide vector, 256 bits of a vector are stored in a register and an execution unit is stored on a vector as four separate 64-bit packed data elements (data elements of the size quad-word - QW). ), eight separate 32-bit packed data elements (data elements of the size double word (DW)), sixteen separate 16-bit packed data elements (data elements of the size of word (Word - W)) or thirty-two separate 8-bit data elements (data elements of the Size byte (B)) operated. In at least one embodiment, however, other vector widths and register sizes are possible.

In at least one embodiment, one or more execution units can be merged into a merged execution unit 3309A-3309N combined, the thread control logic ( 3311A-3311N ) that is common to the merged ESs, such as the execution unit 3307A associated with the execution unit 3308A to the merged execution unit 3309A is merged. In at least one embodiment, several EUs can be merged into one EU group. In at least one embodiment, each EU in a merged EU group can be configured to execute a separate SIMD hardware thread, with a number of EUs in a merged EU group according to different Embodiments may vary. In at least one embodiment, different SIMD widths can be performed per EU including, but not limited to, SIMD8, SIMD16, and SIMD32. In at least one embodiment, each includes fused graphics execution units 3309A-3309N at least two execution units. For example, in at least one embodiment, includes the fused execution unit 3309A a first EU 3307A , a second EU 3308A and thread control logic 3311A that the first EU 3307A and the second EU 3308A is common. In at least one embodiment, the thread control logic controls 3311A Threads running on the merged graphics execution unit 3309A executed so that each ES within the merged execution units 3309A-3309N can be performed using a common instruction pointer register.

In at least one embodiment, one or more internal instruction caches (e.g. 3306 ) in the thread execution logic 3300 to cache thread instructions for execution units. In at least one embodiment, one or more data caches (e.g. 3312 ) to cache thread data during thread execution. In at least one embodiment, is a scanner 3310 included to provide texture sensing for 3D operations and media sensing for media operations. In at least one embodiment, the scanner includes 3310 a specialized texture or media sampling functionality to process texture or media data during a sampling process before the sampled data is provided to an execution unit.

During execution, in at least one embodiment, graphics and media pipelines send thread initiation requests to thread execution logic through thread creation and dispatch logic 3300 . In at least one embodiment, once a group of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) is resumed within the shader processor 3302 called to further compute output information and to cause the results to be written to output areas (e.g. color buffer, depth buffer, template buffer, etc.). In at least one embodiment, a pixel shader or fragment shader calculates the values of various vertex attributes that are to be interpolated over a rasterized object. In at least one embodiment, the pixel processor logic runs within the shader processor 3302 then execute a pixel or fragment shader program supplied via an application programming interface (API). In at least one embodiment, the shader processor shares 3302 for executing a shader program threads via the thread arbiter 3304 an execution unit (e.g. 3308A ) to. In at least one embodiment, the shader uses a processor 3302 the texture sampling logic in the scanner 3310 to access texture data in texture maps stored in memory. In at least one embodiment, arithmetic operations on texture data and input geometry data are used to calculate pixel color data for each geometrical fragment or to exclude one or more pixels from further processing.

In at least one embodiment, the data port 3314 a memory access mechanism for the thread execution logic 3300 ready to output processed data to memory for further processing on a graphics processor output pipeline. In at least one embodiment, the data port includes 3314 one or more cache memories (e.g. the data cache 3312 ) or is coupled to this in order to temporarily store data for memory access via a data port.

As in 33B illustrates, a graphics execution unit 3308 in at least one embodiment, an instruction fetch unit 3337 , an array of general register files (GRF) 3324 , an array of architectural register files (ARF) 3326 , a thread mediator 3322 , a transmitter unit 3330 , a branch unit 3332 , a set of SIMD floating point units (FPUs) 3334 and a set of dedicated integer SIMD ALUs 3335 include. In at least one embodiment, the GRF include 3324 and the ARF 3326 a set of general register banks and architectural register banks associated with each simultaneous hardware thread running in the graphics execution unit 3308 can be active. In at least one embodiment, the architectural state is per thread in the ARF 3326 managed while the data used during thread execution is in the GRF 3324 get saved. In at least one embodiment, the execution state of each thread, including the instruction pointers for each thread, can be stored in thread-specific registers in the ARF 3326 be kept.

In at least one embodiment, the graphics execution unit 3308 adopts an architecture that is a combination of simultaneous multi-threading (SMT) and fine-grained interleaved multi-threading (IMT). In at least one embodiment, the architecture has a modular configuration that is based on a Target number of simultaneous threads and number of registers per execution unit can be fine-tuned, dividing the resources of the execution unit among the logic used to execute multiple simultaneous threads.

In at least one embodiment, the graphics execution unit 3308 Output multiple statements at the same time, each of which can be a different statement. In at least one embodiment, the thread broker 3322 of the graphics execution unit thread 3308 Instructions from one of the transmitter units 3330 , the branching unit 3332 or the SIMD-FPU (s) 3334 allot for execution. In at least one embodiment, each thread of execution can access 128 general purpose registers within the GRF 3324 each register can store 32 bytes, which are accessible as SIMD-8 element vector of 32-bit data elements. In at least one embodiment, each thread of the execution unit has access to 4 kilobytes within the GRF 3324 although embodiments are not so limited and more or fewer register resources may be provided in other embodiments. In at least one embodiment, up to seven threads can be executed simultaneously, although a number of threads per execution unit can also vary according to embodiments. In at least one embodiment where seven threads can access 4 kilobytes, the GRF 3324 save a total of 28 kilobytes. In at least one embodiment, flexible addressing modes may allow registers to be addressed together to effectively form wider registers or to represent layered rectangular block data structures.

In at least one embodiment, memory operations, scanner operations, and other longer latency system communications are dispatched via "send" instructions that are accomplished by message passing to the sending unit 3330 are executed. In at least one embodiment, branch instructions are used by the branch unit 3332 allocated to facilitate SIMD divergence and ultimately convergence.

In at least one embodiment, the graphics execution unit includes 3308 one or more SIMD floating point units (FPU (s)) 3334 for performing floating point operations. In at least one embodiment, the FPU (s) support 3334 also integer calculation. In at least one embodiment, the FPU (s) can 3334 Execute up to a number of M 32-bit floating point (or integer) operations via SIMD or execute up to 2M 16-bit integer or 16-bit floating point operations via SIMD. In at least one embodiment, at least one FPU provides advanced math capabilities to support high-throughput, 64-bit, double-precision, 64-bit floating point math functions. Also in at least one embodiment is a set of 8-bit integer SIMD ALUs 3335 that may be specifically optimized to perform operations associated with machine learning computations.

In at least one embodiment, arrays of multiple instances of the graphics execution unit 3308 instantiated in a graphics split core grouping (e.g. a partial slice). In at least one embodiment, the execution unit 3308 Execute instructions across a variety of execution channels. In at least one embodiment, each thread running on the graphics execution unit 3308 is running, running on a different channel.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, portions of the or all of the inference and / or training logic 915 into the thread execution logic 3300 be involved. In addition, in at least one embodiment, the inference and / or training operations described herein can be performed using logic other than that in 9A or 9B logic illustrated. In at least one embodiment, weighting parameters may be stored in on-chip or off-chip memory and / or in registers (shown or not shown), the ALUs of the thread execution logic 3300 Configure to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

34 illustrates a parallel processing unit ("PPU") 3400 according to at least one embodiment. In at least one embodiment, the PPU is 3400 configured with machine readable code which when executed by the PPU 3400 the PPU 3400 caused to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the PPU is 3400 a multi-threaded processor running on one or more devices with Integrated circuit is implemented and uses multi-threading as a technique for concealing latency, which is designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) on multiple threads in parallel. In at least one embodiment, a thread refers to an execution thread and is an instantiation of a set of instructions configured to do so by the PPU 3400 to be executed. In at least one embodiment, the PPU is 3400 a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to produce two-dimensional ("2D") image data for display on a display device, such as a device with liquid crystal display ("LCD"). In at least one embodiment, the PPU 3400 used to perform computations such as linear algebra operations and machine learning operations. 34 Fig. 10 illustrates an example of a parallel processor that is for illustrative purposes only and should be construed as a non-limiting example of processor architectures contemplated within the scope of this disclosure and that any suitable processor may be used to supplement and / or replace it can be.

In at least one embodiment, there are one or more PPUs 3400 configured to accelerate high performance computing ("HPC"), data center, and machine learning applications. In at least one embodiment, the PPU is 3400 configured to accelerate deep learning systems and applications, including the following non-limiting examples: autonomous vehicle platforms, deep learning, high accuracy voice, image and text recognition systems, intelligent video analytics, molecular simulations, drug discovery, disease diagnosis, Weather forecast, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time voice translation, online search optimization and personalized user recommendations, and more.

In at least one embodiment, the PPU includes 3400 an input / output ("I / O") unit without restriction 3406 , a front-end unit 3410 , a planning unit 3412 , a labor distribution unit 3414 , a hub 3416 , a crossbar (crossbar - "XBar") 3420 , one or more General Purpose Processing Clusters ("GPCs") 3418 and one or more partition units ("storage partition units") 3422 . In at least one embodiment, the PPU is 3400 with a host processor or other PPUs 3400 via one or more high-speed GPU interconnections ("GPU interconnections") 3408 connected. In at least one embodiment, the PPU is 3400 via a system bus 3402 connected to a host processor or other peripheral devices. In at least one embodiment, the PPU is 3400 connected to local storage that includes one or more storage devices ("Storage") 3404 includes. In at least one embodiment, the include storage devices 3404 one or more dynamic random access memory ("DRAM") devices, without limitation. In at least one embodiment, one or more DRAM devices are configured and / or configurable as high bandwidth memory subsystems ("HBM"), with multiple DRAM dies stacked within each device.

In at least one embodiment, the high speed GPU interconnect can 3408 refer to a wire-based multi-lane communications link used by systems for scaling and one or more PPUs 3400 in combination with one or more central processing units ("CPUs") and cache coherence between PPUs 3400 and CPUs as well as CPU mastering supported. In at least one embodiment, data and / or commands are passed through the high speed GPU interconnection 3408 over the hub 3416 to / from other units of the PPU 3400 such as one or more copy engines, video encoders, video decoders, power management units and other components included in 34 may not be explicitly illustrated.

In at least one embodiment, the I / O device is 3406 configured to allow communication (e.g. commands, data) from a host processor (in 34 not illustrated) via the system bus 3402 transmits and receives. In at least one embodiment, the I / O device is communicating 3406 with the host processor directly via the system bus 3402 or through one or more intermediate devices such as a storage bridge. In at least one embodiment, the I / O device can 3406 via the system bus 3402 communicate with one or more other processors, such as one or more of the PPUs 3400 . In at least one embodiment, implements the I / O device 3406 a Peripheral Component Interconnect Express ("PCIe") interface for communication over a PCIe bus. In at least one embodiment, implements the I / O device 3406 Interfaces for communicating with external devices.

In at least one embodiment, the I / O device decodes 3406 via the system bus 3402 received packets. In at least one embodiment, at least some packets represent commands that are configured to run the PPU 3400 cause various operations to be performed. In at least one embodiment, the I / O device is transmitting 3406 decoded commands to various other units of the PPU 3400 as dictated by commands. In at least one embodiment, commands are sent to the front-end unit 3410 transferred and / or to the hub 3416 or other units of the PPU 3400 such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (in 34 not explicitly illustrated). In at least one embodiment, the I / O device is 3406 configured to allow communication between and among different logical units of the PPU 3400 routes.

In at least one embodiment, a program executed by the host processor encodes a stream of instructions in a buffer called the PPU 3400 Provision workloads for processing. In at least one embodiment, a workload includes instructions and data to be processed by those instructions. In at least one embodiment, a buffer is a region in memory shared by both a host processor and the PPU 3400 access (e.g. read / write) - a host interface unit can be configured to access this buffer in system memory associated with the system bus 3402 is connected, accesses memory requests that are made over the system bus 3402 through the I / O base 3406 be transmitted. In at least one embodiment, a host processor writes an instruction stream to a buffer and then transmits a pointer to the PPU for a start of an instruction stream 3400 so that the front-end unit 3410 Receives pointers for one or more instruction streams and manages one or more instruction streams by reading instructions from instruction streams and instructions to various units of the PPU 3400 forwards.

In at least one embodiment, the front-end unit is 3410 to the planning unit 3412 coupled to the different GPCs 3418 configured to process tasks defined by one or more instruction streams. In at least one embodiment, the planning unit is 3412 configured to provide status information related to various by the scheduler unit 3412 tracked managed tasks, with the status information indicating which of the GPCs 3418 a task is assigned, whether the task is active or inactive, what priority level is associated with the task, and so on. In at least one embodiment, the planner unit manages 3412 the execution of a large number of tasks on one or more GPCs 3418 .

In at least one embodiment, the planning unit is 3412 to the work distribution unit 3414 coupled that is configured to run tasks on the GPCs 3418 allocates. In at least one embodiment, the work distribution unit tracks 3414 a number of scheduled tasks performed by the scheduler unit 3412 received, and the work distribution unit 3414 maintains a pool of pending tasks and a pool of active tasks for each of the GPCs 3418 . In at least one embodiment, the pending task pool comprises a number of slots (e.g., 32 slots) that contain tasks that are to be processed by a particular GPC 3418 assigned; an active task pool may include a number of slots (e.g. 4 slots) for tasks that are active by the GPCs 3418 processed so if one of the GPCs 3418 completes the execution of a task, this task from this pool of active tasks for the GPC 3418 is removed and another task is selected from a pool of outstanding tasks and executed on the GPC 3418 is scheduled. If there is an active task on the GPC 3418 is inactive, such as while waiting for a data dependency to be resolved, then in at least one embodiment that active task becomes from the GPC 3418 removed and returned to this pending task pool, while another task in this pending task pool is selected and run on the GPC 3418 is scheduled.

In at least one embodiment, the work distribution unit communicates 3414 with one or more GPCs 3418 via the XBar 3420 . In at least one embodiment, the XBar 3420 an interconnection network that includes many units of the PPU 3400 to other units of the PPU 3400 couples and can be configured to do this, the work distribution unit 3414 to a specific GPC 3418 to pair. In at least one embodiment, one or more other units of the PPU 3400 over the hub 3416 with the XBar 3420 be connected.

In at least one embodiment, tasks are carried out by the scheduler unit 3412 and managed by the Labor Distribution Unit 3414 one of the GPCs 3418 allocated. In at least one embodiment, the GPC is 3418 configured to process a task and produce results. In at least one embodiment, the results can be shared by other tasks within the GPC 3418 consumed over the XBar 3420 to another GPC 3418 routed or in memory 3404 get saved. In at least one embodiment, the results can be shared across the partition units 3422 , which is a memory interface for reading and writing data to / from memory 3404 implement into memory 3404 to be written. In at least one embodiment, the results can be delivered through the high speed GPU interconnection 3408 to another PPU 3404 or CPU. In at least one embodiment, the PPU includes 3400 without restriction a number U of partition units 3422 , which equals a number of separate and distinct storage devices 3404 is that to the PPU 3400 are coupled as herein in connection with 36 described in more detail.

In at least one embodiment, a host processor executes a driver kernel that implements an application programming interface (“API”) that enables one or more applications running on a host processor to operate on the PPU 3400 to plan. In at least one embodiment, multiple computing applications are run simultaneously by the PPU 3400 executed and the PPU 3400 provides isolation, quality of service ("QoS"), and independent address spaces for multiple computing applications. In at least one embodiment, an application generates instructions (e.g. in the form of API calls) that cause a driver kernel to set up one or more tasks for execution by the PPU 3400 , and this driver kernel outputs tasks to one or more streams passed through the PPU 3400 are processed. In at least one embodiment, each task comprises one or more groups of related threads, which can be referred to as a warp. In at least one embodiment, a warp comprises a plurality of related threads (e.g. 32 threads) that can be executed in parallel. In at least one embodiment, cooperating threads can refer to a plurality of threads that contain instructions for performing tasks and that exchange data through a shared memory. In at least one embodiment, threads and cooperating threads are associated with 36 described in more detail.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the deep leaming application processor is used to train a machine learning model, such as a neural network, to implement the PPU 3400 Predict or inference information provided. In at least one embodiment, the deep leaming application processor 3400 used to inference or predict information based on a trained machine learning model (e.g., a neural network), transmitted by another processor or system, or by the PPU 3400 was trained. In at least one embodiment, the PPU 3400 can be used to perform one or more of the neural network use cases described herein.

35 illustrates a General Purpose Processing Cluster ("GPC") 3500 according to at least one embodiment. In at least one embodiment, it is the GPC 3500 to the GPC 3418 out 34 . In at least one embodiment, each includes GPC 3500 without limitation, a number of hardware units for processing tasks and each includes GPC 3500 without limitation a pipeline manager 3502 , a pre-raster operations unit ("preROP") 3504 , a raster engine 3508 , a work distribution crossbar ("WDX") 3516 , a memory management unit ("MMU") 3518 , one or more data processing clusters ("DPCs") 3506 and any suitable combination of parts.

In at least one embodiment, the operation of the GPC 3500 by the pipeline manager 3502 controlled. In at least one embodiment, the pipeline manager manages 3502 the configuration of one or more DPCs 3506 for processing tasks assigned to the GPC 3500 are assigned. In at least one embodiment, the pipeline manager configures 3502 at least one of one or more DPCs 3506 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, the DPC is 3506 configured to run a vertex shader program on a programmable streaming multiprocessor (streaming multi-processor - "SM") 3514 to execute. In at least one embodiment, the pipeline manager is 3502 configured to forward the packets received from a work distribution unit to appropriate logical units within the GPC 3500 routes, and in at least one embodiment, some packets may be sent to fixed function hardware units in the preROP 3504 and / or the raster engine 3508 while other packets are being routed for processing by a primitive engine 3512 or the SM 3514 to the DPCs 3506 can be routed. In at least one embodiment, the pipeline manager configures 3502 at least one of the DPCs 3506 for implementing a model of a neural network and / or a computation pipeline.

In at least one embodiment, the preROP unit is 3504 configured to, in at least one embodiment, be performed by the raster engine 3508 and the DPCs 3506 generated data to a unit for raster operations (Raster Operations - "ROP") in the partition unit 3422 routes used in connection with 34 is described in more detail. In at least one embodiment, the preROP unit is 3504 configured in such a way that, among other things, it performs optimizations for color mixing, organizes pixel color data and performs address translations. In at least one embodiment, includes the raster engine 3508 includes, without limitation, a number of fixed function hardware units configured to perform various raster operations, and in at least one embodiment includes the raster engine 3508 without limitation, a setup engine, a coarse grid engine, a culling engine, a clipping engine, a fine grid engine, a tile blending engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives transformed vertices and generates plane equations associated with the geometric primitive defined by the vertices; the plane equations are passed to a coarse raster engine to generate coverage information (e.g., an x, y coverage mask for a tile) for the primitive; the output of a coarse raster engine is passed to a culling engine in which fragments associated with a primitive that fail a z-test are culled and passed to a clipping engine in which fragments that are outside of a truncated cone of vision are subjected to clipping. In at least one embodiment, fragments that survive clipping and culling are passed to a fine grid engine to generate attributes for pixel fragments based on plane equations generated by a setup engine. In at least one embodiment, an output comprises the raster engine 3508 Fragments submitted by any suitable entity, such as one within the DPC 3506 implemented fragment shaders are to be processed.

In at least one embodiment, each comprises DPC 3506 that is in the GPC 3500 is included, without restriction, an M-Pipe controller (M-Pipe Controller - "MPC") 3510 ; the primitive engine 3512 ; one or more SMs 3514 and any suitable combination thereof. In at least one embodiment, the MPC controls 3510 the operation of the DPC 3506 and routes from the pipeline manager 3502 received packets to the appropriate units in the DPC 3506 . In at least one embodiment, packets associated with a vertex are sent to the primitive engine 3512 routed configured to retrieve vertex attributes associated with a vertex from memory; In contrast, packets associated with a shader program can be sent to the SM 3514 be transmitted.

In at least one embodiment, the SM 3514 without limitation, a programmable streaming processor configured to process tasks represented by a number of threads. In at least one embodiment, the SM 3514 multiple threads and is configured so that it concurrently executes a large number of threads (e.g. 32 threads) from a specific group of threads and implements a single instruction multiple data ("SIMD") architecture which each thread in a group of threads (e.g. a warp) is configured to process a different record based on the same set of instructions. In at least one embodiment, all of the threads in a group of threads execute a common set of instructions. In at least one embodiment, the SM 3514 a Single Instruction Multiple Thread ("SIMT") architecture in which each thread in a group of threads is configured to process a different set of data based on that common set of instructions, but allowing each Threads in a group of threads diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp, thereby enabling concurrency between warps and serial execution within warps when threads diverge within a warp. In another embodiment, a program counter, a call stack, and an execution state are maintained for each individual thread, thereby enabling equivalent concurrency between all threads, within and between warps. In at least one embodiment, the execution state is maintained for each individual thread and threads executing common instructions can be converged and executed in parallel for better efficiency. At least one embodiment of the SM 3514 is described in more detail herein.

In at least one embodiment, the MMU 3518 an interface between the GPC 3500 and a storage partition unit (e.g. the partition unit 3422 out 34 ) and provides the MMU 3518 Translation of virtual addresses to physical addresses, memory protection and mediation of memory requests ready. In at least one embodiment, the MMU 3518 one or more address translation buffers (“TLBs”) to perform the translation of virtual addresses to physical addresses in memory.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the deep leaming application processor is used to train a machine learning model, such as a neural network, to use the GPC 3500 Predict or inference information provided. In at least one embodiment, the GPC 3500 used to inference or predict information based on a trained machine learning model (e.g., a neural network), transmitted by another processor or system, or by the GPC 3500 was trained. In at least one embodiment, the GPC 3500 can be used to perform one or more of the neural network use cases described herein.

36 Fig. 10 illustrates a memory partition unit 3600 a parallel processing unit (“PPU”) according to at least one embodiment. In at least one embodiment, the memory partition unit includes 3600 one unit without restriction 3602 for raster operations (“ROP”), a level two (“L2”) cache 3604, a memory interface 3606 and any suitable combination thereof. In at least one embodiment, the memory interface is 3606 coupled to memory. In at least one embodiment, the memory interface can 3606 Implement 32-, 64-, 128-, 1024-bit data buses or the like for high speed data transfer. In at least one embodiment, the PPU U includes memory interfaces 3606 , where U is a positive integer, with a memory interface 3606 per pair of partition units 3600 , where each pair of partition units 3600 is connected to a corresponding storage device. For example, in at least one embodiment, the PPU may be connected to up to Y memory devices, such as high bandwidth memory stacks or graphics double data rate version 5 synchronous dynamic random access memory ("GDDR5-SDRAM").

In at least one embodiment, implements the memory interface 3606 a memory interface with second generation high bandwidth memory ("HBM2") and Y is equal to half of U. In at least one embodiment, HBM2 memory stacks are on a physical chassis with a PPU, which compares to traditional GDDR5 SDRAM Systems provides significant savings in performance and space. In at least one embodiment, each HBM2 stack contains, without restriction, four memory dies with Y = 4, each HBM2 stack containing two 128-bit channels per die for a total of 8 channels and a data bus width of 1024 bits. In at least one embodiment, this memory supports Single Error Correcting Double Error Detecting (“SECDED”) error correction code (“ECC”) for protecting data. In at least one embodiment, the ECC can provide higher reliability for computing applications that are susceptible to data corruption.

In at least one embodiment, the PPU implements a multi-level memory hierarchy. In at least one embodiment, the memory partition device supports 3600 unified memory to provide a single unified virtual address space for the memory of the central processing unit (“CPU”) and the PPU, thereby enabling data to be shared between virtual storage systems. In at least one embodiment, the frequency of accesses by a PPU to memory residing on other processors is tracked to ensure that pages of memory are moved into physical memory of the PPU that is accessing pages more frequently. In at least one embodiment, the high speed GPU supports interconnection 3408 Address translation services that enable the PPU to access the page tables of a CPU directly and provide a PPU with full access to the CPU memory.

In at least one embodiment, copy engines transfer data between multiple PPUs or between PPUs and CPUs. In at least one embodiment, copy engines may generate page faults for addresses that are not mapped in page tables and the memory partition unit 3600 then handles page faults by mapping the addresses into the page table, whereupon the copy engine carries out a transmission. In at least one embodiment, the memory is pinned (ie, non-pageable) between multiple processors for multiple Copy Engine operations, which significantly reduces the available memory. In at least one embodiment, addresses can be passed to copy engines in the event of hardware page faults, regardless of whether memory pages are memory-resident and a copy process is transparent.

Data from memory 3404 out 34 or another system memory are in accordance with at least one embodiment by the memory partition unit 3600 retrieved and in L2 cache 3604 stored on the chip and shared by different GPCs. Any storage partition unit 3600 In at least one embodiment, includes, without limitation, at least a portion of the L2 cache associated with a corresponding storage device. In at least one embodiment, the lower level caches are implemented in different units within the GPCs. In at least one embodiment, each of the SMs 3514 out 35 implement a level 1 ("L1") cache, this L1 cache being a private memory used for a specific SM 3514 is dedicated, and data from the L2 cache 3604 are fetched and in each L1 cache for processing in functional units of the SMs 3514 saved. In at least one embodiment, the L2 cache is 3604 to the memory interface 3606 and the in 34 XBar shown 3420 coupled.

In at least one embodiment, the ROP unit performs 3602 Perform graphics screening operations related to pixel color such as color compression, pixel blending, and more. In at least one embodiment, implements the ROP unit 3602 the in-depth inspection in conjunction with the raster engine 3508 , being a depth for a sample location associated with a pixel fragment from a culling engine of the raster engine 3508 receives. In at least one embodiment, the depth is checked against a corresponding depth in a depth buffer for a sample location associated with a fragment. If this fragment passes the depth test for that sample point, the ROP unit updates 3602 then in at least one embodiment the depth buffer and transmits a result of this depth check to the raster engine 3508 . It goes without saying that there are a number of partition units 3600 can differ from a number of GPCs and therefore can each ROP unit 3602 be coupled to each GPC in at least one embodiment. In at least one embodiment, the ROP unit tracks 3602 the packets received by various GPCs and determines whether one is sent by the ROP unit 3602 generated result for the XBar 3420 should be routed through.

37 illustrates a Streaming Multiprocessor ("SM") 3700 according to at least one embodiment. In at least one embodiment, the SM 3700 the SM off 35 . In at least one embodiment, the SM 3700 an instruction cache without restriction 3702 , one or more planning units 3704 , a register bank 3708 , one or more processing cores ("cores") 3710 , one or more special function units ("SFUs") 3712 , one or more load / store units ("LSUs") 3714 , an interconnection network 3716 , a shared memory / level one ("L1") cache 3718 and / or any suitable combination thereof.

In at least one embodiment, a work distribution unit allocates tasks for execution on General Purpose Processing Clusters ("GPCs") of Parallel Processing Units ("PPUs") and each task is assigned to a specific data processing cluster ("DPC") within a GPC, and if a task with a shader Is associated with the program, this task becomes one of the SMs 3700 assigned. In at least one embodiment, the scheduler unit receives 3704 Tasks from a work distribution unit and it manages the instruction scheduling for one or more thread blocks assigned to the SM 3700 assigned. In at least one embodiment, the planning unit plans 3704 Thread blocks for execution as warps from parallel threads, with at least one warp assigned to each thread block. In at least one embodiment, each warp threads. In at least one embodiment, the planner unit manages 3704 a plurality of different thread blocks by assigning warps to different thread blocks and then, during each clock cycle, instructions from a plurality of different cooperative groups to different functional units (e.g. processing cores 3710 , SFUs 3712 and LSUs 3714 ) allocates.

In at least one embodiment, cooperative groups can refer to a programming model for organizing groups of communicating threads that allows developers to express the granularity with which threads communicate, thus enabling the expression of richer, more efficient parallel decompositions. In at least one embodiment, cooperative startup APIs support synchronization between thread blocks for executing parallel algorithms. In at least one embodiment, applications of conventional programming models provide a single, simple construct for synchronizing cooperating threads: a lock over all threads of a thread block (e.g. the syncthreads () function). In at least one embodiment, however, programmers can define groups of threads with a lower than thread block granularity and synchronize them within defined groups in order to enable higher computing power, design flexibility and software reuse in the form of collective group-wide functional interfaces. In at least one embodiment, cooperative groups allow programmers to explicitly define groups of threads with sub-block (ie, as small as a single thread) and multi-block granularity, and to perform collective operations, such as synchronization, on threads in a cooperative group. In at least one Embodiment, this programming model supports a clean composition across software boundaries, so that libraries and utility functions can safely synchronize within their local context without having to make assumptions about convergence. In at least one embodiment, cooperative group primitives enable new patterns of cooperative parallelism, including, but not limited to, producer-consumer parallelism, opportunistic parallelism, and global synchronization over an entire grid of thread blocks.

In at least one embodiment, there is an allocation unit 3706 configured to transmit instructions to one or more functional units and the scheduler unit 3704 includes two allocation units without restriction 3706 which allow two different instructions from a common warp to be dispatched during each clock cycle. In at least one embodiment, each includes a scheduler unit 3704 a single allocation unit 3706 or additional allocation units 3706 .

In at least one embodiment, each includes SM 3700 in at least one embodiment, the register bank without restriction 3708 , which is a set of registers for functional units of the SM 3700 provides. In at least one embodiment, the register bank is 3708 distributed to each functional unit, so that each functional unit has a dedicated section of the register bank 3708 is assigned. In at least one embodiment, the register bank is 3708 divided into different warps, which are caused by the SM 3700 and the register bank 3708 provides temporary data storage for operands that are connected to data paths of functional units. In at least one embodiment, each comprises SM 3700 without limitation, a variety of L processing cores 3710 , where L is a positive integer. In at least one embodiment, the SM 3700 a large number (e.g. 128 or more) of different processing cores without limitation 3710 . In at least one embodiment, each includes processing core 3710 without limitation, a full pipeline processing unit with single precision, double precision and / or mixed precision, which includes without limitation an arithmetic-logic unit for floating point numbers and an arithmetic-logic unit for integers. In at least one embodiment, the arithmetic and logic units for floating point numbers implement the IEEE 754-2008 standard for floating point arithmetic. In at least one embodiment, the include processing cores 3710 without restriction 64 floating point kemes with single precision (32 bit), 64 integer cores, 32 floating point kemes with double precision (64 bit) and 8 tensor cores.

According to at least one embodiment, tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are in the processing cores 3710 contain. In at least one embodiment, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations to train and inference neural networks. In at least one embodiment, each tensor core operates on a 4x4 matrix and performs a matrix multiplication and accumulation operation D = AXB + C, where A, B, C and D are 4x4 matrices.

In at least one embodiment, matrix multiplication inputs A and B are 16-bit floating point matrices and accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices. In at least one embodiment, the tensor cores operate on 16-bit floating point input data with 32-bit floating point accumulation. In at least one embodiment, 16-bit floating point multiplication uses 64 operations and yields a full precision product which is then accumulated using 32-bit floating point addition with other intermediate products for 4x4x4 matrix multiplication. In at least one embodiment, the tensor kernels are used to perform much larger two-dimensional or higher-dimensional matrix operations built from these smaller elements. In at least one embodiment, an API, such as a CUDA 9 C ++ API, exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations in order to program the tensor cores efficiently with CUDA-C ++. In at least one embodiment, at a CUDA level on a warp level interface, matrices the size of 16x16 are assumed, which extend over all 32 threads of the warp.

In at least one embodiment, each comprises SM 3700 without restriction M SFUs 3712 that perform special functions (e.g., attribute evaluation, reciprocal square root, and the like). In at least one embodiment, the include SFUs 3712 without limitation, a tree traversing unit configured to traverse a hierarchical tree data structure. In at least one embodiment, the include SFUs 3712 without restriction a texture unit that is configured to Perform texture map filter operations. In at least one embodiment, the texture units are configured to load texture maps (e.g., a 2D array of texels) from memory and to scan texture maps to produce scanned texture values for use in shader programs implemented by the SM 3700 are executed. In at least one embodiment, the texture maps are in the shared memory / L1 cache 3718 saved. In at least one embodiment, the texture units implement texture operations, such as filter operations using mip maps (e.g. texture maps with varying levels of detail), according to at least one embodiment. In at least one embodiment, each includes SM 3700 two texture units without restriction.

Every SM 3700 In at least one embodiment, includes, without limitation, N LSUs 3714 , the load and store operations between the shared memory / L1 cache 3718 and the register bank 3708 to implement. The interconnection network 3716 connects each functional unit to the register bank in at least one embodiment 3708 and the LSU 3714 with the register bank 3708 and the shared memory / L1 cache 3718 . In at least one embodiment, the interconnection network is 3716 a crossbar that can be configured to include any functional units with any registers in the register bank 3708 connects and LSUs 3714 with the register bank 3708 and locations in the shared memory / L1 cache 3718 connects.

In at least one embodiment, the shared memory is / L1 cache 3718 an array of on-chip memory that, in at least one embodiment, provides data storage and communication between the SM 3700 and the primitive engine as well as between threads in the SM 3700 enables. In at least one embodiment, the shared memory includes / L1 cache 3718 without limitation, it has a storage capacity of 128 KB and it is located in a path from the SM 3700 to a partition unit. In at least one embodiment, the shared memory is / L1 cache 3718 used in at least one embodiment for caching read and write operations. In at least one embodiment, one or more of the shared memory are / L1 cache 3718 , L2 cache and additional storage.

Combining the functionality of the data cache and the shared memory in a single memory block provides, in at least one embodiment, improved computing power for both types of memory accesses. In at least one embodiment, the capacity is used as a cache by programs that do not use shared memory, or it may be used, such as if the shared memory is configured to use half a capacity and texture- and load / store operations can use the remaining capacity. Integration with shared memory / L1 cache 3718 enables shared memory / L1 cache 3718 to function as a high throughput line for streaming data while simultaneously high bandwidth, low latency access to frequently reused data, in accordance with at least one embodiment Data is provided. In at least one embodiment, a configuration for universal parallel computation can use a simpler configuration compared to graphics processing. In at least one embodiment, fixed function graphics processing units are bypassed, resulting in a much simpler programming model. In a configuration for universal parallel computations, a work distribution unit in at least one embodiment assigns blocks of threads directly to the DPCs and distributes them. In at least one embodiment, threads in a block execute a common program, using a unique thread ID in the computation to ensure that each thread produces unique results, the SM 3700 the shared memory / L1 cache is used to run the program and perform calculations 3718 used to communicate between the threads and the LSU 3714 to read and write to global memory through shared memory / L1 cache 3718 and the memory partition unit is in use. When configuring for universal parallel calculations, the SM 3700 in at least one embodiment, commands issued by the scheduler unit 3704 can be used to start new work in the DPCs.

In at least one embodiment, a PPU resides in a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smartphone (e.g., a wireless portable device), a personal digital assistant ("PDA"), a digital camera, vehicle, head-mounted display, portable electronic device, etc., included or coupled thereto. In at least one embodiment, a PPU is embodied on a single semiconductor substrate. In at least one embodiment, a PPU is included in a system on a chip ("SoC") along with one or more other devices, such as additional PPUs, memory, a reduced instruction Set computer (“RISC”) CPU, a memory management unit (“MMU”), a digital-to-analog converter (“DAC”) and the like.

In at least one embodiment, a PPU may be included on a graphics card that includes one or more storage devices. In at least one embodiment, this graphics card can be configured to interface with a PCIe slot on a motherboard of a desktop computer. In at least one embodiment, this PPU can be an integrated graphics processing unit (“iGPU”) that is contained in the chipset of a motherboard.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided. In at least one embodiment, the deep leaming application processor is used to train a machine learning model, such as a neural network, to provide the SM 3700 Predict or inference information provided. In at least one embodiment, the SM 3700 used to inference or predict information based on a trained machine learning model (e.g., a neural network), transmitted by another processor or system, or by the SM 3700 was trained. In at least one embodiment, the SM 3700 can be used to perform one or more of the neural network use cases described herein.

Embodiments are disclosed that are related to a virtualized computing platform for advanced computing, such as image inference and image processing in medical applications. Without limitation, embodiments can include radiography, magnetic resonance imaging (MRI), nuclear medicine, ultrasound, sonography, elastography, photoacoustic imaging, tomography, echocardiography, functional near infrared spectroscopy, and magnetic particle imaging, or a combination thereof. In at least one embodiment, a virtualized computing platform and the processes associated therewith described herein can additionally or alternatively without restriction in forensic analysis, detection and imaging of the subsurface (e.g. oil exploration, archeology, paleontology, etc.), topography, oceanography, geology, osteology, meteorology, intelligent area or object tracking and monitoring, sensor data processing (e.g. RADAR, SONAR, LIDAR, etc.) and / or genomics and gene sequencing.

With reference to 38 is 38 an exemplary data flow diagram for a process 3800 for generating and deploying an image processing and inference pipeline according to at least one embodiment. In at least one embodiment, the process 3800 for use with imaging devices, processing devices, genomics devices, gene sequencing devices, radiology devices, and / or other types of devices in one or more facilities 3802 such as medical facilities, hospitals, health institutes, clinics, research or diagnostic laboratories, etc. In at least one embodiment, the process 3800 can be used to perform genome analysis and inference on sequencing data. Examples of genome analyzes that can be performed using the systems and processes described herein include, without limitation, variant calling, mutation detection, and quantification of gene expression.

In at least one embodiment, the process 3800 within a training system 3804 and / or a deployment system 3806 are executed. In at least one embodiment, the training system 3804 used to train, deploy, and implement machine learning models (e.g., neural networks, object detection algorithms, machine vision algorithms, etc.) for use in the deployment system 3806 perform. In at least one embodiment, the deployment system 3806 Be configured to offload processing and computational resources in a distributed computing environment to meet the infrastructure requirements in the facility 3802 to reduce. In at least one embodiment, the deployment system 3806 a streamlined platform for selecting, customizing, and implementing virtual instruments for use with imaging devices (e.g., MRI, CT scan, X-ray, ultrasound, etc.) or sequencing devices in the facility 3802 provide. In at least one embodiment, virtual instruments may include software defined applications for performing one or more processing operations on imaging data generated by imaging devices, sequencing devices, radiology devices, and / or other types of devices. In at least one embodiment, one or more applications in a pipeline can provide services (for example inference, visualization, calculation, AI, etc.) of the deployment system 3806 use or invoke while running applications.

In at least one embodiment, some of the applications used in advanced processing and inference pipelines may use machine learning models or other AI to perform one or more processing steps. In at least one embodiment, machine learning models can be implemented in the facility 3802 using data 3808 (such as imaging data) can be trained in the facility 3802 (and on one or more servers of a picture archiving and communication system (PACS) in the facility 3802 are stored), and they can be made using imaging or sequencing data 3808 be trained from another facility or facilities (e.g. another hospital, laboratory, clinic, etc.) or a combination thereof. In at least one embodiment, the training system 3804 can be used to provide applications, services and / or other resources to generate working, operational machine learning models for the deployment system 3806 provide.

In at least one embodiment, a model registration database 3824 be supported by object storage, which can support versioning and object metadata. In at least one embodiment, the object storage can be accessed, for example, by a cloud storage facility (e.g. a cloud 3926 out 39 ) compatible application programming interface (API) from within a cloud platform. In at least one embodiment, machine learning models can be found within the model registry database 3824 uploaded, listed, modified or deleted by the developer or partner of a system that interacts with an API. In at least one embodiment, an API can provide access to methods that enable users with appropriate credentials to associate models with applications so that models can be executed as part of the execution of containerized instantiations of applications.

In at least one embodiment, a training pipeline 3904 ( 39 ) Include a scenario in which the establishment 3802 trained their own machine learning model or has an existing machine learning model that needs to be optimized or updated. In at least one embodiment, imaging data 3808 generated by imaging device (s), sequencing devices, and / or other types of devices. In at least one embodiment, once imaging data 3808 received, the AI-supported annotation 3810 can be used to aid in generating annotations that support the imaging data 3808 to be used as ground truth data for a machine learning model. In at least one embodiment, the AI-assisted annotation 3810 include one or more machine learning models (e.g., convolutional neural networks (CNNs)) that can be trained to generate annotations that correspond to the particular types of imaging data 3808 (e.g. from certain devices) and / or certain types of anomalies in the imaging data 3808 correspond. In at least one embodiment, the AI-supported annotations 3810 then used directly or adjusted or fine-tuned using an annotation tool (e.g., by a researcher, clinician, doctor, scientist, etc.) to generate ground truth data. In at least one embodiment, in some examples, labeled clinical data 3812 (e.g., annotations provided by a clinician, doctor, scientist, technician, etc.) can be used as ground truth data for training a machine learning model. In at least one embodiment, the AI-supported annotations 3810 , labeled clinic data 3812 or a combination thereof can be used as ground truth data for training a machine learning model. In at least one embodiment, a trained machine learning model can be used as the output model 3816 are designated and by the deployment system 3806 can be used as described herein.

In at least one embodiment, the training pipeline 3904 ( 39 ) Include a scenario in which the establishment 3802 a machine learning model for use in performing one or more processing tasks for one or more applications in the deployment system 3806 needed the facility 3802 but may not currently have such a machine learning model (or may not have a model that is optimized, efficient, or effective for such purposes). In at least one embodiment, an existing machine learning model can be extracted from the model registration database 3824 to be chosen. In at least one embodiment, the model registration database 3824 Include machine learning models trained to perform a variety of different inference tasks on imaging data. In at least one embodiment, the machine learning models can be stored in the model registration database 3824 to imaging data from facilities other than the facility 3802 have been trained (e.g. facilities located in a different location). In at least one embodiment, the machine learning models can be applied to imaging data from one location, two locations, or any number of Have been trained in places. In at least one embodiment, the training when training on imaging data can take place from a specific location at that location or at least in a way that protects the confidentiality of the imaging data or restricts the transmission of the imaging data outside of the premises (e.g. for compliance of HIPAA regulations, data protection regulations, etc.). In at least one embodiment, once a machine learning model has been trained - or partially trained - in a location, it can be added to the model registration database 3824 to be added. In at least one embodiment, a machine learning model can then be retrained or updated at any number of other facilities and a retrained or updated model can be stored in the model registry 3824 be made available. In at least one embodiment, a machine learning model can then be obtained from the model registration database 3824 can be selected - and as an output model 3816 are designated - and in the deployment system 3806 can be used to carry out one or more processing tasks for one or more applications of a deployment system.

In at least one embodiment, the training pipeline 3904 ( 39 ) can be used in a scenario that involves the establishment 3802 a machine learning model for use in performing one or more processing tasks for one or more applications in the deployment system 3806 requires the establishment 3802 but may not currently have such a machine learning model (or may not have a model that is optimized, efficient, or effective for such purposes). In at least one embodiment, one could be from the model registry 3824 Machine learning model selected due to population differences, genetic variations, the robustness of the training data used to train a machine learning model, the diversity of the anomalies in the training data, and / or other problems with the training data not for those at the facility 3802 generated imaging data 3808 fine-tuned or optimized. In at least one embodiment, the AI-assisted annotation 3810 can be used to aid in generating annotations that support the imaging data 3808 to be used as ground truth data for retraining or updating a machine learning model. In at least one embodiment, labeled clinical data 3812 (e.g., annotations provided by a clinician, doctor, scientist, etc.) can be used as ground truth data for training a machine learning model. In at least one embodiment, retraining or updating a machine learning model may be model training 3814 are designated. In at least one embodiment, the model training 3814 - e.g. B. AI-supported annotations 3810 , labeled clinic data 3812 or a combination thereof - used as ground truth data for retraining or updating a machine learning model.

In at least one embodiment, the deployment system 3806 software 3818 , Services 3820 , Hardware 3822 and / or include other components, features and functionalities. In at least one embodiment, the deployment system 3806 include a software “stack” so that the software 3818 on the services 3820 can be built and the services 3820 can use to perform some or all of the processing tasks and the services 3820 and the software 3818 can on the hardware 3822 be built and the hardware 3822 use to perform processing, storage and / or other arithmetic tasks of the deployment system 3806 to execute.

In at least one embodiment, the software 3818 contain any number of different containers, each container being able to instantiate an application. In at least one embodiment, each application can perform one or more processing tasks in an advanced processing and inference pipeline (e.g., inference, object detection, feature detection, segmentation, image enhancement, calibration, etc.). In at least one embodiment, for each type of imaging device (e.g., CT, MRI, X-ray, ultrasound, sonography, echocardiography, etc.), sequencing device, radiology device, genomics device, etc., there may be any number of containers that perform a data processing task in relation to imaging data 3808 (or other types of data such as those described herein) generated by a device. In at least one embodiment, an advanced processing and inference pipeline can be defined based on selections of different containers that are used to process imaging data 3808 what is desired or required, in addition to containers, is the imaging data for use by each container and / or for use by the facility 3802 received and configured after processing through a pipeline (e.g. to convert outputs back into a usable data type, such as data from digital imaging and communications in medicine (DICOM), data from a radiology information system ( radiology information system - RIS), data from a clinical information system (CIS), data for calling up a remote procedure call (RPC), data that essentially conforms to an interface for representation state transfer (REST) are, data that are substantially compliant with a file-based interface, and / or raw data, for storage and display in the facility 3802 ). In at least one embodiment, a combination of containers within the software 3818 (e.g. forming a pipeline) can be referred to as a virtual instrument (as described in more detail herein) and a virtual instrument can provide services 3820 and hardware 3822 to perform some or all of the processing tasks of containerized applications.

In at least one embodiment, a data processing pipeline may include input data (e.g., imaging data 3808 ) in a DICOM, RIS, CIS, REST-compliant, RPC, raw data and / or other format in response to an inference request (e.g. a request from a user of the deployment system 3806 such as a clinician, doctor, radiologist, etc.). In at least one embodiment, the input data may be representative of one or more images, videos, and / or other data representations generated by one or more imaging devices, sequencing devices, radiology devices, genomics devices, and / or other types of devices. In at least one embodiment, the data may be preprocessed as part of the data processing pipeline to prepare the data for processing by one or more applications. In at least one embodiment, post-processing can be performed on an output of one or more inference tasks or other processing tasks of a pipeline in order to prepare output data for a next application and / or to prepare output data for transmission and / or use by a user (e.g. B. in response to an inference request). In at least one embodiment, inference tasks can be performed by one or more models of machine learning, such as trained or deployed neural networks, the output models 3816 of the training system 3804 may include.

In at least one embodiment, the tasks of the data processing pipeline can be encapsulated in a container (s), each of which represents a discrete, fully functional instantiation of an application and a virtualized computing environment that is able to refer to models of machine learning. In at least one embodiment, containers or applications can be published in a private (e.g., restricted access) area of a container registration database (described in greater detail herein) and trained or deployed models can be stored in the model registration database 3824 saved and associated with one or more applications. In at least one embodiment, images of applications (e.g., container images) can be available in a container registry, and once selected by a user from a container registry for use in a pipeline, an image can be used to create a container for instantiation an application for use by a user's system.

In at least one embodiment, developers (e.g. software developers, clinicians, doctors, etc.) can develop, publish and store applications (e.g. as containers) for performing image processing and / or inference on supplied data. In at least one embodiment, development, publication, and / or storage may be performed using a software development kit (SDK) associated with a system (e.g., to ensure that a developed application and / or a developed container is compliant or compatible with a system). In at least one embodiment, an application that is being developed can be checked locally (e.g., at a first facility, on data from a first facility) with an SDK that includes at least some of the services 3820 as a system (e.g. system 3900 out 39 ) can support. Because DICOM objects can contain between one and hundreds of images or other types of data, and because of a variation in the data, in at least one embodiment a developer can use for management (e.g., setting constructs for, building preprocessing into a Application etc.) be responsible for the extraction and preparation of incoming DICOM data. In at least one embodiment, an application can once it through the system 3900 validated (e.g. for accuracy, security, patient privacy, etc.), be available in a container registry for selection and / or implementation by a user (e.g., hospital, clinic, laboratory, healthcare provider, etc.) to perform one or more processing tasks related to data in a device (e.g., a second device) of a user.

In at least one embodiment, developers can then network applications or containers for access and use by users of a system (e.g., the system 3900 out 39 ) divide. In at least one embodiment, closed and validated applications or containers can be stored in a container registration database, and machine learning models associated therewith can be stored in the model registration database 3824 get saved. In at least one embodiment, a requesting entity (e.g., a user in a medical facility) - providing an inference or image processing request - may have a container registration database and / or a model registration database 3824 Search for an application, container, data set, machine learning model, etc., select a desired combination of items to include in the data processing pipeline, and submit an image processing request. In at least one embodiment, a request may include input data (and patient data associated therewith in some examples) necessary to complete a request and / or a selection of machine learning application (s) and / or models that are used in the processing a request should be executed. In at least one embodiment, a request can then be made to one or more components of the deployment system 3806 (e.g. a cloud) to perform the processing of the data processing pipeline. In at least one embodiment, processing by the deployment system 3806 referencing selected elements (e.g. applications, containers, models, etc.) from a container registration database and / or model registration database 3824 include. In at least one embodiment, once results have been generated by a pipeline, the results may be returned to a user for reference (e.g., for viewing in a viewing application suite running on a local workstation or terminal on the premises). In at least one embodiment, a radiologist may receive results from a data processing pipeline that includes any number of applications and / or containers, where the results may include abnormality detection in x-rays, CT scans, MRIs, and so on.

In at least one embodiment, to support the processing or execution of applications or containers in pipelines, the services 3820 be exploited. In at least one embodiment, the services 3820 Include computing services, artificial intelligence (AI) services, visualization services, and / or other types of services. In at least one embodiment, the services 3820 provide functionality that one or more applications in the software 3818 have in common so that the functionality can be abstracted into a service that can be called or used by applications. In at least one embodiment, the services 3820 The functionality provided runs dynamically and more efficiently, while it is also easily scalable by allowing applications to process data in parallel (e.g. using a parallel computing platform 3930 ( 39 )). Instead of having every application that shares the same functionality that is provided by a service 3820 is offered a corresponding instance of the service 3820 must have, the service can 3820 be shared by different applications in at least one embodiment. In at least one embodiment, the services may include an inference server or engine that, as non-limiting examples, may be used to perform detection or segmentation tasks. In at least one embodiment, a model training service may be included that may provide the ability to train and / or retrain models of machine learning. In at least one embodiment, a data expansion service can also be included that enables the extraction, resizing, scaling and / or other expansion of GPU-accelerated data (e.g. DICOM data, RIS data, CIS data, REST-compliant data, RPC data, raw data, etc.). In at least one embodiment, a visualization service can be used that can add image rendering effects - such as ray tracing, rasterization, noise reduction, sharpening, etc. - to make two-dimensional (2D) and / or three-dimensional (3D) models more realistic. In at least one embodiment, virtual instrument services may be included that provide beamforming, segmentation, inferencing, imaging, and / or support for other applications within virtual instrument pipelines.

In at least one embodiment in which a service 3820 includes an AI service (e.g., an inference service), one or more machine learning models associated with an anomaly detection application (e.g., tumors, growth abnormalities, scarring, etc.) can be executed using a Inference service (e.g. an inference server) is called (e.g. as an API call) to execute machine learning model (s) or to process them as part of application execution. In at least one embodiment where another application includes one or more machine learning models for segmentation tasks, an application can invoke an inference service to execute machine learning models for performing one or more processing operations associated with segmentation tasks. In at least one embodiment, the software 3818 who implements an advanced processing and inference pipeline that includes a segmentation application and includes an anomaly detection application, since each application can invoke a same inference service to perform one or more inference tasks.

In at least one embodiment, the hardware 3822 Include GPUs, CPUs, graphics cards, an AI / deep learning system (e.g. an AI supercomputer such as NVIDIA's DGX supercomputer system), a cloud platform, or a combination thereof. In at least one embodiment, different types of hardware 3822 used to provide efficient, purpose-built support for software 3818 and services 3820 in the deployment system 3806 provide. In at least one embodiment, GPU processing can be used for local processing (e.g., at the facility 3802 ), within an AI / deep learning system, in a cloud system and / or in other processing components of the deployment system 3806 can be implemented to improve the efficiency, accuracy and effectiveness of image processing, image reconstruction, segmentation, MRI exams, stroke or heart attack detection (e.g. in real time), image quality when rendering, etc. In at least one embodiment, a facility may include imaging devices, genomics devices, sequencing devices, and / or other types of devices on the premises that GPUs can exploit to generate imaging data representative of a subject's anatomy.

In at least one embodiment, the software 3818 and / or the services 3820 be optimized as non-limiting examples of GPU processing in relation to deep learning, machine learning, and / or high-computational computing. In at least one embodiment, at least part of the computing environment of the deployment system 3806 and / or the training system 3804 be executed in a data center on one or more supercomputers or computing systems with high computing power with GPU-optimized software (e.g. hardware and software combination of the DGX system from NVIDIA). In at least one embodiment, data centers may be compliant with HIPAA regulations so that the receipt, processing, and transmission of imaging data and / or other patient data are safely handled with regard to the protection of patient data. In at least one embodiment, the hardware 3822 include any number of GPUs that can be invoked to process data in parallel as described herein. In at least one embodiment, the cloud platform can further include GPU processing for GPU-optimized execution of deep learning tasks, machine learning tasks, or other computing tasks. In at least one embodiment, the cloud platform (e.g., NGC from NVIDIA) can be configured using AI / deep learning supercomputer (s) and / or GPU-optimized software (e.g., such as on DGX systems from NVIDIA provided) as a hardware abstraction and scaling platform. In at least one embodiment, the cloud platform can integrate an application container clustering system or orchestration system (e.g. KUBERNETES) on multiple GPUs to enable seamless scaling and load sharing.

39 is a system diagram for an exemplary system 3900 for creating and deploying an imaging deployment pipeline in accordance with at least one embodiment. In at least one embodiment, the system 3900 used to the process 3800 out 38 and / or implement other processes, including advanced processing and inference pipelines. In at least one embodiment, the system 3900 the training system 3804 and the deployment system 3806 include. In at least one embodiment, the training system 3804 and the deployment system 3806 using software 3818 , Services 3820 and / or hardware 3822 as described herein.

In at least one embodiment, the system 3900 (e.g. the training system 3804 and / or the deployment system 3806 ) be implemented in a cloud computing environment (e.g. using the cloud 3926 ). In at least one embodiment, the system 3900 implemented locally in relation to a healthcare facility or as a combination of both cloud and local computing resources. In at least one embodiment, in embodiments in which cloud computing is implemented, patient data from one or more components of the system 3900 processed separately or not through them, which would make the processing non-compliant with HIPAA and / or other data handling and privacy regulations or laws. In at least one embodiment, access to the APIs can be in the cloud 3926 restricted to authorized users by security measures or protocols in place. In at least one embodiment, a security protocol can contain web tokens that can be signed by an authentication service (e.g. AuthN, AuthZ, Gluecon, etc.) and can carry appropriate authorization. In at least one embodiment, APIs from virtual instruments (described herein) or other instantiations of the system 3900 Be limited to a set of public IPs that have been security cleared or authorized to interact.

In at least one embodiment, various components of the system 3900 communicate with one another using any of a variety of different network types including, but not limited to, local area networks (LANs) and / or wide area networks (WANs) via wired and / or wireless communication protocols. In at least one embodiment, the communication between devices and components of the system 3900 (e.g. for transmitting inference requests, receiving results of inference requests, etc.) via a data bus or buses, wireless data protocols (Wi-Fi), wired data protocols (e.g. Ethernet), etc.

In at least one embodiment, the training system 3804 Training pipelines 3904 similar to those described herein with respect to 38 are described. In at least one embodiment in which one or more machine learning models in deployment pipelines 3910 through the deployment system 3806 training pipelines can be used 3904 can be used to train or retrain one or more (e.g. pre-trained) models and / or one or more of the pre-trained models 3906 to implement (e.g. without the need for retraining or updating). In at least one embodiment, as a result of the training pipelines 3904 Output model (s) 3816 be generated. In at least one embodiment, the training pipelines 3904 any number of processing steps include, for example, but not limited to, converting or adapting imaging data (or other input data) (e.g., using a DICOM adapter 3902A for converting DICOM images to another format suitable for processing by respective machine learning models, such as the Neuroimaging Informatics Technology Initiative (NIfTI) format, AI-assisted annotation 3810 , Labeling or annotation of imaging data 3808 to get labeled clinic data 3812 to generate, model selection from a model registration database, model training 3814 , Training, retraining or updating models and / or other processing steps. In at least one embodiment, different machine learning models implemented by the deployment system 3806 different training pipelines are used 3904 be used. In at least one embodiment, a training pipeline can be used for a first machine learning model 3904 which is similar to a first example related to FIG 38 is described, a training pipeline for a second model of machine learning 3904 which is similar to a second example relating to 38 and for a third machine learning model, a training pipeline 3904 which is similar to a third example related to FIG 38 is described. In at least one embodiment, any combination of tasks within the training system 3804 can be used, depending on what is required for each particular machine learning model. In at least one embodiment, one or more of the machine learning models may already be trained and ready for use such that the machine learning models may not be processed by the training system 3804 are subjected to and through the deployment system 3806 can be implemented.

In at least one embodiment, the output model (s) 3816 and / or the previously trained model (s) 3906 include any type of machine learning model, depending on the implementation or embodiment. In at least one embodiment and without limitation, the system 3900 Machine learning models used Machine learning model (s) using linear regression, logistic regression, decision trees, support vector machines (SVM), naive Bayesian classifier, k-nearest neighbor (Knn), k-means clustering, random forest, dimension reduction algorithms, gradient amplification algorithms, neural networks (e.g. autocoders, folding, recurrent, perceptrons, long / short term memory (LSTM), Hopfield, Boltzmann, deep belief, unfolding, generating adversarial, liquid state machine, etc.) and / or other types of machine learning models.

In at least one embodiment, the training pipelines 3904 Include AI-assisted annotation, as herein referred to at least 42B described in more detail. In at least one embodiment, labeled clinical data 3812 (e.g. conventional annotation) can be generated by any number of techniques. In at least one embodiment, labels or other annotations can be used within a drawing program (e.g. an annotation program), a program for computer-aided design (CAD), a labeling program, a other type of program suitable for generating annotations or labels for Ground Truth, and / or, in some examples, hand-drawn. In at least one embodiment, the ground truth data can be produced synthetically (e.g. generated from computer models or renderings), actually produced (e.g. designed and produced from data from the real world), machine-automated (e.g. under Using feature analysis and learning to extract features from data and then create labels), human annotated (e.g., a labeler or annotation expert defines the location of labels), and / or a combination thereof. In at least one embodiment, for each instance of the imaging data 3808 (or some other type of data used by machine learning models) there must be corresponding ground truth data that is present by the training system 3804 be generated. In at least one embodiment, the AI-based annotation can be used as part of the deployment pipelines 3910 be performed; either in addition to or instead of the AI-supported annotation in the training pipelines 3904 is included. In at least one embodiment, the system 3900 contain a multi-tier platform that includes a software tier (e.g. software 3818 ) of diagnostic applications (or other types of applications) that can perform one or more medical imaging and diagnostic functions. In at least one embodiment, the system 3900 be communicatively coupled to (e.g. via encrypted links) PACS server networks of one or more facilities. In at least one embodiment, the system 3900 be configured in such a way that it accesses and references data (e.g. DICOM data, RIS data, raw data, CIS data, REST-compliant data, RPC data, raw data, etc.) from PACS servers (e.g. E.g. via a DICOM adapter 3902 or an adapter for another data type such as RIS, CIS, RESTful, RPC, raw data, etc.) to perform operations such as training machine learning models, deploying machine learning models, image processing, inferencing and / or other operations.

In at least one embodiment, a software layer can be implemented as a secure, encrypted and / or authenticated API, by the applications or containers from an external environment (s) (e.g. facility 3802 ) can be selected (e.g. called up). In at least one embodiment, applications can then have one or more services 3820 invoke or execute to perform computation, AI, or visualization tasks associated with respective applications and the software 3818 and / or the services 3820 can the hardware 3822 to perform processing tasks in an effective and efficient manner.

In at least one embodiment, the deployment system 3806 Deployment pipelines 3910 To run. In at least one embodiment, feed pipelines 3910 include any number of applications that can be sequentially, non-sequentially, or otherwise applied to imaging data (and / or other types of data) generated by imaging devices, sequencing devices, genomics devices, etc. - including AI-assisted annotation, as described above . In at least one embodiment, as described herein, a deployment pipeline 3910 for a single device can be referred to as a virtual device for a device (e.g., a virtual ultrasound instrument, a virtual CT scan instrument, a virtual sequencing instrument, etc.). In at least one embodiment, more than one deployment pipeline may be used for a single device depending on information desired from data generated by a device 3910 to be available. If it is desired to detect anomalies using an MRI machine, in at least one embodiment a first deployment pipeline can be used 3910 and if image enhancement based on output from an MRI machine is desired, a second deployment pipeline may be required 3910 to be available.

In at least one embodiment, the feed pipelines 3910 Available applications include any application that can be used to perform processing tasks on imaging data or other data from devices. In at least one embodiment, different applications can be responsible for image enhancement, segmentation, reconstruction, anomaly detection, object detection, feature detection, treatment planning, dosimetry, radiation planning (or other radiation treatment procedures) and / or other analysis, image processing or inference tasks. In at least one embodiment, the deployment system 3806 Define constructs for each of the applications so that the users of the deployment system 3806 (e.g. medical facilities, laboratories, clinics, etc.) understand the constructs and be able to adapt the applications for implementation within their respective facility. In at least one embodiment, an image reconstruction application for inclusion in the deployment pipeline 3910 can be selected, but the type of data generated by an imaging device may be different from a type of data used within an application. In at least one embodiment, the DICOM adapter 3902B (and / or a DICOM Reader) or an adapter or reader for another data type (e.g. RIS, CIS, REST-compliant, RPC, raw data, etc.) within the deployment pipeline 3910 used to convert data into a form that can be used by an application within the deployment system 3806 can be used. In at least one embodiment, access to libraries with DICOM data, RIS data, CIS data, RESTful data, RPC data, raw data and / or other data types can be accumulated and preprocessed, including decoding, extracting and / or Performing convolution, color correction, sharpness, gamma and / or other extensions of the data. In at least one embodiment, DICOM data, RIS data, CIS data, RESTful data, RPC data, and / or raw data can be out of order and preprocessed to organize or sort collected data. Since, in at least one embodiment, different applications may share image operations, in some embodiments a data expansion library (e.g., as one of the services 3820 ) can be used to speed up these operations. In at least one embodiment, to avoid bottlenecks in traditional processing approaches that rely on CPU processing, the parallel computing platform 3930 can be used to accelerate these processing tasks through the GPU.

In at least one embodiment, an image reconstruction application may include a processing task that includes using a machine learning model. In at least one embodiment, a user may wish to use their own machine learning model or a machine learning model from the model registration database 3824 want to choose. In at least one embodiment, a user can implement their own machine learning model or select a machine learning model for inclusion in an application to perform a processing task. In at least one embodiment, the applications can be selectable and individually adaptable, and by defining constructs of applications, the use and implementation of applications are presented as a more seamless user experience for a specific user. In at least one embodiment, feed pipelines 3910 by taking advantage of other features of the system 3900 - such as the services 3820 and the hardware 3822 - Be even more user-friendly, provide easier integration and produce more accurate, efficient and faster results.

In at least one embodiment, the deployment system 3806 a user interface 3914 (e.g., a graphical user interface, a web interface, etc.) that can be used to select applications for inclusion in the deployment pipeline (s) 3910, arrange applications, modify or change applications or parameters or constructs thereof, use and interact with the deployment pipeline (s) 3910 during setup and / or deployment and / or otherwise with the deployment system 3806 to interact. In at least one embodiment, although not related to the training system 3804 illustrates the user interface 3914 (or other user interface) for selecting models for use in the deployment system 3806 to select models for training or retraining in the training system 3804 and / or to otherwise interact with the training system 3804 be used.

In at least one embodiment, the pipeline manager 3912 in addition to an application orchestration system 3928 used to facilitate the interaction between the applications or containers of the deployment pipeline (s) 3910 and the services 3820 and / or the hardware 3822 manage. In at least one embodiment, the pipeline manager 3912 be configured to allow application-to-application, application-to-service interactions 3820 and / or from application or service to hardware 3822 facilitated. Though it's illustrative in the software 3818 is included, in at least one embodiment this is not intended to be limiting and in some examples (such as in 40 illustrated) the pipeline manager 3912 in the services 3820 be included. In at least one embodiment, the application orchestration system 3928 (e.g. Kubernetes, DOCKER, etc.) contain a container orchestration system that can group applications into containers as logical units for coordination, management, scaling and deployment. In at least one embodiment, by associating applications from the deployment pipeline (s) 3910 (e.g., a reconstruction application, a segmentation application, etc.) with individual containers, each application in a self-contained environment (e.g., at the kernel level ) to increase speed and efficiency.

In at least one embodiment, each application and / or container (or an image thereof) can be developed, modified and deployed individually (e.g., a first user or developer can develop, modify and deploy a first application and a second user or developer can develop, modify and deploy a first application develop, modify and deploy a second application separately from a first user or developer), which may make it possible to focus on a task of a single application and / or container (s) to focus and concentrate without being hindered by the tasks of another application (s) or another container (s). In at least one embodiment, the communication and cooperation between different containers or applications can be carried out by the pipeline manager 3912 and the application orchestration system 3928 get supported. In at least one embodiment, as long as an expected input and / or output of each container or application is known to a system (e.g., based on constructs of applications or containers), the application orchestration system can 3928 and / or the pipeline manager 3912 facilitate communication among and between each of the applications or containers and the sharing of resources among and between them. Because one or more applications or containers in the deployment pipeline (s) 3910 can share the same services and resources, the application orchestration system 3928 in at least one embodiment, orchestrate the shared use of services or resources between and among different applications or containers, and distribute and determine their load. In at least one embodiment, a planner can be used to track the resource requirements of applications or containers, the current usage or planned usage of these resources, and the resource availability. In at least one embodiment, a planner can thus assign resources to different applications and distribute resources between and among applications with regard to the needs and availability of a system. In some examples, a planner (and / or another component of the application orchestration system 3928 ) Determine resource availability and distribution based on restrictions imposed on a system (e.g. user restrictions) such as quality of service (QoS), urgency of the need for data outputs (e.g. to determine whether real-time processing or delayed Processing is to be carried out) etc.

In at least one embodiment, the services 3820 created by applications or containers in the deployment system 3806 exploited and shared, computing services 3916 , AI services 3918 , Visualization services 3920 and / or other types of services. In at least one embodiment, applications can use one or more of the services 3820 invoke (e.g. execute) to perform processing operations on an application. In at least one embodiment, the computing services 3916 can be exploited by applications to perform supercomputing or other high-performance computing (HPC) tasks. In at least one embodiment, the computing service (s) 3916 can be used for parallel processing (e.g. using a parallel computing platform 3930 ) to process data by one or more applications and / or to perform one or more tasks of a single application essentially simultaneously. In at least one embodiment, the parallel computing platform 3930 (e.g. CUDA from NVIDIA) Enable universal data processing on GPUs (GPGPU) (e.g. GPUs 3922 ). In at least one embodiment, a software layer of the parallel computing platform 3930 Provide access to virtual instruction sets and parallel compute elements of GPUs for the execution of compute kernels. In at least one embodiment, the parallel computing platform 3930 Include memory, and in some embodiments, memory may be shared between and among multiple containers and / or between and among different processing tasks within a single container. In at least one embodiment, calls for inter-process communication (IPC) can be generated for several containers and / or for several processes within a container in order to retrieve the same data from a shared memory segment of the parallel computing platform 3930 (e.g. when several different levels of an application or several applications process the same information). In at least one embodiment, the same data in the same storage location can be used for any number of processing tasks (e.g., at the same time, at different times, etc.) rather than making a copy of the data and moving the data to different locations move in memory (e.g., a read / write operation). In at least one embodiment, since data is used to create new data as a result of the processing, that information can be stored about a new location of data and shared between different applications. In at least one embodiment, a location of data and a location of updated or modified data can be part of a definition of how user data is to be understood within containers.

In at least one embodiment, the AI services 3918 can be exploited to perform inference services for executing machine learning model (s) associated with applications (e.g. charged with performing one or more processing tasks of an application). In at least one embodiment, the AI services 3918 the AI system 3924 exploit machine learning model (s) (e.g., neural networks such as CNNs) for segmentation, reconstruction, object detection, feature detection, classification and / or other inference tasks. In at least one embodiment, the applications of the deployment pipeline (s) 3910 one or more of the output models 3816 from the training system 3804 and / or use other models of applications to Perform inference on imaging data (e.g. DICOM data, RIS data, CIS data, RESTful data, RPC data, raw data, etc.). In at least one embodiment, two or more examples of inferencing using the application orchestration system 3928 (e.g. a planner) must be available. In at least one embodiment, a first category can include a high priority / low latency path that can achieve higher service level agreements, such as inferring urgent requests during an emergency or for a radiologist during diagnosis. In at least one embodiment, a second category can include a standard priority path that can be used for requests that are not urgent or where analysis can be performed at a later time. In at least one embodiment, the application orchestration system 3928 Resources (e.g. services 3820 and / or hardware 3822 ) based on priority paths for different inference tasks of the AI services 3918 distribute.

In at least one embodiment, the shared data store can be used with the AI services 3918 within the system 3900 be connected. In at least one embodiment, the shared data store can act as a cache (or other type of storage device) and can be used to process inference requests from applications. In at least one embodiment, when an inference request is sent, a request can be made through a set of API instances of the deployment system 3806 and one or more instances can be selected (e.g., best fit, load balancing, etc.) to process a request. In at least one embodiment, a request can be entered into a database to process a request, a machine learning model can be obtained from the model registration database 3824 if it is not already in a cache, a validation step can ensure that an appropriate machine learning model is loaded into a cache (e.g. a shared data store), and / or a copy of a model can be stored in saved in a cache. In at least one embodiment, a planner (e.g., the pipeline manager 3912 ) can be used to start an application referenced in a request if an application is not already running or if there are not enough instances of an application. In at least one embodiment, an inference server can be started if an inference server for running a model has not already been started. In at least one embodiment, any number of inference servers can be started per model. In at least one embodiment, models can be cached in a pull model in which inference servers are clustered whenever load distribution is advantageous. In at least one embodiment, inference servers can be statically loaded into corresponding, distributed servers.

In at least one embodiment, the inference can be performed using an inference server that runs in a container. In at least one embodiment, an instance of an inference server can be associated with a model (and optionally a plurality of versions of a model). In at least one embodiment, if an instance of an inference server does not exist when a request to perform an inference on a model is received, a new instance can be loaded. In at least one embodiment, when an inference server is started, a model can be transferred to an inference server, so that the same container can be used to service different models as long as the inference server is running as a different entity.

In at least one embodiment, an inference request for a given application can be received during application execution and a container (e.g. hosting an instance of an inference server) loaded (if not already done) and a start procedure invoked. In at least one embodiment, preprocessing logic in a container can load and decode incoming data and / or perform any additional preprocessing on it (e.g. using CPU (s) and / or GPU (s)). In at least one embodiment, once the data is prepared for inference, a container can inference the data as needed. In at least one embodiment, this may include a single inference call on an image (e.g., a hand x-ray) or require inference on hundreds of images (e.g., a chest CT). In at least one embodiment, an application may summarize results before closing, which may include, without limitation, a single confidence score, segmentation at pixel level, segmentation at voxel level, generating a visualization, or generating text to summarize findings. In at least one embodiment, different models or applications can be assigned different priorities. For example, some models may have real-time priority (TAT less than a minute) while others may have a lower priority (e.g., TAT less than 10 minutes). In at least one embodiment, the model execution times can vary from the requesting institution or entity are measured and include the time for the traversal of the partner network as well as the execution on an inference service.

In at least one embodiment, the transmission of requests between the services 3820 and hidden from inference applications behind a software development kit (SDK) and robust transport provided through a queue. In at least one embodiment, a request is queued through an API for a single application / tenant ID combination and an SDK queues a request and issues a request to an application. In at least one embodiment, a name of a queue can be provided in an environment from which an SDK picks it up. In at least one embodiment, asynchronous communication through a queue can be useful as it can allow any instance of an application to start working as soon as it becomes available. In at least one embodiment, the results can be passed back through a queue to ensure that no data is lost. In at least one embodiment, queues can also provide a capability to segment work, since highest priority work can go to a queue that most instances of an application are connected to, while lowest priority work can go to a queue that only a single instance is connected that processes tasks in the order in which they are received. In at least one embodiment, an application can run on a GPU-accelerated instance that is in the cloud 3926 has been generated and an inference service can perform the inference on a GPU.

In at least one embodiment, the visualization services 3920 can be used to create visualizations for viewing outputs from applications and / or deployment pipeline (s) 3910 to create. In at least one embodiment, the GPUs can 3922 through the visualization services 3920 can be used to generate visualizations. In at least one embodiment, rendering effects, such as ray tracing, can be performed by the visualization services 3920 implemented to produce higher quality visualizations. In at least one embodiment, visualizations can include, without limitation, 2D image renderings, 3D volume renderings, 3D volume reconstructions, 2D tomography slices, virtual reality displays, augmented reality displays, and so on. In at least one embodiment, virtualized environments can be used to create a virtual interactive display or environment (e.g., a virtual environment) for interaction by users of a system (e.g., doctors, nurses, radiologists, etc.). In at least one embodiment, the visualization services 3920 include an internal visualizer, kinematics, and / or other rendering or image processing capabilities or functions (e.g. ray tracing, rasterization, internal optics, etc.).

In at least one embodiment, the hardware 3822 GPUs 3922 , the AI system 3924 , the cloud 3926 and / or any other hardware required to run the training system 3804 and / or the deployment system 3806 is used. In at least one embodiment, the GPUs can 3922 (e.g. TESLA and / or QUADRO GPUs from NVIDIA) contain any number of GPUs that are used to perform processing tasks of computing services 3916 , AI services 3918 , Visualization services 3920 , other services, and / or any of features or functions of the software 3818 can be used. In terms of the AI services 3918 can the GPUs 3922 for example, to perform preprocessing on imaging data (or other types of data used by machine learning models), post-processing on outputs of the machine learning models, and / or to perform inference (e.g., to run machine learning models ) be used. In at least one embodiment, the cloud 3926 , the AI system 3924 and / or other components of the system 3900 the GPUs 3922 use. In at least one embodiment, the cloud 3926 Include a GPU-optimized platform for deep learning tasks. In at least one embodiment, the AI system can 3924 Use GPUs and the cloud 3926 - or at least one section charged with deep learning or inferencing - can be done using one or more AI systems 3924 are executed. Although the hardware 3822 Discrete components as illustrated, accordingly are not intended to be limiting, and arbitrary components of the hardware 3822 can work with any other hardware component 3822 combined or exploited by them.

In at least one embodiment, the AI system can 3924 Include a specially designed computing system (e.g., a supercomputer or an HPC) configured for inference, deep learning, machine learning, and / or other artificial intelligence tasks. In at least one embodiment, the AI system can 3924 (e.g. DGX from NVIDIA) Include GPU-optimized software (e.g. a software stack) that utilizes a variety of GPUs 3922 in addition to CPUs, RAM, Data storage and / or other components, features or functions can be executed. In at least one embodiment, one or more AI systems 3924 in the cloud 3926 (e.g. in a data center) may be implemented to handle some or all of the AI-based processing tasks of the system 3900 perform.

In at least one embodiment, the cloud 3926 Include a GPU-accelerated infrastructure (e.g., NGC from NVIDIA) that provides a GPU-optimized platform for performing system processing tasks 3900 can provide. In at least one embodiment, the cloud 3926 an AI system (s) 3924 to perform one or more AI-based tasks of the system 3900 (e.g. as a hardware abstraction and scaling platform). In at least one embodiment, the cloud 3926 into the application orchestration system 3928 integrated that takes advantage of multiple GPUs for seamless scaling and load sharing between and among applications and services 3820 to enable. In at least one embodiment, the cloud 3926 be tasked with at least some of the services 3820 of the system 3900 perform, including computing services 3916 , the AI services 3918 and / or the visualization services 3920 as described herein. In at least one embodiment, the cloud 3926 Perform inference on small and large batches (e.g. running TENSOR RT from NVIDIA), deploy an accelerated parallel computing API and platform 3930 (e.g. CUDA from NVIDIA), an application orchestration system 3928 execute (e.g. KUBERNETES), provide a graphics rendering API and platform (e.g. for ray tracing, 2D graphics, 3D graphics and / or other rendering techniques to generate higher quality kinematics) and / or it can perform other functions for the system 3900 provide.

In at least one embodiment, the cloud 3926 In an effort to maintain the confidentiality of patient data (e.g., if patient data or files are to be used off-premises), include a registry - such as a deep learning container registry. In at least one embodiment, a registration database can store containers for instantiations of applications that can perform preprocessing, postprocessing, or other processing tasks on patient data. In at least one embodiment, the cloud 3926 Receive data that contain patient data as well as sensor data in containers, perform the requested processing only for the sensor data in these containers and then forward a resulting output and / or visualizations to appropriate parties and / or devices (e.g. medical devices in the premises, used for visualization or diagnosis) without the need to extract, save or otherwise access patient data. In at least one embodiment, patient data confidentiality is maintained in accordance with HIPAA and / or other data regulations.

In at least one embodiment, a neural network trained with images transformed using aspects that correspond to domain differences could using the system 3900 implemented.

40 includes an exemplary illustration of a deployment pipeline 3910A for processing imaging data according to at least one embodiment. In at least one embodiment, the system 3900 - and especially the deployment system 3806 - used to build the deployment pipeline (s) 3910A customize, update and / or integrate into one or more production environments. In at least one embodiment, the deployment pipeline includes 3910A out 40 is one non-limiting example of a deployment pipeline 3910A which can be individually defined by a specific user (or a team of users) in an institution (e.g. in a hospital, clinic, laboratory, research setting, etc.). In at least one embodiment, a user can define deployment pipelines 3910A for a CT scanner 4002 - for example from a container registry - select one or more applications that have specific functions or tasks related to the CT scanner 4002 perform generated imaging data. In at least one embodiment, applications can access the deployment pipeline 3910A to be used as a container that provides the services 3820 and / or hardware 3822 of the system 3900 can take advantage of. In addition, the deployment pipeline 3910A Include additional processing tasks or applications that can be implemented to prepare data for use by applications (e.g., the DICOM adapter 3902B and a DICOM reader 4006 in the pipeline 3910A used to compile data for use by a CT reconstruction 4008 , an organ segmentation 4010 etc.). In at least one embodiment, the deployment pipeline 3910A be customized or selected for consistent use, one-time use, or a different frequency or interval. In at least one embodiment, a user can perform the CT reconstruction 4008 and the organ segmentation 4010 want for several subjects over a specific interval and therefore the pipeline 3910A use for this period. In at least one embodiment, for each request from the system, a user can 3900 select the applications that a user would like to perform processing on that data for that request. In at least one embodiment, the deployment pipeline 3910A can be set in any interval and due to the adaptability and scalability of a container structure within the system 3900 this can be a seamless process.

In at least one embodiment, the deployment pipeline 3910A out 40 a CT scanner 4002 for generating imaging data of a patient or test person. In at least one embodiment, the imaging data can be from the CT scanner 4002 on a PACS server (s) 4004 associated with a facility in which the CT scanner 4002 is located. In at least one embodiment, the PACS server can 4004 Include software and / or hardware components associated with the imaging modalities (e.g. the CT scanner 4002 ) can form a direct interface in a facility. In at least one embodiment, the DICOM adapter 3902B enable sending and receiving of DICOM objects using DICOM protocols. In at least one embodiment, the DICOM adapter 3902B when preparing or configuring DICOM data from PACS server (s) 4004 for use by the deployment pipeline 3910A help. In at least one embodiment, the pipeline manager 3912 Data to the deployment pipeline 3910A route through as soon as DICOM data passes through the DICOM adapter 3902B are processed. In at least one embodiment, the DICOM reader can 4006 Extract image files and any associated metadata from DICOM data (e.g. raw sinogram data, as in the visualization 4016A illustrated). In at least one embodiment, work files that are extracted may be cached for faster processing by other applications in the deployment pipeline 3910A to enable. In at least one embodiment, once the DICOM reader 4006 has finished extracting and / or storing data, a completion signal to the pipeline manager 3912 be communicated. In at least one embodiment, the pipeline manager 3912 then one or more other applications or containers in the deployment pipeline 3910A initiate or call.

In at least one embodiment, the application and / or the container for the CT reconstruction 4008 are executed as soon as data (e.g. raw sinogram data) is available for processing by the application for CT reconstruction 4008 Are available. In at least one embodiment, the CT reconstruction 4008 Read sinogram raw data from a cache, reconstruct an image file from the sinogram raw data (e.g. in the visualization 4016B illustrated) and cache the resulting image file. In at least one embodiment, upon completion of the reconstruction, the pipeline manager 3912 signaled that the reconstruction task has been completed. In at least one embodiment, once the reconstruction is complete and a reconstructed image file can be stored in a cache (or other storage device), the organ segmentation application and / or container can be used 4010 by the pipeline manager 3912 to be triggered. In at least one embodiment, the application and / or the container can be used for organ segmentation 4010 read an image file from a cache, normalize an image file or convert it to a format suitable for inference (e.g. convert an image file to an input resolution of a machine learning model), and perform inference against a normalized image. In order to perform inference on a normalized image, the application and / or the container for organ segmentation can be used 4010 in at least one embodiment on the services 3820 support and the pipeline manager 3912 and / or the application orchestration system 3928 can use the services 3820 by the application and / or the container for organ segmentation 4010 facilitate. For example, in at least one embodiment, the application and / or the container for organ segmentation 4010 the AI services 3918 to perform inference on a normalized image and the AI services 3918 can the hardware 3822 (e.g. the AI system 3924 ) take advantage of the AI services 3918 to execute. In at least one embodiment, a result of an inference can be a mask file (such as in the visualization 4016C illustrated), which can be stored in a cache (or other storage device).

In at least one embodiment, once applications processing DICOM data and / or data extracted from DICOM data have completed processing, a signal to the pipeline manager may be provided 3912 be generated. In at least one embodiment, the pipeline manager 3912 then a DICOM writing instrument 4012 to read results from a cache (or other storage device) and convert results to a DICOM format (e.g., DICOM output 4014 ) for use by users at a facility that generated a request. In at least one embodiment, the DICOM output can 4014 then to the DICOM adapter 3902B be transmitted, to the DICOM output 4014 prepare for storage on the PACS server (s) 4004 (e.g. for viewing by a DICOM viewer in a facility). In at least one embodiment, visualizations can be used in response to a request for reconstruction and segmentation 4016B and 4016C and made available to a user for diagnostic, research and / or other purposes.

Although as a consecutive application in the deployment pipeline 3910A Illustrates the uses for CT reconstruction 4008 and organ segmentation 4010 processed in parallel in at least one embodiment. In at least one embodiment, in which the applications are not dependent on one another and data is available for each application (e.g. after the DICOM reader 4006 Extracted data), applications can run concurrently, substantially concurrently, or with some overlap. In at least one embodiment, two or more applications have similar services 3820 may require a planner of the system 3900 be used for load balancing and for distributing computing or processing resources between and among different applications. In at least one embodiment, the parallel computing platform 3930 to perform parallel processing for applications to be used at the runtime of the deployment pipeline 3910A shorten to deliver results in real time.

In at least one embodiment and with reference to 41A-41B can the deployment system 3806 can be implemented as one or more virtual instruments to implement different functionalities - such as image processing, segmentation, enhancement, AI, visualization and inferencing - with imaging devices (e.g. CT scanners, X-ray machines, MRI machines, etc.), sequencing devices, genomics devices and / or other types of devices. In at least one embodiment, the system 3900 enable the creation and deployment of virtual instruments that have a software-defined deployment pipeline 3910 capable of receiving raw / unprocessed input data generated by a device (s) and outputting processed / reconstructed data. In at least one embodiment, feed pipelines 3910 (e.g. 3910A and 3910B ) that are virtual instruments that implement intelligence in a pipeline, such as by taking advantage of machine learning models to provide containerized inference support to a system. In at least one embodiment, virtual instruments can execute any number of containers, each of which contains instantiations of applications. In at least one embodiment, such as when real-time processing is desired, deployment pipelines 3910 representing virtual instruments may be static (e.g. containers and / or applications may be fixed), while in other examples containers and / or applications for virtual instruments from a pool of applications or resources (e.g. within a container registry k) can be selected (e.g. per requirement).

In at least one embodiment, the system 3900 instantiated or executed as one or more virtual instruments on the premises in a facility, for example in a computing system that is used in addition to a radiology machine, an imaging device and / or another type of device in a facility or is otherwise in communication therewith. In at least one embodiment, however, an installation in the premises within a computing system of a device itself (e.g. a computing system that is integral with an imaging device), in a local data center (e.g. a data center on the premises) and / or in a cloud environment (e.g. in the cloud 3926 ) instantiated or executed. In at least one embodiment, the deployment system 3806 that works as a virtual instrument can, in some examples, be instantiated by a supercomputer or other HPC system. In at least one embodiment, the on-premise installation may enable high bandwidth uses (e.g., via higher throughput local communication interfaces such as RF over Ethernet) for real-time processing. In at least one embodiment, real-time or near real-time processing can be particularly useful when a virtual instrument supports an ultrasound device or other imaging modality where instant visualizations are expected or required for accurate diagnosis and analysis. In at least one embodiment, a cloud computing architecture may be capable of dynamic bursting to a cloud computing service provider or other computing cluster when local demand exceeds local capacity or capability. In at least one embodiment, a cloud architecture, when implemented, can be tailored for training neural networks or other machine learning models, as herein with respect to the training system 3804 described. In at least one embodiment, machine learning models with existing training pipelines can continuously learn and improve as they process additional data from devices that support them. In at least one embodiment, virtual instruments can be created using additional data, new data, existing machine learning models and / or updated machine learning models are continuously improved.

In at least one embodiment, a computing system may include some or all of the hardware described herein 3822 include and the hardware 3822 may be distributed in any of a number of ways, including within a device, as part of a computing device coupled to and in proximity to a device, in a local data center at a facility, and / or in the cloud 3926 . Since the deployment system 3806 and the applications or containers associated therewith are created in software (e.g. as discrete containerized instantiations of applications), the behavior, operation and configuration of virtual instruments and the outputs generated by virtual instruments can be modified as desired in at least one embodiment or customized without having to alter or alter the raw output of a device that supports a virtual instrument.

In at least one embodiment, a neural network trained with images transformed using aspects that correspond to domain differences could using the system 3900 implemented.

41A includes an exemplary data flow diagram of a virtual instrument supporting an ultrasound device, in accordance with at least one embodiment. In at least one embodiment, the deployment pipeline 3910B one or more of the services 3820 of the system 3900 use. In at least one embodiment, the deployment pipeline 3910B and the services 3820 the hardware 3822 of a system either locally or in the cloud 3926 use. In at least one embodiment, although not illustrated, the process 4100 by the pipeline manager 3912 , the application orchestration system 3928 and / or the parallel computing platform 3930 be relieved.

In at least one embodiment, the process 4100 receiving imaging data from an ultrasound device 4102 include. In at least one embodiment, the imaging data can be stored on the PACS server (s) in a DICOM format (or some other format such as RIS, CIS, RESTful, RPC, raw data, etc.) and by the system 3900 for processing through the deployment pipeline 3910 used as a virtual instrument (e.g. a virtual ultrasound) for the ultrasound device 4102 selected or customized. In at least one embodiment, the imaging data can be obtained directly from an imaging device (e.g., ultrasound device 4102 ) and processed by a virtual instrument. In at least one embodiment, a transducer or other signal converter communicatively coupled between an imaging device and a virtual instrument can convert the signal data generated by an imaging device into image data that can be processed by a virtual instrument. In at least one embodiment, raw data and / or image data can be sent to the DICOM reader 4006 applied to data for use by applications or containers in the deployment pipeline 3910B to extract. In at least one embodiment, the DICOM reader can 4006 the data expansion library 4114 (e.g. DALI from NVIDIA) as a service 3820 (e.g. as one of the computing services (s) 3916 ) to extract, resize, rescale, and / or otherwise prepare data for use by applications or containers.

In at least one embodiment, once the data is prepared, an application and / or a container can be used for the reconstruction 4106 run to the data from the ultrasound device 4102 to reconstruct into an image file. In at least one embodiment, after the reconstruction 4106 or simultaneously with the reconstruction 4106 an application and / or a container for detection 4108 for anomaly detection, for object detection, for feature detection and / or for other detection tasks in relation to the data. In at least one embodiment, a 4106 image file generated during detection 4108 used to identify anomalies, objects, features, etc. In at least one embodiment, the application can be for detection 4108 an inference engine 4116 (e.g. as one of the AI service (s) 3918 ) to perform inference on data to generate detections. In at least one embodiment, one or more machine learning models (e.g. from the training system 3804 ) by applying for detection 4108 executed or called.

In at least one embodiment, once the reconstruction 4106 and / or detection 4108 is / are completed, the data output from these applications and / or containers is used to create visualizations 4110 to generate, such as the visualization 4112 (e.g. a Grayscale output) displayed on a workstation or display terminal. In at least one embodiment, the visualization can allow a technician or other user to view the results of the deployment pipeline 3910B in relation to the ultrasonic device 4102 to visualize. In at least one embodiment, the visualization 4110 by taking advantage of a rendering component 4118 of the system 3900 (e.g. one of the visualization services (s) 3920 ) are executed. In at least one embodiment, the rendering component 4118 run a 2D, OpenGL, or ray tracing service to visualize the 4112 to create.

41B includes an exemplary data flow diagram of a virtual instrument supporting a CT scanner, in accordance with at least one embodiment. In at least one embodiment, the deployment pipeline 3910C one or more of the services 3820 of the system 3900 use. In at least one embodiment, the deployment pipeline 3910C and the services 3820 the hardware 3822 of a system either locally or in the cloud 3926 use. In at least one embodiment, although not illustrated, the process 4120 by the pipeline manager 3912 , the application orchestration system 3928 and / or the parallel computing platform 3930 be relieved.

In at least one embodiment, the process 4120 that include the CT scanner 4122 Raw data generated by the DICOM reader 4006 can be received (e.g. directly, via a PACS server 4004 , after processing, etc.). In at least one embodiment, a virtual CT (through the deployment pipeline 3910C instantiated) a first real-time pipeline for monitoring a patient (e.g. patient motion detection AI 4126 ) and / or for setting or optimizing the exposure of the CT scanner 4122 (e.g. using exposure control AI 4124 ) include. In at least one embodiment, one or more of the applications (e.g. 4124 and 4126 ) a service 3820 exploit such as the AI service (s) 3918 . In at least one embodiment, the application (or container) outputs to the exposure control AI 4124 and / or the application (or container) for the patient motion detection AI 4126 as feedback to the CT scanner 4122 and / or a technician can be used to adjust the exposure (or other settings of the CT scanner 4122 ) and / or inform a patient to exercise less.

In at least one embodiment, the deployment pipeline 3910C a non-real-time pipeline for analyzing the data sent by the CT scanner 4122 contain generated data. In at least one embodiment, a second pipeline can be the application and / or the container for the CT reconstruction 4008 , an application and / or a container for a coarse detection AI 4128 , an application and / or a container for a fine detection AI 4132 (e.g. if certain results are obtained by the coarse detection KI 4128 can be detected), an application and / or a container for visualization 4130 and an application and / or a container for the DICOM writing instrument 4012 (and / or a writing device for another data type, such as RIS, CIS, REST-compliant, RPC, raw data, etc.). In at least one embodiment, the can be performed by the CT scanner 4122 generated raw data through pipelines of the operational pipeline 3910C (instantiated as a virtual CT instrument) to generate results. In at least one embodiment, the results can be obtained from the DICOM writer 4012 can be transferred for display and / or stored on the PACS server (s) 4004 for / for later retrieval, analysis or display by a technician, a specialist or another user.

In at least one embodiment, a neural network trained with images transformed using aspects corresponding to domain differences could be performed using the deployment pipeline 41 implemented.

42A Figure 11 illustrates a data flow diagram for a process 4200 for training, retraining, or updating a machine learning model in accordance with at least one embodiment. In at least one embodiment, the process 4200 as a non-limiting example using the system 3900 out 39 are executed. In at least one embodiment, the process 4200 the services 3820 and / or the hardware 3822 of the system 3900 as described herein. In at least one embodiment, refined models 4212 going through the process 4200 generated by the deployment system 3806 for one or more containerized applications in deployment pipelines 3910 are executed.

In at least one embodiment, the model training 3814 retraining or updating an initial model 4204 (e.g. a pre-trained model) using new training data (e.g. new input data, such as the customer data set 4206 , and / or new ground truth data associated with the input data). In at least one embodiment, for retrain or update the initial model 4204 the output or loss layer (s) of the initial model 4204 reset or deleted and / or replaced by updated or new output or loss layer (s). In at least one embodiment, the initial model 4204 already have fine-tuned parameters (e.g. weightings and / or distortions) that are left over from a previous training session, so that the training or the new training 3814 can't take as long or as much processing as training a model from scratch. In at least one embodiment, during model training 3814 by resetting or replacing the output or loss layer (s) of the initial model 4204 the parameters are updated and retuned for a new data set based on loss calculations that match the accuracy of the output or loss layer (s) in generating predictions on a new customer data set 4206 (e.g. image data 3808 out 38 ) are associated.

In at least one embodiment, the previously trained models 3906 in a data store or registry (e.g. the model registry 3824 out 38 ) must be saved. In at least one embodiment, the previously trained models 3906 at least partially in one or more facilities other than the facility running the process 4200 executes, have been trained. In at least one embodiment, the previously trained models can be used to protect the privacy and rights of patients, test subjects or clients from different institutions 3906 have been trained on the premises using customer or patient data generated on the premises. In at least one embodiment, the previously trained models 3906 using the cloud 3926 and / or other hardware 3822 be trained, but confidential, data protection protected patient data may not be transferred to any components of the cloud 3926 (or other hardware outside the own premises), used by them or be accessible to them. In at least one embodiment, in which a previously trained model 3906 is trained using patient data from more than one facility, the pre-trained model 3906 individually trained for each facility before being trained on patient or customer data from another facility. In at least one embodiment, such as when customer or patient data has been exempted from privacy concerns (e.g., by waiver, for experimental use, etc.) or when customer or patient data is included in a public record, customer or Patient data from any number of institutions can be used to create the pre-trained model 3906 to train inside and / or outside of your own premises, such as in a data center or other cloud computing infrastructure.

In at least one embodiment, a user can in selecting applications for use in the deployment pipelines 3910 also select machine learning models to be used for specific applications. In at least one embodiment, a user may not have a model to use, so a user may have a pre-trained model 3906 can select to use with an application. In at least one embodiment, the pre-trained model is 3906 may not be optimized to give accurate results on the customer record 4206 a user's facility (e.g., based on patient diversity, demographics, types of medical imaging devices used, etc.). In at least one embodiment, the previously trained model 3906 before inserting the previously trained model 3906 in the pipeline 3910 updated, retrained, and / or fine-tuned for use with an application (s) for use in a particular facility.

In at least one embodiment, a user can use a pre-trained model 3906 select to be updated, retrained, and / or fine-tuned and the pre-trained model 3906 can be used as an initial model 4204 for the training system 3804 within the process 4200 are designated. In at least one embodiment, the customer record 4206 (e.g., imaging data, genomics data, sequencing data, or other types of data generated by devices in a facility) may be used to perform model training 3814 (which can include transfer learning without restriction) on the initial model 4204 perform to the refined model 4212 to create. In at least one embodiment, the ground truth data belonging to the customer record 4206 through the training system 3804 be generated. In at least one embodiment, ground truth data can be generated at least partially by clinicians, scientists, doctors, specialists in a facility (for example as labeled clinic data 3812 out 38 ).

In at least one embodiment, the AI-assisted annotation 3810 used in some examples to generate ground truth data. In at least one embodiment, the AI-assisted annotation 3810 (e.g. implemented using an SDK for AI-supported annotation) Exploit machine learning models (e.g., neural networks) to generate proposed or predicted ground truth data for a customer record. In at least one embodiment, the user can 4210 Annotation tools within a user interface (a graphical user interface (GUI)) on the computing device 4208 use.

In at least one embodiment, the user can 4210 via the computing device 4208 interact with a GUI to edit or fine-tune annotation or automatic annotation. In at least one embodiment, a polygon editing feature can be used to move vertices of a polygon to more accurate or finer-tuned locations.

In at least one embodiment, once ground truth data with the customer record 4206 are associated with the ground truth data (e.g. from AI-supported annotation, manual labeling, etc.) during model training 3814 by being used to the refined model 4212 to create. In at least one embodiment, the customer record 4206 as often as you want on the initial model 4204 can be applied and the ground truth data used to set the parameters of the initial model 4204 update to an acceptable level of accuracy for the refined model 4212 is reached. In at least one embodiment, the refined model can 4212 once the refined model 4212 is generated within one or more feed pipelines 3910 can be used in a device for performing one or more processing tasks relating to medical imaging data.

In at least one embodiment, the refined model can 4212 into the previously trained models 3906 in the model registration database 3824 uploaded to be selected by another institution. In at least one embodiment, this process can be performed in any number of facilities such that the refined model 4212 can be refined any number of times on new data sets in order to generate a more universal model.

In at least one embodiment, a neural network trained with images transformed using aspects corresponding to domain differences could be performed using a refined model 42 implemented.

42B Figure 3 is an exemplary illustration of a client-server architecture 4232 for expanding annotation tools with previously trained annotation models according to at least one embodiment. In at least one embodiment, the AI-supported annotation tools 4236 based on a client-server architecture 4232 be instantiated. In at least one embodiment, the annotation tools 4236 in imaging applications, for example, support radiologists in identifying organs and abnormalities. In at least one embodiment, imaging applications may include software tools that are useful to the user 4210 A few extreme points on a specific organ of interest on raw images help as a non-limiting example 4234 (e.g. on a 3D MRT or CT scan) and automatically receive annotated results for all 2D slices of a specific organ. In at least one embodiment, the results can be stored in a data memory as training data 4238 stored and used as (for example and without limitation) ground truth data for training. In at least one embodiment, if the computing device 4208 Extreme points for the AI-supported annotation 3810 sends, a deep learning model can receive this data as input, for example, and return inference results from a segmented organ or an abnormality. In at least one embodiment, pre-instantiated annotation tools, such as the AI-supported annotation tool 4236B in 42B , by making API calls (e.g. API call 4244 ) to a server such as an annotation assistant server 4240 , which is a set of pre-trained models 4242 may include, for example, stored in an annotation model registry. In at least one embodiment, an annotation model registration database can include pre-trained models 4242 (e.g. machine learning models such as deep learning models) that are trained in advance to carry out AI-supported annotation on a specific organ or anomaly. In at least one embodiment, these models can be implemented using training pipelines 3904 to be further updated. In at least one embodiment, pre-installed annotation tools can improve over time as new labeled clinic data 3812 to be added.

The inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are herein in connection with 9A and / or 9B provided.

1. 1. Prozessor, umfassend eine oder mehrere Schaltungen, um dabei zu helfen, ein oder mehrere erste neuronale Netze an einem ersten Satz von Bildern unter Verwendung einer oder mehrerer Grafikverarbeitungseinheiten zu trainieren, um ein oder mehrere Objekte innerhalb eines oder mehrerer Bilder eines zweiten Satzes von Bildern zu identifizieren, wobei es sich bei dem ersten Satz von Bildern um Bilder aus einer ersten Domäne handelt, wobei es sich bei dem zweiten Satz von Bildern um Bilder aus einer zweiten Domäne handelt und wobei der erste Satz von Bildern vor dem Trainieren auf Grundlage von erwarteten Unterschieden zwischen der ersten Domäne und der zweiten Domäne transformiert wird.
2. 2. Prozessor nach Satz 1, ferner umfassend ersten Speicher zum Speichern des ersten Satzes von Bildern, einen Transformator zum Transformieren eines ersten Bildes des ersten Satzes von Bildern gemäß einem Bildaspekt, um ein erstes transformiertes Bild zu bilden, und zweiten Speicher zum des ersten transformierten Bildes zur Verwendung beim Trainieren des einen oder der mehreren ersten neuronalen Netze.
3. 3. Prozessor nach Satz 2, wobei der Bildaspekt eines oder mehrere von einem Qualitätsaspekt, einem Aussehensaspekt oder einem Raumkonfigurationsaspekt umfasst.
4. 4. Prozessor nach Satz 3, wobei der Transformator Logik zum Auswählen eines Bildaspektwerts für den Bildaspekt aus einem Bereich von Aspektwerten beinhaltet, die zum Transformieren des ersten Bildes gemäß dem Bildaspekt und dem Bildaspektwert verwendet werden soll.
5. 5. Prozessor nach einem der Sätze 2-4, ferner umfassend Segmentierungsspeicher zum Speichern von Segmentierungsdaten des ersten Bildes.
6. 6. Prozessor nach Satz 5, wobei der Bildaspekt einen Raumkonfigurationsaspekt umfasst und wobei der Transformator das erste Bild gemäß Raumkonfigurationsaspektparametern modifiziert und die Segmentierungsdaten des ersten Bildes gemäß den Raumkonfigurationsaspektparametern modifiziert.
7. 7. Prozessor nach einem der Sätze 2-6, wobei der Bildaspekt einen Raumkonfigurationsaspekt umfasst und wobei das erste Bild ein Volumenbild ist, wobei der Prozessor ferner einen Bildzuschneider umfasst, um das erste Bild in Teilvolumenbilder zuzuschneiden, wobei Teilvolumenbilder separat verarbeitet werden.
8. 8. Prozessor nach Satz 7, wobei der Bildzuschneider ein Zuschneider ist, der innerhalb eines Quaders mit minimaler Oberfläche, der ein 3D-Koordinatengitter enthält, interpoliert.
9. 9. Prozessor, umfassend ein trainiertes neuronales Netz, das eine oder mehrere Grafikverarbeitungseinheiten verwendet, um ein oder mehrere Objekte innerhalb eines oder mehrerer Bilder eines zweiten Satzes von Bildern zu identifizieren, wobei es sich bei dem trainierten neuronalen Netz um ein neuronales Netz handelt, das an einem ersten Satz von Bildern trainiert ist, wobei es sich bei dem ersten Satz von Bildern um Bilder aus einer ersten Domäne handelt, wobei es sich bei dem zweiten Satz von Bildern um Bilder aus einer zweiten Domäne handelt und wobei der erste Satz von Bildern vor dem Trainieren des trainierten neuronalen Netzes auf Grundlage von erwarteten Unterschieden zwischen der ersten Domäne und der zweiten Domäne transformiert wird.
10. 10. Prozessor nach Satz 9, ferner umfassend Speicher für Domänenunterschiedsdaten, die die erwarteten Unterschiede zwischen der ersten Domäne und der zweiten Domäne darstellen, und eine Eingabe des trainierten neuronalen Netzes zum Empfangen der Domänenunterschiedsdaten zum Verwenden in einem Bildverarbeitungsprozess.
11. 11. Prozessor nach Satz 9 oder 10, wobei die erwarteten Unterschiede zwischen der ersten Domäne und der zweiten Domäne einem oder mehreren von einem Qualitätsaspekt, einem Aussehensaspekt oder einem Raumkonfigurationsaspekt entsprechen.
12. 12. Prozessor nach einem der Sätze 9-11, wobei der zweite Satz von Bildern medizinische Bilder umfasst.
13. 13. Prozessor nach Satz 12, wobei es sich bei dem ersten Satz von Bildern um Bilder handelt, die unter Verwendung einer ersten medizinischen Vorrichtung erlangt werden, und es sich bei dem zweiten Satz von Bildern um Bilder handelt, die unter Verwendung einer zweiten medizinischen Vorrichtung erlangt werden, die sich von der ersten medizinischen Vorrichtung unterscheidet.
14. 14. Prozessor nach einem der Sätze 9-13, wobei der erste Satz von Bildern volumetrische Bilder umfasst.
15. 15. Verfahren unter Verwendung einer oder mehrerer Grafikverarbeitungseinheiten zum Verarbeiten von Bildern, umfassend Trainieren eines ersten neuronalen Netzes mit einem ersten Satz von Bildern und Ausgaben, um einem trainierten neuronalen Netz dabei zu helfen, Ausgaben von einem eingegebenen Bild eines zweiten Satzes von Bildern zu inferenzieren, wobei es sich bei dem ersten Satz von Bildern um Bilder aus einer ersten Domäne handelt, wobei es sich bei dem zweiten Satz von Bildern um Bilder aus einer zweiten Domäne handelt und wobei der erste Satz von Bildern vor dem Trainieren auf Grundlage von erwarteten Unterschieden zwischen der ersten Domäne und der zweiten Domäne transformiert wird.
16. 16. Verfahren nach Satz 15, wobei Trainieren des ersten neuronalen Netzes Folgendes umfasst: Erlangen des ersten Satzes von Bildern, der mindestens ein erstes Bild umfasst, Erlangen einer Segmentierung des ersten Bildes, wobei die Segmentierung Grenzen von Objekten darstellt, die in dem ersten Bild abgebildet sind, Bestimmen eines Transformationsaspektparameters, wobei der Transformationsaspektparameter mindestens einem der erwarteten Unterschiede zwischen der ersten Domäne und der zweiten Domäne entspricht, Bestimmen eines Werts des Transformationsaspektparameters, Transformieren des ersten Bildes auf Grundlage des Werts des Transformationsaspektparameters, um ein transformiertes erstes Bild zu bilden, Trainieren des ersten neuronalen Netzes mit dem transformierten ersten Bild.
17. 17. Verfahren nach Satz 16, ferner umfassend Bestimmen, ob das erste Bild im Ganzen unter Verwendung eines Speichers transformiert werden kann, und Zuschneiden des ersten Bildes in eine Vielzahl von Teilvolumina zum separaten Laden in den Speicher.
18. 18. Verfahren nach Satz 16 oder 17, ferner umfassend Erzeugen einer Vielzahl von transformierten Bildern aus dem ersten Bild unter Verwendung einer Vielzahl von Transformationsaspektparametern.
19. 19. Verfahren nach Satz 18, wobei die Vielzahl von Transformationsaspektparametern einen Qualitätsaspekt, einen Aussehensaspekt und/oder einen Raumkonfigurationsaspekt umfasst.
20. 20. Verfahren nach einem der Sätze 16-19, wobei der Transformationsaspektparameter einen Raumkonfigurationsaspektparameter umfasst, wobei das Verfahren ferner Modifizieren des ersten Bildes gemäß dem Raumkonfigurationsaspektparameter und Modifizieren der Segmentierung des ersten Bildes gemäß dem Raumkonfigurationsaspektparameter umfasst.
21. 21. Verfahren nach Satz 20, wobei Modifizieren des ersten Bildes gemäß dem Raumkonfigurationsaspektparameter zufälliges Zuschneiden von Teilvolumina des ersten Bildes zum Laden in einen Speicher umfasst, um den Wert des Transformationsaspektparameters auf das erste Bild anzuwenden.
22. 22. Verfahren nach einem der Sätze 16-21, ferner umfassend Trainieren des ersten neuronalen Netzes über eine Vielzahl von Trainingsepochen unter Verwendung eines unterschiedlichen Transformationsaspektparameters für jede der Vielzahl von Trainingsepochen.
23. 23. Verfahren unter Verwendung einer oder mehrerer Grafikverarbeitungseinheiten zum Verarbeiten von Bildern, umfassend Identifizieren eines oder mehrerer Objekte innerhalb eines oder mehrerer Bilder eines zweiten Satzes von Bildern unter Verwendung eines trainierten neuronalen Netzes, wobei es sich bei dem trainierten neuronalen Netz um ein neuronales Netz handelt, das an einem ersten Satz von Bildern trainiert ist, wobei es sich bei dem ersten Satz von Bildern um Bilder aus einer ersten Domäne handelt, wobei es sich bei dem zweiten Satz von Bildern um Bilder aus einer zweiten Domäne handelt und wobei der erste Satz von Bildern vor dem Trainieren des trainierten neuronalen Netzes auf Grundlage von erwarteten Unterschieden zwischen der ersten Domäne und der zweiten Domäne transformiert wird.
24. 24. Verfahren nach Satz 23, ferner umfassend Bestimmen eines Domänenunterschieds, der die erwarteten Unterschiede zwischen der ersten Domäne und der zweiten Domäne darstellt, Bereitstellen des Domänenunterschieds als Eingabe in das trainierte neuronale Netz und Verwenden des Domänenunterschieds in einem Bildverarbeitungsprozess.
25. 25. Verfahren nach Satz 23 oder 24, wobei der zweite Satz von Bildern medizinische Bilder umfasst.
26. 26. Verfahren nach Satz 25, wobei es sich bei dem ersten Satz von Bildern um Bilder handelt, die unter Verwendung einer ersten medizinischen Vorrichtung erlangt werden, und es sich bei dem zweiten Satz von Bildern um Bilder handelt, die unter Verwendung einer zweiten medizinischen Vorrichtung erlangt werden, die sich von der ersten medizinischen Vorrichtung unterscheidet.
27. 27. Verfahren nach einem der Sätze 23-26, wobei der erste Satz von Bildern volumetrische Bilder umfasst.
28. 28. Verfahren nach einem der Sätze 23-26, wobei die erwarteten Unterschiede zwischen der ersten Domäne und der zweiten Domäne einem oder mehreren von einem Qualitätsaspekt, einem Aussehensaspekt oder einem Raumkonfigurationsaspekt entsprechen.

Embodiments of the disclosure can be described in terms of the following sentences:

1. A processor comprising one or more circuitry to help train one or more first neural networks on a first set of images using one or more graphics processing units to generate one or more objects within one or more images of a second set of Identify images, the first set of images being images from a first domain, the second set of images being images from a second domain, and the first set of images based on prior to training expected differences between the first domain and the second domain is transformed.
2. 2. The processor of sentence 1, further comprising first memory for storing the first set of images, a transformer for transforming a first image of the first set of images according to an image aspect to form a first transformed image, and second memory for transforming the first Image for use in training the one or more first neural networks.
3. 3. The processor of clause 2, wherein the image aspect comprises one or more of a quality aspect, an appearance aspect, or a spatial configuration aspect.
4. 4. The processor of clause 3, wherein the transformer includes logic to select an image aspect value for the image aspect from a range of aspect values to be used to transform the first image according to the image aspect and the image aspect value.
5. 5. The processor of any one of sets 2-4, further comprising segmentation memory for storing segmentation data of the first image.
6. 6. The processor of sentence 5, wherein the image aspect comprises a space configuration aspect and wherein the transformer modifies the first image according to space configuration aspect parameters and modifies the segmentation data of the first image according to the space configuration aspect parameters.
7. 7. The processor of any of sentences 2-6, wherein the image aspect comprises a spatial configuration aspect and wherein the first image is a volume image, the processor further comprising an image cropper to crop the first image into sub-volume images, wherein sub-volume images are processed separately.
8. 8. The processor of clause 7, wherein the image cropper is a cropper that interpolates within a cuboid with minimal surface area containing a 3D coordinate grid.
9. 9. A processor comprising a trained neural network that uses one or more graphics processing units to identify one or more objects within one or more images of a second set of images, the trained neural network being a neural network which is trained on a first set of images, the first set of images being images from a first domain, the second set of images being images from a second domain, and the first set of images being prior transforming the training of the trained neural network based on expected differences between the first domain and the second domain.
10. 10. The processor of sentence 9, further comprising storage for domain difference data representing the expected differences between the first domain and the second domain, and an input of the trained neural network for receiving the domain difference data for use in an image processing process.
11. 11. The processor of clause 9 or 10, wherein the expected differences between the first domain and the second domain correspond to one or more of a quality aspect, an appearance aspect, or a space configuration aspect.
12. 12. The processor of any of sets 9-11, wherein the second set of images comprises medical images.
13. 13. The processor of clause 12, wherein the first set of images are images obtained using a first medical device and the second set of images are images obtained using a second medical device which is different from the first medical device.
14. 14. The processor of any one of sets 9-13, wherein the first set of images comprises volumetric images.
15. 15. A method of processing images using one or more graphics processing units, comprising training a first neural network with a first set of images and outputs to help a trained neural network generate outputs from an input Image of a second set of images, the first set of images being images from a first domain, the second set of images being images from a second domain, and the first set of images being prior transforming training based on expected differences between the first domain and the second domain.
16. 16. The method of clause 15, wherein training the first neural network comprises: obtaining the first set of images including at least a first image, obtaining a segmentation of the first image, the segmentation representing boundaries of objects included in the first image are mapped, determining a transformation aspect parameter, wherein the transformation aspect parameter corresponds to at least one of the expected differences between the first domain and the second domain, determining a value of the transformation aspect parameter, transforming the first image based on the value of the transformation aspect parameter to form a transformed first image, Training the first neural network with the transformed first image.
17. 17. The method of clause 16, further comprising determining whether the first image can be transformed as a whole using a memory, and cropping the first image into a plurality of sub-volumes for loading separately into the memory.
18. 18. The method of sentence 16 or 17, further comprising generating a plurality of transformed images from the first image using a plurality of transformation aspect parameters.
19. 19. The method of clause 18, wherein the plurality of transformation aspect parameters includes a quality aspect, an appearance aspect, and / or a space configuration aspect.
20. 20. The method according to any of sentences 16-19, wherein the transformation aspect parameter comprises a space configuration aspect parameter, the method further comprising modifying the first image according to the space configuration aspect parameter and modifying the segmentation of the first image according to the space configuration aspect parameter.
21. 21. The method of clause 20, wherein modifying the first image according to the spatial configuration aspect parameter comprises randomly cropping partial volumes of the first image for loading into memory to apply the value of the transformation aspect parameter to the first image.
22. 22. The method according to any one of sentences 16-21, further comprising training the first neural network over a plurality of training epochs using a different transformation aspect parameter for each of the plurality of training epochs.
23. 23. A method using one or more graphics processing units for processing images, comprising identifying one or more objects within one or more images of a second set of images using a trained neural network, the trained neural network being a neural network trained on a first set of images, the first set of images being images from a first domain, the second set of images being images from a second domain, and the first set of Images is transformed prior to training the trained neural network based on expected differences between the first domain and the second domain.
24. 24. The method of sentence 23, further comprising determining a domain difference representing the expected differences between the first domain and the second domain, providing the domain difference as input to the trained neural network, and using the domain difference in an image processing process.
25. 25. The method of sentence 23 or 24, wherein the second set of images comprises medical images.
26. 26. The method of sentence 25, wherein the first set of images are images obtained using a first medical device and the second set of images are images obtained using a second medical device which is different from the first medical device.
27. 27. The method of any one of sets 23-26, wherein the first set of images comprises volumetric images.
28. 28. The method of any of sentences 23-26, wherein the expected differences between the first domain and the second domain correspond to one or more of a quality aspect, an appearance aspect, or a space configuration aspect.

In at least one embodiment, a single semiconductor platform can refer to a single unitary semiconductor-based integrated circuit or chip. In at least one embodiment, multi-chip modules with increased connectivity can be used that the Simulate chip-internal operation and offer significant improvements compared to the use of a conventional implementation with a central processing unit ("CPU") and a bus. In at least one embodiment, different modules can also be accommodated separately or in different combinations of semiconductor platforms, as desired by the user.

In at least one embodiment, referring again to FIG 15th , are computer programs in the form of machine readable executable code or computer control logic algorithms in main memory 1504 and / or secondary storage. If executed by one or more processors, computer programs enable the system 1500 to perform various functions in accordance with at least one embodiment. In at least one embodiment, there are main memories 1504 , Data storage, and / or any other storage possible examples of computer readable media. In at least one embodiment, secondary storage may refer to any suitable storage device or system, such as a hard disk drive and / or a removable storage drive, a floppy disk drive, a magnetic tape drive, a compact disk drive , digital versatile disk (“DVD”) drive, recording device, universal serial bus (“USB”) flash memory, and so on. In at least one embodiment, the architecture and / or functionality of various previous figures in the context of the CPU 1502 , the parallel processing system 1512 , an integrated circuit that provides at least some of the capabilities of both the CPU 1502 as well as the parallel processing system 1512 is capable of using a chipset (e.g. a group of integrated circuits designed to operate and be sold as a unit to perform related functions, etc.) and / or any suitable combination of integrated circuit (s) implemented.

In at least one embodiment, the architecture and / or functionality of various previous figures are implemented in the context of a general purpose computer system, a circuit board system, an entertainment game console system, an application specific system, and more. In at least one embodiment, the computer system can 1500 in the form of a desktop computer, laptop computer, tablet computer, servers, supercomputers, smartphone (e.g. wireless portable device), personal digital assistant ("PDA"), digital camera, an Vehicle, head-mounted display, handheld electronic device, cellphone device, television, workstation, game console, embedded system, and / or any other type of logic.

In at least one embodiment, the system includes parallel processing 1512 a multitude of parallel processing units ("PPUs") without restriction 1514 and associated memories 1516 . In at least one embodiment, the are PPUs 1514 via an interconnection 1518 and a switch 1520 or multiplexers connected to a host processor or other peripheral devices. In at least one embodiment, the parallel processing system distributes 1512 Compute tasks on PPUs 1514 that can be parallelized - for example as part of the distribution of computing tasks over several thread blocks of a graphics processing unit (“GPU”). In at least one embodiment, the memory is used by some or all of the PPUs 1514 shared and accessible to them (e.g. for read and / or write access), although such shared memory has a computational impact on the use of local memory and registers contained in a PPU 1514 are resident, can bring with it. In at least one embodiment, the operation of the PPUs 1514 by using a command such as _syncthreads (), all threads are synchronized in a block (e.g. across multiple PPUs 1514 across) must reach a point in code execution before continuing.

Other variations are within the spirit of the present disclosure. Thus, while various modifications and alternative constructions can be made in the disclosed techniques, certain illustrated embodiments thereof have been shown in the drawings and have been described in detail above. It should be understood, however, that it is not intended to limit the disclosure to the specific form or shapes disclosed, but rather, on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents disclosed in the The spirit and scope of the disclosure fall as defined in the appended claims.

The use of the terms “a” and “an” and “der / die / das” and similar referents in the context of describing disclosed embodiments (particularly in the context of the following claims) is to be construed to cover both the singular and the plural unless otherwise specified herein or the context clearly contradicts it, and not as a definition of a term. The terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (meaning “including, but not limited to,”) unless otherwise noted. When it is unmodified and to refer to physical connections, “connected” is to be construed as incorporated, attached, or attached to one another in whole or in part, including with an element therebetween. The mentioning of ranges of values herein is intended only as a brief process of individual reference to each separate value that falls within the range, unless otherwise stated herein, and each separate value is included in the description as if individually herein would be reproduced. In at least one embodiment, the use of the term “set” (e.g., “a set of items”) or “subset” is to be construed as a non-empty collection that includes one or more items, unless otherwise noted or the context contradicts it. Furthermore, unless otherwise stated or the context contradicts this, the term “subset” of a corresponding sentence does not necessarily denote a correct subset of the corresponding sentence, but the subset and the corresponding sentence can be the same.

Unless specifically stated otherwise or the context clearly contradicts this, connective language, such as formulations of the form “at least one of A, B and C” or “at least one of A, B and C”, is otherwise in the context in which they are generally used to represent that an object, phrase, etc. can be either A or B or C or any non-empty subset of the set of A and B and C. For example, in the illustrative example of a sentence having three elements, the connective phrases "at least one of A, B and C" and "at least one of A, B and C" refer to any of the following sentences: {A }, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, in general, such connective language is not intended to imply that any particular discourse requires that at least one of A, at least one of B, and at least one of C be present. Unless otherwise noted or the context contradicts this, the term “multiplicity” indicates a state of plurality (e.g. “a multiplicity of objects” indicates several objects). In at least one embodiment, the number of objects in a plurality is at least two, but there can also be more if this is indicated either explicitly or by the context. Unless otherwise stated or otherwise apparent from the context, the phrase “based on” means “based at least in part on” and not “solely based on”.

Operations of processes described herein may be performed in any suitable order unless otherwise stated herein or the context clearly contradicts it. In at least one embodiment, a process such as the processes described herein (or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with executable instructions and is available as code (e.g. executable instructions, one or more computer programs or one or more applications) that executes together on one or more processors, implemented by hardware or combinations thereof. In at least one embodiment, code is stored on a computer-readable storage medium, for example in the form of a computer program, which comprises a plurality of instructions that can be executed by one or more processors. In at least one embodiment, a computer readable storage medium is a non-transitory computer readable storage medium that excludes transitory signals (e.g., propagating transient electrical or electromagnetic transmission), but non-transitory data storage circuits (e.g., buffers, cache, and queues) within transceivers of includes transitory signals. In at least one embodiment, the code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media having stored thereon executable instructions (or other storage for storing executable instructions) which upon execution ( ie, as a result of execution) by one or more processors of a computer system, causing the computer system to perform operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media comprises a plurality of non-transitory computer-readable storage media and one or more of the individual non-transitory storage media of several non-transitory computer-readable storage media lacks the entire code, while several non-transitory computer-readable storage media together store the entire code. In at least one embodiment, the executable instructions are executed such that different instructions are executed by different processors - for example, a non-transitory computer readable storage medium stores instructions and a primary central processing unit ("CPU") executes some of the instructions, while a graphics processing unit ("GPU “) Executes other instructions. In at least one embodiment, different components of a computer system have separate processors and different processors execute different subsets of instructions.

Accordingly, in at least one embodiment, computer systems are configured to implement one or more services that individually or collectively perform operations of the processes described herein, and such computer systems are configured with appropriate hardware and / or software that enable the operations to be performed. Further, a computer system that implements at least one embodiment of the present disclosure is a single device, and in another embodiment is a distributed computer system that includes multiple devices that operate differently such that the distributed computer system performs the operations described herein and such that a single device does not performs all operations.

The use of any and all examples or exemplary wording (e.g., “such as”) provided herein is intended only to better clarify the embodiments of the disclosure and is not intended to limit the scope of the disclosure unless it is something other claims. No wording in the description should be construed as indicating any unclaimed element as essential to the practice of the disclosure.

All references, including publications, patent applications and patents, mentioned herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated as being incorporated herein by reference and set forth in their entirety.

In the description and claims, the terms “coupled” and “connected” and their derivatives may be used. It should be understood that these terms cannot be intended to be synonyms for one another. Rather, “connected” or “coupled” may be used in specific examples to indicate that two or more elements are in direct or indirect physical or electrical contact with one another. “Coupled” can also mean that two or more elements are not in direct contact with one another, but still work or interact with one another.

Unless expressly stated otherwise, it goes without saying that expressions such as “processing”, “calculating”, “calculating”, “determining” or the like in the entire description refer to actions and / or processes of a computer or computing system or a similar electronic computing device that manipulate and / or convert data represented as physical, such as electronic, quantities within the registers and / or memories of the computing system, and / or convert them to other data that are similar to physical quantities within the memories, registers or other such information storage, transmission or display devices of the computing system are shown.

Similarly, the term “processor” can refer to any device or portion of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data stored in registers and / or Memory can be saved. As a non-limiting example, the “processor” can be a CPU or a GPU. A “computing platform” can include one or more processors. As used herein, "software" processes can include, for example, software and / or hardware entities that do work over time, such as tasks, threads, and intelligent agents. In addition, each process can refer to multiple processes to execute instructions sequentially or in parallel, continuously or intermittently. In at least one embodiment, the terms “system” and “method” are used interchangeably herein to the extent that a system can embody one or more methods and the methods can be viewed as a system.

In the present document, reference may be made to the acquisition, acquisition, reception or input of analog or digital data in a subsystem, a computer system or a computer-implemented machine. In at least one embodiment, the process of obtaining, capturing, receiving, or entering analog and digital data can be accomplished in a variety of ways, such as by receiving data as parameters of a function call or an application programming interface call. In some implementations, the process of obtaining, capturing, receiving, or entering analog or digital data can be done by communicating data over a serial or parallel interface. In another implementation, the process of acquiring, capturing, receiving or entering analog or digital data can be done by transmitting data over a computer network from the providing entity to the capturing entity. Reference can also be made to the provision, output, transmission, transmission or display of analog or digital data. In various examples, the process of providing, outputting, transmitting, sending or displaying analog or digital data can be achieved by transmitting data as Input or output parameters of a function call, a parameter of an application programming interface or an interprocess communication mechanism take place.

While the discussion above sets out example implementations of the techniques described, other architectures can be used to implement the functionality described and are intended to be within the scope of this disclosure. In addition, while specific distributions of responsibilities are defined above for purposes of discussion, various functions and responsibilities could be differently distributed and divided depending on the circumstances.

Furthermore, although subject matter has been described in language specific to structural features and / or procedural acts, it should be understood that subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Rather, specific features and acts are disclosed as example forms of implementing the claims.

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• US 62/819432 [0001]

Non-patent literature cited

• National Highway Traffic Safety Administration ("NHTSA"), a division of the US Department of Transportation, and the Society of Automotive Engineers ("SAE") "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g. B. Standard No. J3016-201806, published June 15, 2018, Standard No. J3016-201609, published September 30, 2016, and previous and future versions of this standard) [0063]

Claims (28)

Processor comprising: one or more circuitry to help train one or more first neural networks on a first set of images using one or more graphics processing units to identify one or more objects within one or more images of a second set of images, wherein the first set of images are images from a first domain, the second set of images are images from a second domain, and the first set of images prior to training based on expected differences between the first Domain and the second domain is transformed. Processor after Claim 1 further comprising: first memory for storing the first set of images; a transformer for transforming a first image of the first set of images according to an image aspect to form a first transformed image; and second memory for the first transformed image for use in training the one or more first neural networks. Processor after Claim 2 wherein the image aspect comprises one or more of a quality aspect, an appearance aspect, or a space configuration aspect. Processor after Claim 3 wherein the transformer includes logic for selecting an image aspect value for the image aspect from a range of aspect values to be used to transform the first image according to the image aspect and the image aspect value. Processor after Claim 2 , further comprising segmentation memory for storing segmentation data of the first image. Processor after Claim 5 wherein the image aspect comprises a space configuration aspect and wherein the transformer modifies the first image according to space configuration aspect parameters and modifies the segmentation data of the first image according to the space configuration aspect parameters. Processor after Claim 2 wherein the image aspect comprises a spatial configuration aspect and wherein the first image is a volume image, the processor further comprising: an image cropper to crop the first image into sub-volume images, wherein sub-volume images are processed separately. Processor after Claim 7 , wherein the image cropper is a cropper that interpolates within a cuboid with minimal surface area that contains a 3D coordinate grid. Processor comprising: a trained neural network that uses one or more graphics processing units to identify one or more objects within one or more images of a second set of images, the trained neural network being a neural network attached to a first set of Images, the first set of images being images from a first domain, the second set of images being images from a second domain, and the first set of images prior to training the trained neural Network is transformed based on expected differences between the first domain and the second domain. Processor after Claim 9 , further comprising: storage for domain difference data representing the expected differences between the first domain and the second domain; and an input of the trained neural network for receiving the domain difference data for use in an image processing process. Processor after Claim 10 wherein the expected differences between the first domain and the second domain correspond to one or more of a quality aspect, an appearance aspect, or a space configuration aspect. Processor after Claim 9 wherein the second set of images comprises medical images. Processor after Claim 12 wherein the first set of images are images obtained using a first medical device and the second set of images are images obtained using a second medical device that differ from differs from the first medical device. Processor after Claim 9 wherein the first set of images comprises volumetric images. A method using one or more graphics processing units to process images, comprising: Training a first neural network with a first set of images and outputs to help a trained neural network inference outputs from an input image of a second set of images, the first set of images being images from a first Domain, the second set of images being images from a second domain, and the first set of images being transformed prior to training based on expected differences between the first domain and the second domain. Procedure according to Claim 15 wherein training the first neural network comprises: obtaining the first set of images including at least a first image; Obtaining a segmentation of the first image, the segmentation representing boundaries of objects imaged in the first image; Determining a transformation aspect parameter, the transformation aspect parameter corresponding to at least one of the expected differences between the first domain and the second domain; Determining a value of the transformation aspect parameter, transforming the first image based on the value of the transformation aspect parameter to form a transformed first image; Training the first neural network with the transformed first image. Procedure according to Claim 16 , further comprising: determining whether the first image can be transformed as a whole using a memory; and cropping the first image into a plurality of sub-volumes for separate loading into the memory. Procedure according to Claim 16 , further comprising generating a plurality of transformed images from the first image using a plurality of transform aspect parameters. Procedure according to Claim 18 wherein the plurality of transformation aspect parameters includes a quality aspect, an appearance aspect, and / or a space configuration aspect. Procedure according to Claim 16 wherein the transformation aspect parameter comprises a space configuration aspect parameter, the method further comprising: modifying the first image according to the space configuration aspect parameter; and modifying the segmentation of the first image in accordance with the spatial configuration aspect parameter. Procedure according to Claim 20 wherein modifying the first image according to the spatial configuration aspect parameter comprises randomly cropping partial volumes of the first image for loading into memory to apply the value of the transformation aspect parameter to the first image. Procedure according to Claim 16 , further comprising training the first neural network over a plurality of training epochs using a different transformation aspect parameter for each of the plurality of training epochs. A method using one or more graphics processing units to process images, comprising: Identifying one or more objects within one or more images of a second set of images using a trained neural network, the trained neural network being a neural network trained on a first set of images, which is the first set of images are images from a first domain, the second set of images are images from a second domain, and the first set of images prior to training the trained neural network based on expected differences between the first domain and the second domain is transformed. Procedure according to Claim 23 , further comprising: determining a domain difference representative of the expected differences between the first domain and the second domain; Providing the domain difference as an input to the trained neural network; and using the domain difference in an image processing process. Procedure according to Claim 23 wherein the second set of images comprises medical images. Procedure according to Claim 25 wherein the first set of images are images obtained using a first medical device and the second set of images are images obtained using a second medical device that differ from differs from the first medical device. Procedure according to Claim 23 wherein the first set of images comprises volumetric images. Procedure according to Claim 23 wherein the expected differences between the first domain and the second domain correspond to one or more of a quality aspect, an appearance aspect, or a space configuration aspect.

Images