DE102019001232A1 - Averaged reference with error monitoring - Google Patents

Abstract

The present disclosure describes a structure and method for generating the mean of two or more reference quantities (eg, reference voltage potentials) and monitoring the integrity of the voltage reference potentials. The present technology provides a reference with improved accuracy and more accurate monitoring than conventional techniques. For example, the present technology provides an error circuit including a monitor circuit and an averaging circuit configured to receive a plurality of reference signals and generate an averaged reference signal based on the received plurality of reference signals. In some examples, the monitoring circuit has a configuration for receiving the averaged reference signal from the averaging circuit, comparing the averaged reference signal with each of the plurality of reference signals, and generating an error signal when the averaged reference signal from at least one of the plurality of reference signals deviates by at least a threshold.

Description

Area of the revelation

The present description relates generally to electrical circuits, and more particularly to an averaged reference with fault monitoring.

background

In electronics, there is an increasing interest in reliability, which is partly driven by trends in automotive development, including self-driving vehicles and advanced driver assistance systems (ADAS). In particular, security is a driver in the development of circuit techniques for monitoring the integrity of a system and indicating potential errors. In one example, electronic circuits may be utilized to control and / or regulate power, brakes, steering, or other systems of a vehicle. These electronic circuits may be based on reference signals as a source of truth, for example, to determine whether these circuits or systems controlled and / or controlled by these circuits are functioning properly. Proof of the accuracy or integrity of such references, for example to improve the security of the systems in which they are used, may require the use of additional circuitry and references. These additional circuits and references can introduce uncertainty into a system, which can reduce the overall security and reliability of the system.

list of figures

• 1 zeigt eine exemplarische Netzwerkumgebung, in der eine gemittelte Referenzfehlerüberwachung entsprechend einem oder mehreren Beispielen implementiert sein kann.
• 2A zeigt ein schematisches Diagramm eines Beispiels für eine herkömmliche Fehlerüberwachungsschaltung, die zwei einzelne Referenzspannungspotenziale überwacht, entsprechend einem oder mehreren Beispielen.
• 2B zeigt ein Konzeptdiagramm eines Beispiels für einen Fehlerspannungsbereich für die herkömmliche Fehlerüberwachungsschaltung von 2A entsprechend einem oder mehreren Beispielen.
• 3A zeigt ein schematisches Diagramm eines Beispiels für eine Fehlerüberwachungsschaltung mit gemittelten Referenzspannungspotenzialen entsprechend einem oder mehreren Beispielen.
• 3B zeigt ein Konzeptdiagramm eines Beispiels für einen Fehlerspannungsbereich für die Fehlerüberwachungsschaltung von 3A entsprechend einem oder mehreren Beispielen.
• 4 zeigt ein Flussdiagramm eines exemplarischen Prozesses zur Fehlerüberwachung mit gemittelter Referenz entsprechend einem oder mehreren Beispielen für die vorliegende Technologie.

Certain features of the present technology are set forth in the appended claims. For purposes of explanation, some embodiments of the present technology are illustrated in the following figures.

• 1 FIG. 10 shows an exemplary network environment in which an average reference error monitor may be implemented according to one or more examples.
• 2A FIG. 12 shows a schematic diagram of an example of a conventional fault monitoring circuit that monitors two single reference voltage potentials, according to one or more examples.
• 2 B FIG. 14 is a conceptual diagram showing an example of an error voltage range for the conventional error monitoring circuit of FIG 2A according to one or more examples.
• 3A FIG. 12 shows a schematic diagram of an example of an error monitoring circuit having averaged reference voltage potentials according to one or more examples.
• 3B FIG. 12 shows a conceptual diagram of an example of an error voltage range for the error monitoring circuit of FIG 3A according to one or more examples.
• 4 FIG. 12 is a flowchart of an exemplary mean reference fault monitoring process according to one or more examples of the present technology. FIG.

detailed description

The present disclosure provides an error monitoring circuit that generates an average or other significant bias of two or more reference quantities (eg, reference voltage potentials) and monitors the integrity of the averaged reference. The present technology provides averaged reference potential with improved accuracy and more accurate monitoring than conventional solutions. The two voltage reference potentials are, for example, averaged together and tested against each other. The result is that the tolerances are not combined in the same way as other solutions can. Instead, the tolerances may overlap with each other to provide an overall tolerance that is improved as compared to the worst case example in which the respective worst case tolerance values are arithmetically added.

The following detailed description is intended as a description of various configurations of the present technology and is not intended to depict the only configurations in which the present technology may be practiced. The attached drawing is included and forms part of the detailed description. The detailed description includes specific details to provide a thorough understanding of the present technology. The present technology is not limited to the specific details listed herein and may be implemented using one or more examples. In one or more cases, structures and components are shown in the form of block diagrams to avoid obscuring the concepts of the present technology.

1 shows an exemplary network environment 100 in which averaged reference error monitoring corresponding to one or more Examples can be implemented. Optionally, not all of the illustrated components are required, and one or more examples may include additional components not shown in the figure. Modifications to the arrangement and type of components may be made without departing from the scope of the claims set forth herein. Additional components, other components or fewer components may be provided.

The exemplary network environment 100 includes a number of electronic devices 102A-C using transmission lines 108 with an electronic device 110 are coupled. The electronic device 110 can the electronic devices 102A-C couple together in terms of communication technology. In one or more examples, one or more of the electronic devices are 102A-C communication technology directly, so for example without the help of the electronic device 110 , coupled with each other. The exemplary network environment 100 also includes an electronic device 112 that with the electronic device 110 is coupled. In this example, the electronic device 110 the electronic device 112 communication technology with the electronic devices 102A-C couple. In one or more examples, the electronic device is 112 Part of the electronic device 110 ,

In one or more examples, one or more of the transmission lines 108 Wired communication transmission lines, such as an Ethernet, a fiber optic, a coaxial design or the like. The electronic device 110 For example, a switching device, a router device, a hub device, or generally any device that communicates with the electronic devices 102A-C can be, be or may include. Any of the electronic devices 102A -C can be the error monitoring circuit 300 from 3 include or may be the process 400 from 4 to implement.

In one or more examples, at least part of the exemplary network environment is 100 within a vehicle, such as a car. The electronic devices can be included 102A-C For example, various systems within a vehicle, such as a powertrain system, a chassis system, a telematics system, an entertainment system, a camera system, a sensor system, such as a lane keeping system, a diagnostic system or in general any system that can be used in a vehicle, or they can be coupled with these. In 1 shown are the electronic devices 102A as camera devices, namely, for example, as cameras facing forward, looking back and looking to the side; the electronic device 102B is shown as a sensor, such as a local diagnostic system; the electronic devices 102C are represented as entertainment systems; and the electronic device 112 is shown as a central in-vehicle diagnostic system. In one or more examples, the electronic device may 110 and / or one or more of the electronic devices 102A-C communication technology with a public communication network, such as the Internet to be connected.

In some examples, the electronic device includes 110 a function assurance technology, such as fault monitoring of one or more voltage reference potentials. For example, if electronic devices are connected to the brakes or the steering of a car, it is important that there is redundancy in the electronic system. In integrated circuits, each circuit has in principle a possible fault point at which a reference can be used as a reference source in the circuit. It is desirable to check the integrity of each individual circuit in the system. One approach involves the use of circuits that generate a reference size (eg, a voltage reference potential). However, there is a problem in verifying that the reference potential is accurate, as it requires another reference to test the main reference, and also requires a window that is used in the test and allows for tolerances. If the integrity of the main reference is checked using another reference, the tolerances of these two voltage reference potentials are unfavorably combined. The result is that the main reference is effectively less accurate.

2A shows a schematic diagram of an example of an error monitoring circuit 200 that monitors two single reference voltage potentials. The error monitoring circuit 200 includes a monitoring circuit 210 , The monitoring circuit 210 includes a comparator 212 , a switch 214 and an error checking circuit 216 , In some examples, the error checking circuit includes 216 a resistor in series with one of the inputs of the comparator 212 and one of the outputs of the switch 214 connected is. In some examples, the electronic device is 110 the error monitoring circuit 200 or includes part of it.

The comparator 212 can be a secondary voltage reference 222 with a primary voltage reference 220 to compare. In some examples, the comparator 212 be a window comparator, the comparator 212 comparing one of the reference voltages with an added offset relative to a first error threshold greater than a nominal reference value and a second error threshold less than the nominal reference value. In operation, an error signal from the comparator 212 to be generated. Such an error signal may have a high signal value (eg, a voltage at least as high as the indicated high threshold voltage) to indicate that an error has occurred or a low signal value (eg, a voltage at least as low as) a specified threshold of low voltage) indicating that no error has occurred.

In some examples, the inputs of the comparator 212 be switched or interconnected, so the comparator 212 check the integrity of each of the two voltage references relative to each other. The error checking circuit 216 may insert an additional value (eg, an offset signal or a value) to a voltage or signal received from one of the two voltage references. This additional value may be a voltage, a current, a phase or a frequency, which depends on the unit example of the two voltage references. Here, the two voltage references can be tested against each other to ensure that the voltages generated by the two voltage references are within a specified threshold range or value with respect to each other. The specified threshold range or value can be a current or a voltage, which depends on the voltage reference examples. The specified threshold may be from the error checking circuit 216 be defined or set. The error checking circuit 216 may generate an error check signal responsive to an incoming signal from a second output of the switch 214 is applied to a combined voltage signal 218 to create. For example, the error check signal (VCHECK, for example) may be set to 20 mV. This occurs when the primary voltage reference 220 within 20 mV (for example, a threshold range) of the secondary voltage reference 222 is, no error condition on. The error signal may go high, for example, to indicate an error when the primary voltage reference moves up or down out of the 20 mV range.

In some examples, the fault monitoring circuit may 200 at least two comparators (not shown) include. A first comparator may be used to determine if an incoming signal is rising above a specified threshold range. A second comparator may be used to determine if the incoming signal falls below a specified threshold range. As in 2A shown is a single comparator 212 from the switch 214 operate. The desk 214 can switch between the two voltage references, for example, the offset signal alternately at the primary voltage reference 220 or the secondary voltage reference 222 to apply. In some examples, the offset signal (eg, the amount of offset) may be passed through the error check circuit 216 be adapted to cause the monitoring circuit 210 detects whether the incoming signals are above or below the specified threshold range.

Sets the error checking circuit 216 For example, in some examples, an offset of 20 mV (for example, 2% of 2V) to the voltage reference under test, a resistor connected in series to an input of the comparator may be a 1 kΩ resistor. The 1 kΩ resistor can cause 20 μA to flow through the series circuit, producing, for example, a drop of 20 mV across the resistor. The voltage level of the error check signal (for example V _CHECK ) may be a fuse limit corresponding to the tolerance of the two voltage reference potentials relative to each other. Such a tolerance can indicate the maximum degree of deviation that a system can safely handle between the two voltage references.

In some examples, the integrity of a voltage reference may be tested by providing a primary voltage reference 220 with a secondary voltage reference 222 is compared. Do the voltage references deviate by more than a threshold voltage (for example VCHECK ) from each other, so an error can be detected. Such errors may be used to bring the system to a safe state (eg, the system may be shut down, an auxiliary reference may be activated, and so forth). However, the error or tolerance (eg, the statistical error) of each voltage reference may be independent. Using a voltage reference to test the integrity of another voltage reference counts such errors several times. This may lead to the detection or reporting of wrong errors.

To avoid the detection of false errors, a monitoring circuit 210 a comparator window (for example VCHECK ), which is sufficiently large to be a normal or nominal operating voltage range Include circuit. In some examples, the comparator window may be wide enough to contain errors in monitoring circuit components 220 such as a comparator error and the combined tolerance of the primary voltage reference 220 and the secondary voltage reference 222 , However, these errors can be so small that they are negligible. The monitoring circuit 210 In addition, a test limit tolerance (for example V _LIMIT ) to define limits of the primary voltage reference value (eg VREF 226 ), which may occur prior to detection of an error, or to consider.

2 B shows a conceptual diagram of an example of an error size range 250 the error monitoring circuit 220 , as in 2A is shown. In some examples, the vertical height of the framed elements represents the size when monitoring a signal parameter. Such signal parameters may include a voltage, a current, a phase, a frequency, or any other measurable signal property. The caption within the framed elements represents the size or size range parameter.

The in 2 B shown error size range 250 may indicate the range in which a monitored signal (eg, a monitored signal parameter) may vary during normal or nominal operation of a circuit utilizing the monitored signal. As in 2 B is shown is ΔVREF_A the variation of the primary voltage reference while ΔVREF_B is the variation of the second voltage reference. In some scenarios can ΔVREF_A and ΔVREF_B drift apart in opposite directions (for example ΔVREF_A from its nominal value increase by 0.5% while ΔVREF_B may fall by 0.5% from its nominal value). Neglecting errors in other components or signals of the monitoring circuit 210 can, if ΔVREF_A and ΔVREF_B are each 2% of the nominal values of their respective voltage reference, the testing of the variation of the primary voltage reference ( VREF_A ) can be set to ± 2% and the examination of the variation of the secondary voltage reference ( VREF_B ) to ± 2%. In this scenario, the voltage variation limit (eg, the nominal upper test limit) must be sufficiently far from the nominal value of a monitored reference signal (eg VREF-NOM ) must be removed in order to detect incorrect errors by the monitoring circuit 210 to prevent. This may require that the check limit setpoint (e.g. VCHECK 252 or 254 ) greater than the worst-case maximum difference between VREF_A and VREF_B is. As in 256 and 258 is shown, this condition is fulfilled when VCHECK greater than the maximum variation of the difference between ΔVREF_A and ΔVREF_B is.

3A shows a schematic diagram of an example of an error monitoring circuit 300 that monitors the mean of two or more reference voltage potentials. Optionally, not all illustrated components are used, and one or more examples may include additional components not shown in the figure. Modifications to the arrangement and type of the components may be made without departing from the spirit or scope of the claims. Additional components, other components or fewer components may be provided.

The error monitoring circuit 300 includes a monitoring circuit 310 and an averaging circuit 320 , In some examples, the electronic device is 110 the error monitoring circuit 300 or includes part of it.

The monitoring circuit 310 includes a comparator 312 , a switch 314 and an error checking circuit 316 , In some examples, the error checking circuit includes 316 an operational amplifier and a resistor, by a ratio of the averaged reference voltage 326 to create. In other examples, the error checking circuit includes 316 a resistor in series with one of the inputs of the comparator 312 and one of the outputs of the switch 314 connected is.

The averaging circuit 320 includes a voltage divider formed of resistors (eg, a resistor network), each signal path from the reference to the comparator 312 includes a resistor connected in series. In some examples, an intermediate node is between the serially connected resistive elements with an input of the monitoring circuit 310 coupled to provide the averaged reference signal. In particular, the intermediate node is directly connected to a second input of the switch 314 coupled. The resistors may be tuned to the same value in some examples, or may not be tuned in other examples. In operation, the averaging circuit receives 320 a plurality of voltage reference signals (for example 322 . 324 ) and generates an average reference voltage 326 based on the received voltage reference signals. In some examples, the averaging circuit averages 320 the voltage reference signals simultaneously, and the comparator 312 compares the averaged reference voltage 326 with one of the voltage reference signals. In some examples, the Averaging and monitoring technique of the fault monitoring circuit 300 are also used in other sizes used in electronic circuits, such as current, phase or frequency. In some examples, the averaging circuit may 320 be any circuit that performs operations using the reference signals to generate a combined signal that has a variation that is less than an overall variation of the reference signals.

In operation are four different configurations of the fault monitoring circuit 300 available. In a first configuration, the switches couple 314 and 328 (hereinafter referred to as "switch 328 "Denotes) the voltage reference 322 (for example VREF_C ) with the non-inverting input of the comparator 312 and couple the averaged reference voltage 326 (For example, a combined reference signal) with the error compensation signal 318 with the inverting input of the comparator 312 , The comparator 312 may output a logic high signal indicating the presence of an error condition if the voltage reference 322 the voltage sum from the averaged reference voltage 326 and the error compensation signal 318 exceeds.

In a second configuration, the switch couples 314 the average reference voltage 326 with the noninverting input of the comparator 312 and couples the voltage reference 322 with the error compensation signal 318 with the inverting input of the comparator 312 , The comparator 312 may output a logic high signal indicating the presence of an error condition when the averaged reference voltage 326 the voltage sum from the voltage reference 322 and the error compensation signal 318 exceeds.

In a third configuration, the switch couples 314 the voltage reference 324 ( VREF_D ) with the non-inverting input of the comparator 312 and couples the averaged reference voltage 326 with the error compensation signal 318 with the inverting input of the comparator 312 , The comparator 312 outputs a logic high signal indicating the presence of an error condition when the voltage reference 324 the voltage sum from the averaged reference voltage 326 and the error compensation signal 318 exceeds.

In a fourth configuration, the switch couples 314 the average reference voltage 326 with the noninverting input of the comparator 312 and couples the voltage reference 324 with the error compensation signal 318 with the inverting input of the comparator 312 , The comparator 312 outputs a logic high signal indicating the presence of an error condition when the averaged reference voltage 326 the voltage sum from the voltage reference 324 and the error compensation signal 318 exceeds.

In some examples, the switch includes 314 a control and / or regulating circuit or other digital circuit for operating a state machine that monitors the switching operation between the voltage reference 322 and the voltage reference 324 controls and / or regulates. The state machine may also include additional states depending on the number of averaged and tested voltage reference potentials. In operation, the switch selects 314 the voltage reference 322 and connects to the comparator 312 ready to the averaged reference voltage 326 with the voltage reference 322 during a first state of the state machine. In some examples, the state machine then enters a second state in which the switch 314 the voltage reference signal 324 can select and connect to the connector 312 to the averaged reference voltage 326 with the voltage reference 324 to compare. In some examples, the comparator gives 312 an error signal after at least one of the voltage reference signals having the averaged reference voltage 326 has been compared. In other examples, the comparator gives 312 the error signal off after all the voltage reference signals with the averaged reference voltage 326 have been compared. In some examples, the averaging circuit distributes 320 the averaged voltage signal is formed into individual signal paths based on the number of voltage reference potentials such that individual connections between each of the reference voltage potentials and the corresponding distributed averaged voltage signal are formed to simultaneously average and compare the reference voltage potentials.

In some examples, the monitoring circuit logs 310 the comparisons by means of a memory module (not shown) and outputs the error signal when, in some examples, at least one of the reference voltage signals deviates beyond the error threshold, or in other examples all reference voltage signals deviate beyond the error voltage value.

By averaging the two or more voltage references (e.g. 322 , 324) becomes the resulting accuracy over that of the error control circuit 200 improved. The effect of each reference is compared to that of 2 B explained voltage variation reduced by about half. As in 3A is shown, the averaged reference voltage (for example VREF 326 ) against every reference. This will be a problem in the Averaging circuit 320 or as a result of a downstream circuit adversely affecting the averaged reference signal.

3B shows a conceptual diagram of an example of an error size range (error budgdet) 350 for the error monitoring circuit of 3A , Optionally, not all illustrated components are utilized, and one or more examples may include additional components not shown in the figure. Modifications to the arrangement and type of the components may be made without departing from the spirit or scope of the claims. Additional components, other components or fewer components may be provided.

As in 3B is shown, the error threshold for the nominal upper limit is set to (ΔVREF_C + ΔVREF_D) / 2, where ΔVREF_C the variation of the primary voltage reference 322 is and ΔVREF_D the variation of the secondary voltage reference 324 is. Similarly, the error threshold for the nominal lower limit is set to (ΔVREF_C-AVREF_D) / 2. Each of the upper and lower test limits (or error check windows), if defined according to these rules, is defined large enough to avoid any false errors. According to these requirements, the error threshold (for example V _CHECK , as in 352 and 354 is shown) such that no false errors occur while giving a value approaching one-half of the corresponding error threshold 2 B , is set. In some examples, the error threshold may be a small fraction of the averaged reference voltage 326 generated, so that an error in any voltage reference potential has very little effect on the error threshold (for example VCHECK ) Has.

In some examples, the error threshold (ie VCHECK ) as the ratio of the averaged reference voltage 326 be adjusted without affecting the accuracy of the monitoring circuit 310 would be affected. In these examples, an error in one of the voltage references has little effect on the error threshold. If the error threshold (for example the degree to which a reference may deviate from the averaged reference) is nominally set to ± 0.5% and a reference drifts by 1%, the error threshold is only 0.5% of 0.5% incorrect (eg incorrectly calculated or estimated). Here, the error threshold ratio can be adjusted such that this (relatively small) effect is compensated.

In some examples, averaging voltages may be extended to three or more reference potentials. With three or more reference sizes included, a voting scheme may be implemented to identify which reference is faulty and to respond accordingly (for example, to disable the erroneous reference and notify the user). For example, if only one of the voltage reference potentials detects an error, then the erroneous reference can be disconnected to keep the overall system running. If necessary, the error reference is only separated if the other two voltage reference potentials do not trigger an error, if three voltage reference potentials are implemented.

In some examples, other techniques may be used for monitoring, such as sampling with an analog-to-digital converter ( ADC ) and calculating an average and digital testing by averaging multiple ADC conversions with different ADC reference potentials and means and comparing the results. In some examples, a primary voltage reference is at the reference input of the ADC created, and it will be the ADC periodically used to measure a secondary voltage reference. When the secondary voltage reference is measured, the error can be calculated digitally from the expected value, and (if the error is within an acceptable range) other than that ADC Measured quantities digitally be adjusted by half of the measured reference error. If the reference error is outside an acceptable range, an error may be reported or system operation may be disabled or modified accordingly.

4 shows a flowchart of an exemplary sequential process 400 for error monitoring an averaged reference according to one or more examples of the present technology. For purposes of explanation, the blocks of the sequential process 400 described herein as occurring in series or linear. Several blocks of the process 400 however, they can also occur in parallel. In addition, the blocks of the process must 400 not be performed in the order shown, and / or it will be one or more of the blocks of the process 400 possibly not performed.

The process 400 begins with the operation 401 in which the error monitoring circuit 300 can receive or generate a set of two or more reference signals. The reference signals may be from substantially independent circuits, such as independent power supplies, power sources, or Signal generators, received or generated. At surgery 402 can the error monitoring circuit 300 average two or more of the set of reference signals, for example, using the averaging circuit 320 to generate an averaged reference signal. At surgery 403 can the error monitoring circuit 300 For example, by the operation of a control and / or regulating circuit select a reference signal from one of the set of reference signals. At surgery 404 can the error monitoring circuit 300 combine the selected reference signal or the averaged reference signal with an error check signal to produce a combined signal. In one example, the error monitoring circuit 300 VREF_C ( 3A) combine with the error check signal in one step, VREF_D ( 3A) combine with the error check signal at a further step or combine the averaged reference voltage with the error check signal at another step. At surgery 405 can the error monitoring circuit 300 compare the selected reference signal or the averaged reference signal with the combined signal. At surgery 406 can the error monitoring circuit 300 Based on the comparison, determine if an error condition exists. In some examples, the error condition may indicate that the selected reference signal or the averaged reference signal exceeds the combined signal by at least one error threshold. At surgery 407 can the error monitoring circuit 300 provide the averaged reference signal (or selected reference) as a system reference voltage for a load when no fault condition exists. At surgery 408 can the error monitoring circuit 300 generate an error signal if an error condition exists.

The following examples define various examples of the present disclosure.

Example 1 is a circuit for monitoring a reference signal, the circuit comprising: a monitoring circuit; and an averaging circuit configured to: receive two or more reference signals, and generate a combined reference signal, the combined reference signal including a variance less than a combined variance of the two or more reference signals; wherein the monitoring circuit has a configuration for: comparing the combined reference signal and at least one reference signal of the two or more reference signals, and generating an error signal in response to an indication that the comparison violates a specified and / or specific criterion.

In Example 2, the subject invention of Example 1 optionally has a configuration including: an error circuit configured to adjust the combined reference signal or the at least one reference signal by a specified signal margin before determining.

In Example 3, the subject invention of Example 1 optionally has such a configuration that it includes: a control and / or regulating circuit for switching a selection of the at least one reference signal between the first reference signal of the two or more reference signals and a second reference signal of the two or more reference signals.

In Example 4, the subject invention of Example 1 optionally has such a configuration that it includes: a resistor network configured to generate the combined reference signal.

In Example 5, the subject invention of Example 1 optionally has such a configuration that the combined reference signal comprises a mean of the two or more reference signals.

In Example 6, the subject invention of Example 1 optionally has such a configuration that each of the two or more reference signals includes a voltage reference.

In Example 7, the subject invention of Example 1 optionally has such a configuration that the specified and / or specific criterion includes a threshold for a difference between the combined reference signal and the at least one reference signal, the threshold using a ratio of the combined reference signal to the at least one reference signal of the two or more reference signals is derived.

Example 8 is a system for detecting an error in a reference signal, the system comprising: an averaging circuit configured to receive two or more reference signals and to generate a combined signal using the two or more reference signals, the combined signal having a variance which is less than a total variance of the two or more reference signals; a switching circuit for selecting a reference signal among the two or more reference signals; an error check circuit configured to generate an error check signal; and a comparison circuit configured to: compare the combined signal with the selected reference signal using the error check signal; and Generating an error signal when the combined signal deviates from the selected reference signal by at least one threshold.

In Example 9, the subject invention of Example 8 optionally has such a configuration that the combined signal comprises a mean of the two or more reference signals.

In Example 10, the subject invention of Example 8 optionally has such a configuration that the error check circuit has a configuration for generating the error check signal based on a specified system tolerance to errors in the two or more reference signals.

In Example 11, the subject invention of Example 8 optionally has such a configuration that the averaging circuit comprises a resistor network configured to generate the combined signal.

In Example 12, the subject invention of Example 8 optionally has such a configuration that each of the two or more reference signals includes a voltage reference.

In Example 13, the subject invention of Example 8 optionally has such a configuration that the threshold comprises a fractional value of the combined signal.

In Example 14, the subject invention of Example 8 optionally has such a configuration that the threshold includes a ratio of the combined reference signal to at least one reference signal of the two or more reference signals.

Example 15 is a method for monitoring a reference signal, the method comprising: receiving two or more reference signals; Generating an averaged reference signal using the two or more reference signals; Selecting a reference signal among the two or more reference signals; Generating a combined signal by adjusting the averaged reference signal or the selected reference signal using an error check signal; Comparing the selected reference signal or the averaged reference signal with the combined signal; determining, based on the comparison, whether an error condition exists and generating an error signal if the error condition exists.

In example 16, the inventive subject matter of example 15 optionally has such a configuration that determining whether an error condition exists includes determining whether the selected reference signal or the averaged reference signal deviates from the combined signal by at least one error threshold.

In Example 17, the subject invention of Example 15 optionally has such a configuration that adjusting the averaged reference signal or the selected reference signal using the error check signal comprises: combining the averaged reference signal or the selected reference signal with the error check signal.

In Example 18, the subject invention of Example 15 optionally has a configuration such that the averaged reference signal or selected reference signal is provided to a load when no fault condition exists.

In Example 19, the subject invention of Example 15 optionally has such a configuration that generating the averaged reference signal comprises: utilizing a resistor network to average the two or more reference signals.

In Example 20, the subject matter of Example 15 optionally has such a configuration that determining the error check signal is based on a specified tolerance to errors in the selected signal.

Each of the non-limiting aspects, or non-limiting examples, described herein may stand alone or may be combined in various permutations or combinations with one or more of the other examples.

The above detailed description includes references to the accompanying drawing, which forms part of the detailed description. The drawings show examples of specific embodiments in which the subject invention can be implemented. These embodiments are also referred to herein as "examples." Such examples may include elements in addition to those shown or described. However, in the context of the present invention, examples are also included in which only those elements shown or described are provided. Moreover, in the context of the present invention, examples are also included which include any combination or permutation of those elements shown or described (or one or more aspects thereof) either with respect to a particular example (or one or more aspects thereof ) or in relation to other examples (or one or more aspects thereof) shown or described.

In the case of inconsistent uses in the present document and in any publications to which reference is made here, the use in the present document should be authoritative.

In the present document, the terms "a / a" are used as is conventional in patent documents, and include one or more than any other cases or uses of "at least one" or "one or more" one. In the present document, the term "or" is used to designate a non-exhaustive "or," such that, for example, " A or B "" A , However not B "," B , However not A " and " A and B "Unless otherwise stated. In the present document, the terms "include" and "in the" are used as equivalents to the terms "comprise" and "in", respectively, in normal English. In the following claims, the terms "include" and "comprise" are open, that is, a system, apparatus, object, composition, formulation, or process that includes elements in addition to those identified by such term in the Claims are, shall continue to be deemed to fall within the scope of that claim. Moreover, in the following claims, the terms "first / first / first,""second / second / second,""third / third / third," and the like are used only for distinction and are not intended to include any stringent requirements for the objects concerned.

Method examples described herein may be at least partially machine or computer implemented. Some examples may include a computer-readable medium or a machine-readable medium encoded with instructions that may be operable to configure an electronic device to perform methods as described in the preceding examples. One implementation of such methods may include codes such as microcode, assembly language code, abstract language code, or the like. Such code may include computer readable instructions for performing various methods. The code can form parts of computer program products. In addition, in one example, the code may be physically stored on one or more volatile, non-temporary, or non-transitory physical computer-readable media, for example, during execution, or on other occasions. Examples of these physical computer readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (eg, CDs and DVDs), magnetic cassettes, memory cards or sticks, random access memory (RAMs), read only memory (ROMs), and the like more.

The foregoing description is intended to be illustrative and not restrictive. The above examples (or one or more aspects thereof) may be used in combination with each other, for example. Other embodiments may be used, for example, by one of ordinary skill in the art upon studying the foregoing description. The summary is provided to enable the reader to quickly grasp the nature of the technical disclosure. It should be aware that it may not be used to interpret or limit the scope or meaning of the claims. In the foregoing detailed description, various features may also be grouped together to streamline the disclosure. This is not to be understood in the sense that an unclaimed disclosed feature is essential to any claim. Rather, the subject invention may be embodied in less than all features of a particular disclosed embodiment. The following claims are hereby incorporated by way of examples or embodiments into the detailed description, wherein each claim stands on its own as a separate embodiment and is included that such embodiments can be combined with each other in various combinations or permutations. The scope of the subject invention should be determined by the appended claims along with the full scope of equivalents to which the claims are entitled.

Claims (10)

A circuit for monitoring a reference signal, the circuit comprising: a monitoring circuit; and an averaging circuit designed to: to receive two or more reference signals, and generate a combined reference signal, wherein the combined reference signal comprises a variance that is less than a combined variance the two or more reference signals; the monitoring circuit being designed to: compare the combined reference signal and at least one reference signal of the two or more reference signals, and generate an error signal in response to an indication that that the comparison violates a specified criterion. Switching to Claim 1 and further comprising an error circuit configured to adjust, prior to determining, the combined reference signal or the at least one reference signal by a specified signal tolerance. Switching to Claim 1 or 2 , further comprising a control and / or regulating circuit for switching over a selection of the at least one reference signal between the first reference signal of the two or more reference signals and a second reference signal of the two or more reference signals. The circuit of any one of the preceding claims, further comprising a resistor network configured to generate the combined reference signal. A circuit according to any one of the preceding claims, wherein the combined reference signal comprises means of the two or more reference signals. The circuit of any one of the preceding claims, wherein each of the two or more reference signals comprises a voltage reference. The circuit of claim 1, wherein the specified criterion comprises a threshold for a difference between the combined reference signal and the at least one reference signal, wherein the threshold is derived using a ratio of the combined reference signal to the at least one reference signal of the two or more reference signals. A system for detecting an error in a reference signal, the system comprising: an averaging circuit configured to receive two or more reference signals and to generate a combined signal using the two or more reference signals, the combined signal having a variance, which is smaller than a total variance of the two or more reference signals; a switching circuit for selecting a reference signal among the two or more reference signals; an error check circuit configured to generate an error check signal; and a comparator circuit designed to: compare the combined signal with the selected reference signal using the error check signal; and generate an error signal when the combined signal deviates from the selected reference signal by at least one threshold. System after Claim 8 wherein the combined signal comprises a mean of the two or more reference signals. System after Claim 8 or 9 wherein the error checking circuit is configured to generate the error checking signal based on a specified system tolerance against errors in the two or more reference signals,.

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