DE102018124815B4 - FIN field effect transistor device and method - Google Patents

Abstract

A method, comprising:forming a first fin (64) overhanging a substrate (50), the first fin (64) having a PMOS region (300);forming a first gate structure (75B) over the first fin (64) in the PMOS region (300);forming a first spacer layer (86) over the first fin (64) and the first gate structure (75B);forming a second spacer layer (84) over the first spacer layer ( 86);performing a first etch process to remove the second spacer layer (84) from a top surface and sidewalls of the first fin (64) in the PMOS region (300);performing a second etch process to remove the first spacer layer (86) from the top surface and sidewalls of the first fin (64) in the PMOS region (300); andepitaxially growing a first source/drain material (80B) over the first fin (64) in the PMOS region (300), the first source/drain material (80) along the top surface (64U) and the sidewalls of the first fin (64) extend in the PMOS region (300); the first fin (64) further having an NMOS region (200), the method further comprising:forming a second gate structure (75A) over the first fin (64) in the NMOS region (200), wherein the first spacer layer (86) and the second spacer layer (84) are formed over the second gate structure (75A);forming a patterned mask layer to cover the NMOS region (200) prior to performing the first etch process; andremoving the patterned mask after epitaxially growing the first source/drain material (80B).

Description

BACKGROUND ART

The semiconductor industry has experienced rapid growth due to constant improvements in the integration density of a variety of electronic components (eg, transistors, diodes, resistors, capacitors, etc.). Most often, this improvement in integration density has consisted of repeated reductions in minimum feature size, allowing more devices to be integrated into a given area.

Fin Field Effect Transistor (FinFET) devices are commonly used in integrated circuits. FinFET devices have a three-dimensional structure that includes a semiconductor fin protruding from a substrate. A gate structure configured to control the flow of charge carriers within a conductive channel of the FinFET device wraps around the semiconductor fin. In a triple-gate FinFET device, the gate structure wraps around three sides of the semiconductor fin, forming conductive channels on three sides of the semiconductor fin. A FinFET semiconductor device is already known from the reference U.S. 2013/0 122 676 A1 . Another semiconductor device is known from US Pat U.S. 2017/0 338 341 A1 .

character list

• 1 veranschaulicht einen FinFET in einer perspektivischen Ansicht in Übereinstimmung mit einigen Ausführungsformen.
• Die 2, 3A, 3B, 4A bis 4C, 5A bis 5F, 6A bis 6C, 7A bis 7C, 8A bis 8C, 9A bis 9C, 10A bis 10C, 11A bis 11C, 12A bis 12C und 13 bis 16 sind diverse Ansichten (zum Beispiel Draufsichten, Querschnittansichten) eines FinFET-Bauteils bei diversen Fertigungsstufen in Übereinstimmung mit einigen Ausführungsformen.
• 17 veranschaulicht ein Ablaufdiagramm eines Verfahrens zum Bilden eines Halbleiterbauteils.

Aspects of the present disclosure are best understood from the following detailed description when taken in conjunction with the accompanying figures. It is emphasized that, in accordance with standard industry practice, various elements are not drawn to scale. Namely, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

• 1 1 illustrates a FinFET in a perspective view, in accordance with some embodiments.
• The 2 , 3A , 3B , 4A until 4C , 5A until 5F , 6A until 6C , 7A until 7C , 8A until 8C , 9A until 9C , 10A until 10C , 11A until 11C , 12A until 12C and 13 until 16 12 are various views (e.g., top views, cross-sectional views) of a FinFET device at various stages of manufacture, in accordance with some embodiments.
• 17 1 illustrates a flow diagram of a method of forming a semiconductor device.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples for practicing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in face-to-face contact, and may also include embodiments in which additional features are formed between the first and the second feature may be formed such that the first and second features may not be in direct contact.

Further, spatial reference terms such as "below," "below," "lower," "above," "upper," and the like may be used herein for ease of description to indicate the relationship of one feature or features to one or more other features or features , as illustrated in the figures. The spatial reference terms may be intended to encompass different orientations of the component in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial reference descriptors used herein will be interpreted accordingly.

1 illustrates an example of a FinFET 30 in a perspective view. FinFET 30 includes substrate 50 and a fin 64 protruding above substrate 50 . The substrate 50 has isolation regions 62 and the fin 64 protrudes over and between adjacent isolation regions 62 . A gate dielectric 66 overlies sidewalls and over a top surface of fin 64, and a gate 68 overlies gate dielectric 66. Source/drain regions 80 lie in the fin on opposite sides of gate 68. 1 further illustrates reference cross-sections used in later figures. Cross section BB extends along a longitudinal axis of gate 68 of FinFET 30. Cross section AA is perpendicular to cross section BB and runs along a longitudinal axis of fin 64 and in a direction, for example, of current flow between source/drain regions 80. Cross-section CC is parallel to cross-section BB and runs over a source/drain region 80 of FinFET 30. Subsequent figures refer to these reference cross-sections for clarity.

The 2 , 3A , 3B , 4A until 4C , 5A until 5F , 6A until 6C , 7A until 7C , 8A until 8C , 9A until 9C , 10A until 10C , 11A until 11C , 12A until 12C and 13 until 16 10 are various views (e.g., top views, cross-sectional views) of a FinFET device 100 at various stages of manufacture, in accordance with an embodiment. The FinFET device 100 is the FinFET 30 in 1 similar but with multiple fins.

2 12 illustrates a top view of a substrate 50 used to fabricate the FinFET device 100. FIG. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (Semiconductor-On-Insulator - SOI) substrate or the like that is doped (e.g. with a P-type or an N-type type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate includes a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates such as a multilayer or gradient substrate can also be used. In some embodiments, the semiconductor substrate 50 may be silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP, or combinations thereof.

As in 2 As illustrated, the substrate 50 has a first portion in a region 200 and a second portion in a region 300 . The first portion of the substrate 50 in region 200 can be used to form N-type devices such as N-type metal-oxide-semiconductor field-effect transistors (MOSFETs), and the second portion of the substrate 50 in region 300 can be used to form P-type devices such as P-type MOSFETs. The area 200 can thus be called an NMOS area of the substrate 50 and the area 300 can be called a PMOS area of the substrate 50. FIG. In other embodiments, P-type (or N-type) devices are formed in both region 200 and region 300 .

3A illustrates the substrate 50 in 2 with an upper portion of the substrate 50 in the region 300 being replaced by a semiconductor material 50A. 3B illustrates a cross-sectional view of the structure in FIG 3A along the cross-section DD.

Referring to the 3A and 3B For example, a portion of substrate 50 in region 300 is replaced with semiconductor material 50A, such as an epitaxial semiconductor material suitable for forming a corresponding device type (e.g., a P-type device) in region 300. FIG. The semiconductor material 50A may be or comprise epitaxially grown silicon germanium, for example. To form the semiconductor material 50A, a mask layer (not shown), which may be a photosensitive layer such as a photoresist, is deposited over the substrate 50 using chemical vapor deposition (CVD), physical vapor deposition (PVD), Spin coating or other convenient deposition process formed. The mask layer is then patterned using, for example, photolithographic and/or patterning techniques. The patterned mask layer covers area 200 but exposes area 300 . An exposed portion of the substrate 50 in the area 300 is then removed by an appropriate etching process, such as reactive ion etching (Reactive Ion Etch - RIE), Neutral Beam Etch (NBE) or a combination thereof to form a depression (not shown) in to form the area 300.

Thereafter, epitaxy is performed to grow the semiconductor material 50A in the recesses of the region 300. FIG. The epitaxially grown semiconductor material 50A may be doped in situ during growth, which may obviate the need for pre- and post-implants, although in situ and implant doping may be used together. After epitaxy, the mask layer can be removed by any convenient removal process such as etching or plasma ashing. A planarization process such as chemical mechanical polishing (CMP) may then be performed to match the top surface of the semiconductor material 50A with the top surface of the substrate 50. FIG. 3B shows an interface 63 between the semiconductor material 50A and the substrate 50, which, as in FIG 3B illustrated, may or may not be a straight line.

Optionally, another patterned mask layer (not shown) may be formed to cover region 300 while region 200 is exposed, and an exposed portion of substrate 50 in region 200 may be removed and bonded with an epitaxially grown semiconductor device material 50B, the in 3B illustrated in dashed lines can be replaced. An interface 63 ′ may be formed between the semiconductor material 50B (if formed) and the substrate 50 . Semiconductor material 50B may be or may include an epitaxial semiconductor material suitable for forming a corresponding device type (e.g., an N-type device) in region 200 . The semiconductor material 50B may be or comprise epitaxially grown silicon carbide, for example.

In other embodiments, semiconductor material 50B (e.g., an epitaxial semiconductor material) replaces a portion of substrate 50 in region 200, and a portion of substrate 50 in region 300 may optionally be replaced with semiconductor material 50A (e.g., an epitaxial semiconductor material). In still other embodiments, the epitaxial semiconductor materials described above (e.g., 50A and 50B) are not formed, so the processing described in FIGS 3A and 3B illustrated can be omitted. The following discussion uses an embodiment configuration for substrate 50 in which semiconductor material 50A is formed in region 300 and semiconductor material 50B is not formed in region 2003, it being understood that the processing illustrated in the present disclosure is also applicable to other substrate configurations such as those described. In the following discussion, substrate 51 will be used to refer to substrate 50 and semiconductor materials 50A/50B if formed.

The semiconductor materials 50A or 50B (e.g., epitaxial semiconductor materials) may have a lattice constant that is greater than, substantially equal to, or less than the lattice constant of the substrate 50. The lattice constant of the semiconductor materials 50A or 50B is determined by the material(s). , which are selected by the conductivity types (e.g. N-type or P-type) of the resulting FinFETs. Furthermore, it may be advantageous to epitaxially grow a material in an NMOS area that is different from the material in a PMOS area. In various embodiments, the semiconductor materials (e.g., 50A, 50B) may include silicon germanium, silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming a III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

Subsequently, as in the 4A until 4C As illustrated, the substrate 51 is patterned to form semiconductor fins 64 (also called fins). 4A 12 illustrates a top view of FinFET device 100 after fins 64 have been formed. The 4B and 4C illustrate cross-sectional views of the FinFET device 100 in FIG 4A along cross-sections FF and EE, respectively. As in 4A As illustrated, each fin 64 includes a portion 64A in region 2003 and a portion 64B in region 300. Section 64A and section 64B may be formed in a same processing step (e.g., a same patterning process), details of which are provided by reference below on the 4B and 4C are described.

Referring to the 4B and 4C For example, the substrate 51 is patterned using lithography and etching techniques. For example, a mask layer such as a pad oxide layer (not shown) and an overlying pad nitride layer (not shown) is formed over substrate 51 . The pad oxide layer may be a thin film comprising silicon oxide formed using a thermal oxidation process, for example. The pat oxide layer can act as an adhesion layer between the substrate 51 and the overlying pad nitride layer. In some embodiments, the pad nitride layer is formed of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or the like, or a combination thereof, and may be formed using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (plasma Enhanced Chemical Vapor Deposition - PECVD) as examples.

The mask layer can be patterned using photolithography techniques. In general, photolithography techniques employ a photoresist (not shown) that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist. The remaining photoresist protects the underlying material, such as the mask layer in this example, from subsequent processing steps such as etching. In this example, the photoresist is used to pattern the pad oxide layer and the pad nitride layer to form a patterned mask 58 . As in the 4B and 4C As illustrated, patterned mask 58 includes patterned pad oxide 52 and patterned pad nitride 56 .

The patterned mask 58 is then used to pattern the substrate 51 to form trenches 61, thereby forming semiconductor fins 64 between adjacent trenches, as in FIGS 4B and 4C illustrated, defined. Each semiconductor fin 64 has a portion 64A (see FIG _. 4A) in region 2003 (e.g., in an NMOS region) and a portion 64B (see FIG 4A ) in the region 300 (e.g. in a PMOS region). Section 64A can be used to form an N-type FinFET, for example, and section 64B can be used to form a P-type FinFET, for example. In the following discussion, portion 64A of fin 64 may be called fin 64A, and portion 64B of fin 64 may be called a fin 64B.

In some embodiments, the semiconductor fins 64 will be formed by etching trenches in the substrate 51 using, for example, Reactive Ion Etch (RIE), Neutral Beam Etch (NBE), the like, or a combination thereof. Etching can be anisotropic. In some embodiments, the trenches may be strips (in plan view) that are parallel to and closely spaced from each other. In some embodiments, the trenches may be continuous and surround the semiconductor fins 64 .

The fins 64 can be patterned by any convenient method. The fins 64 may be patterned, for example, using one or more photolithographic processes including double patterning or multiple patterning processes. In general, double-patterning or multiple-patterning processes combine photolithography and self-aligned processes that allow creating structures that, for example, have pitches smaller than those that can otherwise be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligning process. The sacrificial layer is then removed and the remaining spacers or mandrels can then be used to pattern the fins.

As mentioned, an upper portion of substrate 50 in region 300 is replaced with semiconductor material 50A. Thus, depending on where the bottom of the trenches 613 lies at the interface 63 between the semiconductor material 50A and the substrate 50 (e.g., at interface 63, above interface 63, or below interface 63), fins 64B may be one or more have materials. In the example of 4C the bottom of trenches 613 extends below interface 63, and fin 64B consequently has a first portion above interface 63 formed of semiconductor material 50A (e.g., silicon-germanium) and a second portion below interface 63, formed of the material (e.g. silicon) of the substrate 50 . The fin 64A is made entirely of the material (e.g., silicon) of the substrate 50 in the illustrated example of FIG 4B educated. In other embodiments, the bottom of trenches 613 extends above or at interface 63 and fin 64B is thus formed entirely of semiconductor material 50A (e.g., silicon germanium) and fin 64A is formed entirely of the material (e.g., silicon ) of the substrate 50 is formed.

Variations in the structure and method of formation of the fins 64 are possible. Although the 4A until 4C illustrate forming two fins 64, more or fewer than two fins can be formed. As another example, the fins 64 may be formed by etching the substrate 50 to form a first plurality of fins (at least portions of which are removed and replaced in subsequent processing), forming an insulating material around the first plurality of fins, Removing portions (e.g., portions in region 300) of the first plurality of fins to form recesses in the insulating material, and epitaxially growing semiconductor material(s) in the recesses to form the fins 64 are formed.

As in the 5A until 5F 1, isolation regions 62 are then formed over substrate 50 and on opposite sides of fins 64, and dummy gate structures 75 (e.g., 75A and 75B) are formed over fins 64. FIG. 5A FIG. 12 is a top view of the FinFET device 100, and FIG 5B and 5C are cross-sectional views of the FinFET device 100 in FIG 5A each along cross-sections FF and EE. The 5D and 5E are cross-sectional views of the FinFET device 100 in FIG 5A respectively along cross-sections HH and GG, and 5F 10 is a cross-sectional view of the FinFET device 100 in FIG 5A along cross-section II.

Referring to the 5B and 5C Isolation regions 62 are formed by filling trenches 613 with an isolation material and deepening the isolation material. The insulating material 54 may be an oxide, such as silicon oxide, a nitride, or the like, or a combination thereof, and may be formed by High Density Plasma Chemical Vapor Deposition (HDP-CVD), Flowable CVD (FCVD) (eg example one on CVD-based material deposition in a remote plasma system and post-cure to have it converted to another material such as an oxide), the like, or a combination of these can be formed. Other insulation materials and/or formation processes can be used. A planarization process, such as a CMP, may remove excess insulating material and form a top surface of the insulating material and top surfaces of the semiconductor fins 64 that are coplanar (not shown). The structured mask 58 (see 4B and 4C ) can be removed by the CMP process.

In some embodiments, the isolation regions 62 include a liner, for example a liner oxide (not shown) at the interface between the isolation regions 62 and the substrate 50/fins 64. FIG. In some embodiments, the liner oxide is formed to reduce crystalline imperfections at the interface between the substrate 50 and the isolation regions 62 . Similarly, the liner oxide can also be used to reduce crystalline imperfections at the interface between the semiconductor fins 64 and the isolation regions. The liner oxide (e.g., silicon oxide) may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 50 and/or the fins 64, although any convenient method for forming the liner oxide may also be used.

Thereafter, the insulating material is deepened to form isolation regions 62 such as Shallow Trench Isolation (STI) regions. The isolation material is recessed such that the top portions of the semiconductor fins 64A/64B protrude between adjacent isolation regions 62 . The top surfaces of the isolation regions 62 may have a flat surface (as illustrated), a convex surface, a concave surface (such as a dishing), or a combination thereof. The top surfaces of the isolation regions 62 may be formed flat, convex, and/or concave by appropriate etching. The isolation regions 62 may be deepened using any acceptable etch process, such as one that is selective with respect to the material of the isolation regions 62 . For example, chemical oxide removal using a CERTAS® etch or an Applied Materials SICONI tool or dilute hydrofluoric acid (dHF) can be used.

The 5A until 5C 12 illustrate forming a dummy gate structure 75 over the semiconductor fins 64. The dummy gate structure 75 includes a gate dielectric 66 and a gate 68 in some embodiments. To form the dummy gate structure 75, a dielectric layer is formed on the semiconductor fins 64 (e.g., 64A and 64B) and the isolation regions 62. FIG. The dielectric layer may be, for example, silicon oxide, silicon nitride, multiple layers thereof, or the like, and may be deposited (as illustrated) or thermally grown (not shown) according to acceptable techniques. The dielectric layer formation methods may include Molecular Beam Deposition (MBD), Atomic Layer Deposition (ALD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and the like.

A gate layer is formed over the dielectric layer and a mask layer is formed over the gate layer. The gate layer can be deposited over the dielectric layer and then planarized by, for example, a CMP. The mask layer can be deposited over the gate layer 60 . The gate layer can be formed of polysilicon, for example, although other materials can also be used. The mask layer can be formed of silicon nitride or the like, for example.

After the layers (e.g., the dielectric layer, the gate layer, and the mask layer) have been formed, the mask layer can be patterned to form a mask 70 using acceptable photolithography and etching techniques. The mask 70 pattern is then transferred to the gate layer and dielectric layer by an acceptable etching technique to form gate 68 and gate dielectric 66, respectively, and gate 68 and gate dielectric 66 cover in some embodiments respective channel regions of the semiconductor fins 64. In other embodiments, the patterning of the mask 70 is transferred to the gate layer to form the gate 68 but is not transferred to the dielectric layer. In other words, the dielectric layer is not patterned by the mask 70 in some embodiments, in which case the dielectric layer may be called the gate dielectric 66 or the dielectric layer 66 . The following discussion uses the example where the dielectric layer is not patterned by the mask 70, however, the concept of the present disclosure applies to embodiments where the dielectric layer is patterned by the mask 70 as well. The gate 68 may have a longitudinal direction substantially perpendicular to the longitudinal direction of the respective semiconductor fins 64 . As in 5A As illustrated, gate structure 75A is formed over fins 64A in region 200, and gate structure 75B is formed over fins 64B in region 300. FIG.

The 5D and 5E 12 illustrate cross-sectional views of FinFET device 100 of FIG 5A each along a cross-section HH and GG. Gate structures 75A and 75B may not be visible in this cross section. In the example of 5E the interface 63 extends further from an upper major surface 50U of the substrate 50 than an upper surface 62U of the isolation regions 62.

5F 12 illustrates a cross-sectional view of FinFET device 100 of FIG 5A along cross-section II. As in 5F As illustrated, gate structure 75A is formed over fins 64A in region 200 and gate structure 75B is formed over fins 64B in region 300. FIG.

The 6A until 6C , 7A until 7C , 8A until 8C , 9A until 9C , 10A until 10C , 11A up to 113C and 12A until 12C illustrate further processing of the FinFET device 100 shown in FIGS 5A until 5F is shown. In particular, the 6A , 7A , 8A , 9A , 10A , 11A and 12A Cross-sectional views of the FinFET device 100 along cross-section II (see FIG 5A ) at various stages of production. The 6B , 7B , 8B , 9B , 10B , 11B and 12B illustrate the corresponding cross-sectional views of the FinFET device 100 along the cross-section HH (see FIG 5A ), and the 6C , 7C , 8C , 9C , 10C , 11C and 12C illustrate the corresponding cross-sectional views of the FinFET device 100 along the cross-section GG (see FIG 5A ).

Subsequently, as in the 6A until 6C 1, a first spacer layer 86 and a second spacer layer 84 are sequentially deposited over the structure shown in FIGS 5A until 5F is illustrated formed. The first spacer layer 86 and the second spacer layer 84 may be formed conformal. In some embodiments, the first spacer layer 86 comprises low-x dielectric material and may therefore be called a low-x spacer layer. The first spacer layer 86 may be formed from any suitable material, such as silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or silicon carbonitride (SiCN). A thickness of the first spacer layer 86 may range from about 2 nm to about 5 nm. In some embodiments, the second spacer layer comprises a nitride-rich dielectric material. The second spacer layer 84 may be formed from any suitable material, such as silicon nitride (SiN) or silicon carbonitride (SiCN). A thickness of the second spacer layer 84 may range from about 3 nm to about 5 nm. Any convenient deposition process, such as PVD, CVD, and ALD, may be used to form first spacer layer 86 and second spacer layer 84 .

In accordance with some embodiments, a first material of the first spacer layer 86 is selected different from a second material of the second spacer layer 84 to provide etch selectivity between the first spacer layer 86 and the second spacer layer 84 in subsequent processing. For example, if the second spacer layer 84 is formed of SiN, the first spacer layer 86 may be formed of SiOC, SiOCN, or SiCN. As another example, if the second spacer layer 84 is formed of SiCN, for example, the first spacer layer 86 may be formed of SiOC or SiOCN.

Subsequently, as in the 7A until 7C 1, a mask layer, which may be a photosensitive layer such as a photoresist, is applied over the structure shown in FIGS 6A until 6C is formed using CVD, PVD, spin coating, or any other suitable deposition process. The mask layer is then patterned to form a patterned mask 88 using, for example, photolithography and/or patterning techniques. Patterned mask 88 covers area 200 but lays down area 300 1 as in FIGS 7A until 7C illustrated, free. The patterned mask 88 thus shields the region 200 from the subsequent etch processes, which are described with reference to FIG 8A until 8C and 9A until 9C are described, from.

Subsequently, as in the 8A until 8C As illustrated, an etch process is performed to remove portions of second spacer layer 84 in region 300 . In some embodiments, the process used to remove portions of the second spacer layer 84 is an anisotropic etch process, such as a dry etch process. A plasma etch process using carbon monoxide (CO), tetrafluoromethane (CF ₄ ), oxygen (O ₂ ), ozone (O ₃ ), or combinations thereof may be performed to etch the exposed second spacer layer 84 in region 300 (e.g a PMOS area). In some embodiments, the plasma etch process has a high etch selectivity (e.g., has a higher etch rate) for the second spacer layer 84 over the first spacer layer 86 . In some embodiments, the plasma (e.g., CF ₄ plasma) reacting at the Plasma etch process is used with the second spacer layer 84 to remove the second spacer layer 84 . In some embodiments, the anisotropic etch process removes the second spacer layer 84 over a top surface and sidewalls of the fins 64B (see FIG 8C ) such that the first spacer layer 86 is exposed over the top surface and sidewalls of the fins 64B. The anisotropic etch process may also remove top portions of first spacer layer 86 in region 300 . As in 8A As illustrated, the etch process removes portions of second spacer layer 84 and portions of first spacer layer 86 over the top surface of gate structure 75B (eg, over mask 70) such that mask 70 is exposed. Additionally, the first spacer layer 86 may be thinned over the top surface of the fins 64B (see FIG 8A ) or removed (not shown).

Portions of the second spacer layer remain due to the anisotropy of the plasma etch process (e.g., DC bias is used) and/or due to the by-product (e.g., polymer) formed on the sidewalls of the gate structure 75B during the plasma etch process 84 (e.g. 84R) along the sidewalls of the gate structure 75B (e.g. due to the protection provided by the by-product of the plasma etch process) after the plasma etch process as in FIG 8A illustrated. The remaining portions 84R of the second spacer layer 84 along the sidewalls of the gate structure 75B advantageously protect portions of the first spacer layer 86, which are arranged between the remaining portions 84R and the gate structure 75B, from a subsequent etching process, so that the portions of the first Spacer layer 86 is left between the remaining portions 84R and the gate structure 75B after the subsequent etch process to serve as a gate spacer of the gate structure 75B.

In an exemplary embodiment, the anisotropic etch process is a plasma etch process that includes a first plasma etch step followed by a second plasma etch step. The first plasma etch step is performed using tetrafluoromethane (CF ₄ ), and the second plasma etch step is performed using oxygen (O ₂ ). In some embodiments, the first plasma etch step may produce by-products such as polymer, with the polymer covering the top surface and sidewalls of the gate structure 75B, and therefore advantageously damage (e.g., etching the sidewalls of the gate structure) to the gate structure 75B is reduced or eliminated during the first plasma etch step. After the first plasma etch step, the O ₂ plasma used in the second plasma etch step removes the by-product generated by the first plasma etch step.

In some embodiments, the first plasma etch step and the second plasma etch step of the plasma etch process are performed at the same temperature and pressure. In some embodiments, a temperature of the plasma etch process ranges from about 30°C to about 65°C and a pressure of the plasma etch process ranges from about 0.53 Pa to about 6.66 Pa. A CF ₄ flow rate in the first plasma etch step may range from about 100 standard cubic centimeters per minute (sccm) to about 200 sccm. An O ₂ flow rate in the second plasma etch step may range from about 100 sccm to about 200 sccm. Carrier gas such as nitrogen, argon or the like can be used to support the plasma. Each cycle of the first plasma etch step can be performed for a duration ranging from about 5 seconds to about 15 seconds. Each cycle of the second plasma etch step can be performed for a duration ranging from about 5 seconds to about 15 seconds. The number of cycles in the first plasma etch step and in the second plasma etch step may depend, for example, on the thickness of the spacer layer (e.g., 84) to be removed.

Subsequently, as in the 9A until 9C As illustrated, another etch process is performed to remove portions of first spacer layer 86 in region 300 . In some embodiments, the other etch process used to remove the first spacer layer 86 is a wet etch process, for example a chemical etch process using an etchant. The etchant may have a high etch selectivity (e.g., higher etch rate) for the first spacer layer 86 compared to the second spacer layer 84 . The first spacer layer 86 can thus be removed without substantially attacking the second spacer layer 84 (e.g., 84R). A wet etch process using, for example, dilute hydrofluoric acid (dHF), hydrogen peroxide (H ₂ O ₂ ), ozone (O ₃ ), phosphoric acid (H ₃ PO ₄ ), a standard (STD) cleaning fluid (which is a mixture containing deionized water (DIW), ammonium hydroxide (NH ₄ OH), and hydrogen peroxide (H ₂ O ₂ )) or combinations thereof may be performed to remove the exposed first spacer layer 86 in region 300 . In some embodiments, the wet etch process completely removes the exposed first spacer layer 86 in region 300 such that a top surface 64BU of fins 64B and sidewalls of fins 64B (e.g., sidewalls of fins 64B over top surface 62U of isolation regions 62) are exposed after the wet etch process, as shown in FIG 9C illustrated. Note that due to the remaining portion 84R of the second spacer layer 84, portions of the first spacer layer 86 remain along the sidewalls of the gate structure 75B after the wet etch process.

In some embodiments, the wet etch process includes a first step, a second step, a third step, and a fourth step that are performed sequentially. In other words, the second step of the wet etching process is performed after the first step of the wet etching process, the third step of the wet etching process is performed after the second step of the wet etching process, and the fourth step of the wet etching process is performed after the third step of the wet etching process. Specifically, the first step is performed using a mixture containing hydrogen peroxide (H ₂ O2) and ozone (O ₃ ), the second step is performed using dilute hydrofluoric acid (dHF), the third step is performed using phosphoric acid (H ₃ PO ₄ ) and the fourth step is performed using the STD cleaning fluid which is a mixture comprising deionized water (DIW), ammonium hydroxide (NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ ). By performing the first step, the second step, the third step, and the fourth step as described above, the removing process of the first spacer layer 86 can be precisely controlled.

Then, as in the 10A until 10C 1 illustrates epitaxial source/drain regions 80B over exposed top surface 64BU (see FIG 9C ) and the exposed sidewalls of the fins 64B using convenient methods such as Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), Vapor Phase Epitaxy ( vapor phase epitaxy - VPE), selective epitaxial growth (SEG), the like, or a combination thereof. Epitaxial source/drain regions 80B may have surfaces raised above respective top surfaces of fins 64B and may have facets. As in 10C As illustrated, the source/drain regions 80B of the adjacent fins 64B combine to form a continuous epitaxial source/drain region 80B. After the epitaxial source/drain regions 80B have been formed, the patterned mask 88 is removed using an appropriate process such as ashing.

Although that in the 10A until 10C Not illustrated, lightly doped drain (LDD) regions may be formed in fins 64B before epitaxial source/drain regions 80B are formed. LDD areas can be formed by a plasma doping process. The plasma doping process can implant a corresponding type of impurities, such as P-type impurities (for P-type devices) into the fins 64B to form the LDD regions. For example, patterned mask 88 may shield region 200 (e.g., an NMOS region) while P-type impurities are implanted in the LDD regions of fins 64B.

In some embodiments, the resulting FinFET in region 300 is a P-type FinFET, source/drain regions 80B include SiGe and a P-type impurity such as boron or indium. The epitaxial source/drain regions 80B may be implanted with dopants followed by an anneal. The source/drain regions 80B may have an impurity (e.g., dopant) concentration in a range from about 10 ¹⁹ cm ^-3 to about 10 ²¹ cm ^-3 . In some embodiments, the source/drain epitaxial regions 80B may be doped in situ during growth.

The source/drain epitaxial regions 80B are formed directly on the exposed top surface 64BU (see FIG 9C ) and formed on the exposed sidewalls of fins 64B. This is from the process of forming the source/drain epitaxial regions 80A described below with reference to FIGS 11A until 11C is discussed, different. The source/drain epitaxial regions 80B formed by processing in the present disclosure are referred to as having a clad epitaxial structure.

Because of the multilayer structure (e.g., first spacer layer 86 and second spacer layer 84) for the spacer layers and because of the specific etch process (e.g., dry etch followed by wet etch, as discussed above) disclosed, first spacer layer 86 and second spacer layer 84 completely removed over the top surface and sidewalls of fins 64B. As a result, the source/drain epitaxial regions 80B can have a larger volume, resulting in improved device performance, such as lower drain induced barrier loss (DIBL), higher ON current I _on , low higher contact resistance for subsequently formed source/drain contacts, and improved device reliability as examples. Additionally, damage to gate structure 75B and fins 64B is reduced. For example, fin top loss is reduced, damage (e.g., etching) to the sidewalls of fins 64B is reduced, and the critical dimension (CD) of fins 64B is better controlled. As another example, since portions of first spacer layer 86 and second spacer layer 84 (e.g., 84R) remain on the sidewalls of gate structure 75B after the etch process disclosed above, damage to gate structure 75B is reduced or prevented, and the strength of the Gate structure 75B is well controlled. Furthermore, the structure and method disclosed herein reduces the loading effect between interior portions (e.g., portions between adjacent fins 64B) of the isolation regions 62 and exterior portions (e.g., portions not between adjacent fins 64B) of the isolation regions. By using the multi-layer structure disclosed herein for the spacer layer and the specific etching process, a distance between a top surface of the inner portions of the isolation regions 62 and a top surface of the outer portions of the isolation regions 62 can be reduced from 25 nm to 5 nm.

Below are in the 11A until 11C removing the second spacer layer 84 in region 200 and the remaining portion 84R of the second spacer layer 84 in region 300 using an appropriate process such as an etch process. A suitable etchant such as phosphoric acid (H ₃ PO ₄ ) can be used for the etching process. Next, the first spacer layer 86 is patterned in the region 200 using, for example, an isotropic etch process to remove portions of the first spacer layer 86 over the top surface of the gate structure 75A and over the top surface of the fins 64A. A patterned mask layer (not shown), such as a patterned photoresist, may be used to cover region 300 while first spacer region 86 in region 200 is patterned. The patterned mask layer is then removed using an appropriate method such as ashing. After patterning the first spacer layer 86 as described above, remaining portions of the first spacer layer 86 (see FIG 11A ), such as those along the sidewalls of gate structures 75A and 75B, are used as the gate spacers (e.g., low-κ gate spacers) of the corresponding gate structure. The portions of the first spacer layer 86 along the sidewalls of the gate structures 75A and 75B may thus be called spacers 86 below.

Then, although not illustrated, LDD regions may be formed in the fins 64A before the source/drain epitaxial regions 80A are formed. LDD areas can be formed by a plasma doping process. The plasma doping process can implant a corresponding type of impurities, such as N-type impurities (for N-type devices) into the fins 64A to form the LDD regions. For example, some patterned mask layer (not shown) may be formed to shield region 300 (e.g., a PMOS region) while N-type impurities are implanted in the LDD regions of the fins 64A. The patterned mask layer can be removed after the LDD areas have been formed.

Then epitaxial source/drain regions 80A are formed in the fins 64A. The epitaxial source/drain regions 80A may be formed by etching the fins 64A (e.g., etching the LDD regions within the fins 64A) to form recesses, and epitaxially growing a material in the recess using appropriate methods such as metal-organic CVD CVD (MOCVD), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), Vapor Phase Epitaxy (VPE), Selective Epitaxial Growth (SEG), the like, or a combination thereof .

As in 11A As illustrated, gaps 87 (e.g., space) between the source/drain regions 80B and the spacers 86 of the gate structure 75B due to the removal of the remaining portions 84R (see FIG 10A ) of the second spacer layer 84 are formed. The source/drain epitaxial regions 80B may be spaced from the spacers 86 by gaps 87, for example. The width of the gaps 87 can be determined by the width of the remaining portions 84R of the second spacer layer 84'. The width of the gaps 87 can be between about 0 nm and 3 nm, for example, although other dimensions are also possible. In contrast, the source/drain epitaxial region 80A physically touches the gate structure 75A spacers 86, and thus in some embodiments there is no gap between the source/drain epitaxial region 80A and the gate structure 75A spacers. In some embodiments, a distance between the source/drain epitaxial regions 80B and the gate structure 75B is greater than a distance between the epitaxial source/drain regions 80A and the gate structure 75A.

As in the 11B As illustrated, etching the LDD regions within fins 64A recesses a top surface 64AU of fins 64A. Etching the LDD region within fins 64A may also remove portions of dielectric layer 66 overlying top surface 64AU, as shown in FIG 11B 11-16, although in other embodiments etching the LDD region within fins 64A does not remove dielectric layer 66. FIG. In the illustrated embodiment of FIG 11B the recessed top surface 64AU lies above the top surface 62U of the isolation regions 62. In other embodiments, the recessed top surface of the fins 64A may under (see e.g. 64AU'') or flush with (see e.g. 64AU') the top surface 62U of the Isolation areas 62 are. As in the 11B and 11C As illustrated, a top surface 64BU of fins 64B extends further away from top surface 62U of isolation regions 62 than recessed top surface 64AU/64AU'/64AU'' of fins 64A. In some embodiments, top surface 64BU is higher (e.g., extends farther from top surface 62U) than recessed top surface 64AU/64AU'/64AU'' by about 18 nm to about 23 nm.

With reference to 11B As a result of etching the LDD regions within the fins 64A, a sub-section of the source/drain epitaxial regions 80A grows in the recess between the first spacer layer 86 first. Once the recess is filled, upper portions of epitaxial source/drain regions 80A are formed over fins 64A and may combine to form continuous source/drain regions 80A. In some embodiments, a bottom surface 80AL of epitaxial source/drain regions 80A contacts recessed top surface 64AU/64AU'/64AU'' of fin 64A, as shown in FIG 11B illustrated. In contrast, a bottom surface 80BL of epitaxial source/drain regions 80B may be below top surface 64BU of fin 64B, as shown in FIG 11C illustrated lying. In some embodiments, the bottom surface 80AL of the source/drain epitaxial regions 80A is lower (e.g., closer to the top major surface 50U of the substrate 50) than the bottom surface 80BL of the source/drain epitaxial regions 80B.

As in the 11A and 11B As illustrated, the source/drain epitaxial regions 80A may include raised surfaces above respective surfaces of the fins 64A (e.g., raised above the non-recessed portions of the fins 64A) and may have facets. The source/drain regions 80A of the adjacent fins 64A may combine to form a continuous epitaxial source/drain region 80A. In some embodiments, the resulting FinFET in region 200 is an N-type FinFET, and source/drain regions 80A include silicon carbide (SiC), silicon phosphorus (SiP), phosphorus-doped silicon-carbon (SiCP), or the like.

The epitaxial source/drain regions 80A can be implanted with dopants followed by an anneal. The source/drain regions 80A may have an impurity (e.g., dopant) concentration in a range from about 10 ¹⁹ cm ^-3 to about 10 ²¹ cm ^-3 . In some embodiments, the source/drain epitaxial regions may be doped in situ during growth.

As in the 12A until 12C 1, a contact etch stop layer (CESL) 105 (e.g., conformed) is then deposited over the structure shown in FIGS 11A until 11C 1 is formed, and thereafter a first interface dielectric (ILD) 90 is formed over the CESL 105 . The CESL can comprise any convenient material, such as TiN, and can be formed by any convenient method, such as PVD, CVD, or the like. In some embodiments, the first ILD 90 is formed from a dielectric material such as silicon oxide, phosphosilicate glass (PSG), boron doped silicon glass (BSG), and undoped silicate glass (USG) or the like and can be deposited by any convenient method such as CVD, PECVD or FCVD. A planarization process, such as a CMP process, may be performed to planarize the top surface of the first ILD 90 such that the top surface of the first ILD 90 is level with the top surface of the gate 68 . The mask 70 (see 11A ), portions of the first spacer layer 86, and portions of the CESL 105 over the top surface of the gate 68 may be removed by the CMP process. Thus, after the CMP process, the top surface of the gate 86 is exposed in some embodiments. In the example of 12B and 12C An air gap exists between the epitaxial source/drain region 80A (or 80B) and the underlying isolation regions 62.

The 13 until 16 12 illustrate cross-sectional views of the FinFET device 100 at further processing steps along cross-section II. As in FIG 13 illustrated, a gate-last process (occasionally replacement Gate-Pro cess) executed. In a gate-last process, the gate 68 and gate dielectric 66 (see Fig 12A ) are considered as dummy structures and are removed and replaced with an active gate (also called a replacement gate) and an active gate dielectric. In some embodiments, the active gate is a metal gate.

With reference to 13 the gate 68 and the gate dielectric 66 directly under the gate 68 are removed in one or more etch steps, respectively, such that depressions (not shown) are formed between respective spacer layers 86 . The recesses are filled by subsequently forming a gate dielectric layer 96, a barrier layer 94, a seed layer 92 and a gate electrode 98 in the recesses.

In some embodiments, the gate dielectric layer 96 is conformally formed in the recesses. Gate dielectric layer 96 may include silicon dioxide. The silicon oxide may be formed by any convenient oxidation and/or deposition process. In some embodiments, the gate dielectric layer 96 comprises a high-x dielectric layer such as hafnium oxide (HfO ₂ ). Alternatively, the high-x dielectric layer may comprise other high-κ dielectrics such as TiO ₂ , HfZrO, Ta ₂ O ₃ , HfSiO ₄ , ZrO ₂ , ZrSiO ₂ , combinations thereof, or other appropriate material. The high-x dielectric layer can be formed by ALD, PVD, CVD, or other appropriate methods.

A barrier layer 94 is then conformally formed over gate dielectric layer 96 . The barrier layer 94 may prevent or reduce material out-diffusion of a subsequently formed gate electrode (e.g., 98). Barrier layer 94 may comprise a conductive material such as titanium nitride, although other materials such as tantalum nitride, titanium, tantalum, or the like may alternatively be used. The barrier layer 94 may be formed using a CVD process such as plasma enhanced CVD (PECVD). Other alternative processes such as sputtering or Metal Organic Chemical Vapor Deposition (MOCVD), ALD, may alternatively be used.

A seed layer 92 is then conformedly formed over the dielectric barrier layer 94 . The seed layer may comprise copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), the like, or a combination thereof and may be formed by atomic layer deposition (ALD), sputtering, physical vapor deposition (Physical Vapor Deposition - PVD) or the like are deposited. In some embodiments, the seed layer is a metal layer, comprising a single layer or a composite layer comprising a plurality of sub-layers formed from different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer.

A conductive material is then formed over the seed layer to fill the recesses to form gate electrode 98 . The conductive material may comprise tungsten, although other suitable materials such as aluminum, copper, ruthenium, silver, gold, rhodium, molybdenum, nickel, cobalt, cadmium, zinc, alloys thereof, combinations thereof, and the like may alternatively be employed. The conductive material can be formed by electroplating, PVD, CVD, or any convenient deposition process. A planarization process, such as a CMP, may be performed to remove excess portions of gate dielectric layer 96, barrier layer 94, seed layer 92, and gate electrode 98, leaving excess portions, for example, over the top surface of first ILD 90 are arranged. The remaining portions of the gate dielectric layer 96, the barrier layer 94, the seed layer 92, and the gate electrode 98 in the recesses form the replacement gates 97 of the FinFET device 100.

Then referring to 14 a second ILD 95 is deposited over the first ILD 90. In one embodiment, the second ILD 95 is a flowable film formed using a flowable CVD process. In some embodiments, the second ILD 95 is formed from a dielectric material, such as PSG, BSG, BPSG, USG, or the like, and may be deposited using any convenient method, such as CVD and PECVD. Contact openings 91 and 93 for contact plugs 102 (see 16 ) are formed by the first ILD 90 and/or the second ILD 95. Contact opening 91 is formed through, for example, second ILD 95 and exposes replacement gate 97, while contact openings 93 are formed through first ILD 90 and second ILD 95 and expose source/drain regions 80A/80B.

Then be in 15 Silicide regions 82 are formed in the source/drain regions 80A/80B and a barrier layer 104 is formed over the silicide regions 82 and the second ILD 95. FIG. In some embodiments, the silicide regions 82 are formed by depositing over the source/drain regions 80A/80B a metal capable of reacting with semiconductor materials (e.g., silicon, germanium) to form silicide or germanide regions. The metal can be nickel, cobalt, titanium, Tantalum, platinum, tungsten or other precious metals, other refractory metals, rare earth metals or their alloys. A thermal anneal process is then performed so that the deposited metal reacts with the source/drain regions 80A/80B to form silicide regions 82. FIG. After the thermal annealing process, unreacted metal is removed.

Barrier layer 104 is conformally formed over silicide regions 82 and second ILD 95 and lines sidewalls and bottoms of contact openings 91/93. The barrier layer 104 may comprise an electrically conductive material, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or the like, and may be formed using a CVD process, such as plasma enhanced CVD (PECVD). . Other alternative processes such as sputtering or metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD) atomic layer deposition (ALD) may alternatively be used.

Then in 16 a seed layer 109 is formed over the barrier layer 104 and an electrically conductive material 110 is formed over the seed layer 109 . The seed layer 109 can be deposited by PVD, ALD, or CVD and can be formed of tungsten, copper, or copper alloys, although other suitable methods and materials can alternatively be used.

Once the seed layer 109 has been formed, the conductive material 110 can be formed on the seed layer 109 to fill the contact openings 91/93. Conductive material 110 may include tungsten, although other suitable materials such as aluminum, copper, tungsten nitride, ruthenium, silver, gold, rhodium, molybdenum, nickel, cobalt, cadmium, zinc, alloys thereof, combinations thereof, and the like may alternatively be employed. Any convenient deposition method such as PVD, CVD, ALD, plating (e.g., electroplating), and reflow may be used to form the conductive material 110 .

Once contact openings 91/93 have been filled, excess barrier layer 104, seed layer 109, and excess conductive material 110 outside of contact openings 91/93 may be removed by a planarization process such as CMP, although any convenient removal process may be used. Contact plugs 102 are therefore formed in the contact openings 91/93. Although contact plugs 102 over the source/drain regions 80A/80B and over the replacement gate 97 are in a same cross-section in FIG 16 1, the contact plugs 102 may be in different cross-sections in the FinFET device 100. FIG.

17 1 illustrates a flow diagram of a method of forming a semiconductor device in accordance with some embodiments. You have to understand that the in 17 The execution method shown is just one example of many possible execution methods. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. Various steps as in 17 illustrated may be added, removed, replaced, rearranged, and repeated, for example.

With reference to 17 at step 1010, a first fin is formed overhanging a substrate, the first fin having a PMOS region and an NMOS region. At step 1020, a first gate structure is formed over the first fin in the PMOS region. At step 1030, a first spacer layer is formed over the first fin and the first gate structure. At step 1040, a second spacer layer is formed over the first spacer layer. At step 1050, a first etch process is performed to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region. At step 1060, a second etch process is performed to remove the first spacer layer from the top surface and sidewalls of the first fin in the PMOS region. At step 1070, a first source/drain material is epitaxially grown over the first fin in the PMOS area, the first source/drain material extending along the top surface and sidewalls of the first fin in the PMOS area .

Embodiments can achieve advantages. The disclosed multilayer spacer structure including the first spacer layer 86 and the second spacer layer structure 84, along with the disclosed etch process (e.g., dry etch followed by wet etch), removes the spacer layers (e.g., 84 and 86) from the top surface and sidewalls of the fins 64B , while retaining portions of the spacer layers on the sidewalls of gate structure 75B. The cladding epitaxial structure (e.g. 80B) is formed on the top surface and sidewalls of the fins 65B with a large volume, resulting in improved device performance, such as lower drain induced reverse leakage (DIBL), higher ON current I _on , lower contact resistance and improved component reliability results. Additionally, damage to the gate structure 75B and fins 64B is reduced, resulting in better control of the profile of the FinFET device formed. Furthermore, the loading effect between tian inner portions of the isolation regions 62 and outer portions of the isolation regions 62 is reduced. Another benefit is improved PMOS channel stress due to the cladding epitaxial structure enabled by the present disclosure.

The invention relates to a method comprising: forming a first fin protruding over a substrate, the first fin having a PMOS region; forming a first gate structure over the first fin in the PMOS area; forming a first spacer layer over the first fin and the first gate structure; forming a second spacer layer over the first spacer layer; performing a first etch process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; performing a second etch process to remove the first spacer layer from the top surface and sidewalls of the first fin in the PMOS region; and epitaxially growing a first source/drain material over the first fin in the PMOS area, the first source/drain material extending along the top surface and sidewalls of the first fin in the PMOS area. In one embodiment, the first spacer layer and the second spacer layer are formed from different materials. In one embodiment, performing the first etch process includes performing an anisotropic etch process. In one embodiment, after performing the first etch process, the first spacer layer is exposed over the top surface and sidewalls of the first fin in the PMOS region, and a remaining portion of the second spacer layer extends along sidewalls of the first gate structure, and the first spacer layer lies between the remaining portion of the second spacer layer and the first gate structure. In one embodiment, the second etch process exposed the top surface and sidewalls of the first fin in the PMOS region. In one embodiment, performing the first etch process includes performing a plasma etch process, the plasma etch process including a first plasma etch step and a second plasma etch step, the first plasma etch step being performed using tetrafluoromethane (CF ₄ ). , and the second plasma etching step is performed using oxygen (O ₂ ). In one embodiment, performing the second etch process includes performing a chemical etch process, the chemical etch process including a first step, a second step, a third step, and a fourth step performed sequentially. In one embodiment, the first step is performed using a mixture containing hydrogen peroxide (H ₂ O ₂ ) and ozone (O ₃ ), the second step is performed using dilute hydrofluoric acid (dHF), the third step is performed using phosphoric acid (H ₃ PO ₄ ) and the fourth step is carried out using the STD cleaning fluid which is a mixture comprising deionized water (DIW), ammonium hydroxide (NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ ). In one embodiment, the first fin further includes an NMOS area, the method further includes forming a second gate structure over the first fin in the NMOS area, the first spacer layer and the second spacer layer over the second gate structure are formed, forming a patterned mask layer to cover the NMOS region prior to performing the first etch process; and removing the patterned mask layer after epitaxially growing the first source/drain material. In one embodiment, the method further comprises, after epitaxially growing the first source/drain material, removing remaining portions of the second spacer layer in the PMOS region and the NMOS region; and epitaxially growing a second source/drain material over the first fin in the NMOS region. In one embodiment, epitaxially growing the second source/drain material comprises removing a portion of the first spacer layer to expose a top surface of the first fin in the NMOS region; recessing the top surface of the first fin in the NMOS area; and epitaxially growing the second source/drain material over the recessed top surface of the first fin in the NMOS region.

The invention further relates to a method comprising: forming a fin protruding over a substrate, the fin having a PMOS region and an NMOS region; forming a first gate over the fin in the PMOS area; forming a second gate over the fin in the NMOS area; forming a first spacer layer over the fin, the first gate and the second gate; forming a second spacer layer, distinct from the first spacer layer, over the first spacer layer; forming a patterned mask layer to cover the NMOS area while leaving the PMOS area exposed; and after forming the patterned mask layer, performing a first etch process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; performing a second etch process to remove the first spacer layer from the top surface and the sidewalls of the fin in the PMOS area, exposing the top surface and sidewalls of the fin in the PMOS area; and epitaxially growing a first semiconductor material along the top surface and sidewalls of the fin in the PMOS region. In one embodiment, the first spacer layer is formed using a material selected from the group consisting essentially of silicon oxycarbide, silicon oxycarbonitride, and silicon carbonitride, and the second spacer layer is formed using a material selected from the group which essentially consists of silicon nitride and silicon carbonitride. In one embodiment, the first etch process comprises a dry etch process and the second etch process comprises a wet etch process. In one embodiment, performing the first etch process includes performing a plasma etch process using carbon monoxide, tetrafluoromethane, oxygen, or ozone. In one embodiment, the method further comprises, after epitaxially growing the first semiconductor material, removing the patterned mask layer; recessing a top surface of the fin in the NMOS area; and epitaxially growing a second semiconductor material over the recessed top surface of the fin in the NMOS region.

The invention also relates to a semiconductor device comprising: a fin protruding from a substrate, the fin having a first portion and a second portion, the first portion being in a PMOS region and the second portion being in a PMOS region NMOS area is; a first gate structure over the first portion of the fin in the PMOS area; a second gate structure over the second portion of the fin in the NMOS area; first source/drain epitaxial regions on opposite sides of the first gate structure and over the first portion of the fin, the first source/drain epitaxial regions being in the PMOS region and extending along a first top surface and first sidewalls of the first section of the fin; and second source/drain epitaxial regions on opposite sides of the second gate structure and over the second portion of the fin, the second source/drain epitaxial regions in the NMOS region and over a second top surface of the second portion of the fin are in the NMOS area; first spacers on opposite sidewalls of the second portion of the fin in the NMOS area, wherein opposite sidewalls of the first portion of the fin in the PMOS area are free of first spacers. In one embodiment, a bottom surface of the second epitaxial source/drain regions contacts the second top surface of the second portion of the fin in the NMOS region. In one embodiment, the first top surface of the first portion of the fin extends further from the substrate than the second top surface of the second portion of the fin.

Claims (18)

Procedure, which includes: forming a first fin (64) protruding over a substrate (50), the first fin (64) having a PMOS region (300); forming a first gate structure (75B) over the first fin (64) in the PMOS region (300); forming a first spacer layer (86) over the first fin (64) and the first gate structure (75B); forming a second spacer layer (84) over the first spacer layer (86); performing a first etch process to remove the second spacer layer (84) from a top surface and sidewalls of the first fin (64) in the PMOS region (300); performing a second etch process to remove the first spacer layer (86) from the top surface and sidewalls of the first fin (64) in the PMOS region (300); and epitaxially growing a first source/drain material (80B) over the first fin (64) in the PMOS region (300), the first source/drain material (80) along the top surface (64U) and the sidewalls of the first fin (64) extend in the PMOS region (300); wherein the first fin (64) further has an NMOS region (200), the method further comprising: forming a second gate structure (75A) over the first fin (64) in the NMOS region (200), wherein the first spacer layer (86) and the second spacer layer (84) are formed over the second gate structure (75A). ; forming a patterned mask layer to cover the NMOS region (200) prior to performing the first etch process; and removing the structured mask after the epitaxial growth of the first source/drain material (80B). procedure after claim 1 wherein the first spacer layer (86) and the second spacer layer (84) are formed of different materials. procedure after claim 1 or 2 , wherein performing the first etch process comprises performing an anisotropic etch process. procedure after claim 3 , wherein after performing the first etching process, the first spacer layer (86) is exposed over the top surface (64U) and sidewalls of the first fin (64) in the PMOS region (300), and a remaining portion of the second spacer layer (84) along sidewalls of the first gate structure (75B) and wherein the first spacer layer (86) lies between the remaining portion of the second spacer layer (84) and the first gate structure (75B). The method of any preceding claim, wherein performing the second etch process exposes the top surface (64U) and sidewalls of the first fin (64) in the PMOS region (300). The method of any preceding claim, wherein performing the first etch process comprises performing a plasma etch process, the plasma etch process comprising a first plasma etch step and a second plasma etch step, the first plasma etch step using tetrafluoromethane ( CF ₄ ) is performed, and the second plasma etch step is performed using oxygen (O ₂ ). The method of any preceding claim, wherein performing the second etch process comprises performing a chemical etch process, the chemical etch process comprising a first step, a second step, a third step and a fourth step performed sequentially. procedure after claim 7 , wherein the first step is performed using a mixture containing hydrogen peroxide (H ₂ O ₂ ) and ozone (O ₃ ), the second step is performed using dilute hydrofluoric acid (dHF), the third step is performed using phosphoric acid (H ₃ PO ₄ ) and the fourth step is carried out using a mixture comprising deionized water (DIW), ammonium hydroxide (NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ ). procedure after claim 1 The further comprising: after epitaxially growing the first source/drain material (80), removing remaining portions of the second spacer layer (84) in the PMOS region (300) and in the NMOS region (200); and epitaxially growing a second source/drain material (80A) over the first fin (64) in the NMOS region (200). procedure after claim 9 wherein epitaxially growing the second source/drain material (80a) comprises: removing a portion of the first spacer layer (86) around an upper surface (64AU) of the first fin (64) in the NMOS region (200) to expose recessing the top surface (64AU) of the first fin (64) in the NMOS area (200); and epitaxially growing the second source/drain material (80A) over the recessed first surface (64AU) of the first fin (64) in the NMOS region (200). Procedure, which includes: forming a fin (64) protruding over a substrate (50), the fin (64) having a PMOS region (300) and an NMOS region (200); forming a first gate structure (75B) over the fin (64) in the PMOS region (300); forming a second gate structure (75A) over the fin (64) in the NMOS region (200); forming a first spacer layer (84) over the fin (64), the first gate (75B) and the second gate (75A); forming a second spacer layer (84), distinct from the first spacer layer (86), over the first spacer layer (86); forming a patterned mask layer to cover the NMOS region (200) while leaving the PMOS region (300) exposed; and after forming the patterned mask layer, performing a first etch process to remove the second spacer layer (84) from a top surface (64BU) and sidewalls of the fin (64) in the PMOS region (300); performing a second etch process to remove the first spacer layer (86) from the top surface (64AU) and sidewalls of the fin (64) in the PMOS region (300), thereby exposing the top surface (64AU) and sidewalls of the fin (64 ) are exposed in the PMOS region (300); and epitaxially growing a first semiconductor material (80B) along the top surface (64BU) and sidewalls of the fin (64) in the PMOS region (300). procedure after claim 11 wherein the first spacer layer (86) is formed using a material selected from the group consisting essentially of silicon oxycarbide, silicon oxycarbonitride and silicon carbonitride, and wherein the second spacer layer (84) is formed using a material consisting of is selected from the group consisting essentially of silicon nitride and silicon carbonitride. procedure after claim 11 or 12 , wherein the first etching process is a dry etching process comprises, and the second etching process comprises a wet etching process. A method according to any of the foregoing Claims 11 until 13 , wherein performing the first etch process comprises performing a plasma etch process using carbon monoxide, tetrafluoromethane, oxygen, or ozone. A method according to any of the foregoing Claims 11 until 14 , further comprising: after epitaxially growing the first semiconductor material (80B), removing the patterned mask layer; recessing an upper surface (64AU) of the fin (64) in the NMOS area (200); and epitaxially growing a second semiconductor material (80A) over the recessed first surface (64AU) of the fin (64) in the NMOS region (200). A semiconductor device (100) comprising: a fin (64) protruding above a substrate (50), the fin (64) having a first portion (64B) and a second portion (64A), the first portion (64B) being in a PMOS region (300 ) and the second portion (64A) is in an NMOS region (200); a first gate structure (75B) over the first portion (64B) of the fin (64) in the PMOS region (300); a second gate structure (75A) over the second portion (64A) of the fin (64) in the NMOS region (200); first source/drain epitaxial regions (80B) on opposite sides of the first gate structure (75B) and over the first portion (64B) of the fin (64), the first source/drain epitaxial regions (80B) in the PMOS region (300) and extending along a first top surface (64BU) and first sidewalls of the first portion (64B) of the fin (64); and second source/drain epitaxial regions (80A) on opposite sides of the second gate structure (75A) and over the second portion (64A) of the fin (64), the second source/drain epitaxial regions (80A) in the NMOS region (200) and overlying a second top surface (64AU) of the second portion (64A) of the fin (64) in the NMOS region (200), and first spacers on opposite sidewalls of the second portion (64A) of the fin (64) in the NMOS region (200), opposite sidewalls of the first portion (64B) of the fin (64) in the PMOS region (300) being free of first are spacers. Semiconductor device (100) according to Claim 16 wherein a bottom surface (80AL) of the second epitaxial source/drain regions (80A) contacts the second top surface (64AU) of the second portion (64A) of the fin (64) in the NMOS region (200). A semiconductor device (100) according to any one of the preceding Claims 16 until 17 wherein the first top surface (64BU) of the first portion (64B) of the fin (64) extends farther from the substrate (50) than the second top surface (64AU) of the second portion (64A) of the fin (64).

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