DE102014019866B3 - Semiconductor device with overload current capacity - Google Patents

Abstract

A semiconductor device (1) comprising: - a semiconductor region (11), the semiconductor region (11) having charge carriers of a first conductivity type; - a transistor cell (1-1) contained in the semiconductor region (11); - a transistor cell (1-1 ) containing semiconductor channel region (111), wherein the semiconductor channel region (111) has a first doping concentration of charge carriers of a second conductivity type which is complementary to the first conductivity type, and wherein a transition between the semiconductor channel region (111) and the semiconductor region (11) has a first pn- - A semiconductor auxiliary region (112) which is contained in the semiconductor region (11) and is different from the semiconductor channel region (111), the semiconductor auxiliary region (112) having a second doping concentration of charge carriers of the second conductivity type, a transition between the semiconductor auxiliary region (112) and the semiconductor region (11) forms a second pn junction (11-2), wherein ei the second pn junction (11-2) is arranged deeper in the semiconductor region (11) than the first pn junction (11-1), and wherein the semiconductor auxiliary region (112) is arranged closest to the semiconductor channel region (111) compared to every other semiconductor region of the semiconductor device (1) which comprises charge carriers of the second conductivity type and which forms a further pn junction to the semiconductor region (11); and - the semiconductor channel region (111) is delimited by a first trench (13) and a second trench (12), the first trench (13) comprising a first electrode (131) and a first dielectric (132), the second trench a gate electrode (121) for controlling the transistor cell (1-1) and a second dielectric (122), the respective dielectric (132, 122) the respective electrode (131, 121) of the respective trench (13, 12) of the semiconductor body (11 ) isolated, wherein the semiconductor auxiliary region (112) is arranged in contact with the first and the second trench (12, 13) and with a further first trench (13).

Description

TECHNICAL AREA

This description relates to embodiments of semiconductor devices, embodiments of circuit arrangements comprising a semiconductor device and a gate driver, and further embodiments of methods for operating a semiconductor device. In particular, this description relates to embodiments of a reverse conducting bipolar transistor with insulated gate electrode, hereinafter also referred to as “RC-IGBT”, and embodiments of a metal-oxide-semiconductor-controlled diode, hereinafter also referred to as “MOS-controlled diode” or “MCD” that enable an overload current, such as an overload current, to be passed in the reverse direction.

BACKGROUND

Many functions of modern devices in automotive, consumer, and industrial applications, such as converting electrical energy and driving an electric motor or machine, rely on semiconductor devices. For example, insulated gate bipolar transistors (IGBT) and diodes are used for various applications including, but not limited to, switches in power supplies and power converters.

A specific example of these applications is so-called high voltage direct current (HVDC) transmission. This type of energy transfer can be used to transport a large amount of electrical energy over a long distance of several kilometers, even several hundreds of kilometers. In short, an alternating current (AC) or alternating voltage is generated by an AC generator such as a wind turbine. After the conversion to the high voltage level, the AC voltage / the AC current is rectified by a conversion station to a direct current (DC) or a DC voltage. The DC voltage / current is fed into an HVDC transmission line. A further conversion station can be installed at a receiving end of the HVDC transmission line in order to convert the received DC energy into AC energy for further distribution.

One approach is to use reverse-conducting IGBTs (RC-IGBTs) in such conversion stations.

The US 2014/0138738 A1 describes an IGBT in which control electrodes are placed in trenches.

DESCRIPTION

According to an embodiment, a semiconductor device according to independent claim 1 is provided.

Those skilled in the art to which this invention pertains will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings.

Figure list

The parts in the figures are not necessarily to scale, emphasis instead being placed on illustrating the principles of the invention. In addition, the same reference symbols denote the corresponding parts in the figures. The following applies in the drawings:

• 1 schematically illustrates a portion of a vertical cross section of a semiconductor device in accordance with one or more embodiments;
• 2 schematically illustrates a portion of a vertical cross section of a semiconductor device in accordance with one or more embodiments;
• 3 schematically illustrates a portion of a vertical cross section of a semiconductor device in accordance with one or more embodiments;
• 4th schematically illustrates, in a perspective view, a portion of a vertical cross section of a semiconductor device in accordance with one or more embodiments;
• 5 schematically illustrates, in a perspective view, a portion of a vertical cross section of a semiconductor device in accordance with one or more embodiments;
• 6th schematically illustrates a circuit diagram of a circuit arrangement according to one or more embodiments;
• 7th schematically illustrates a flow diagram of a method of operating a semiconductor device in accordance with one or more embodiments;
• 8th FIG. 11 schematically and by way of example illustrates a diagram indicating an amount of charge contained in a semiconductor device in a reverse current mode depending on a voltage of a gate signal; FIG.
• 9A-D illustrate schematically and by way of example methods for operating a circuit arrangement in accordance with one or more embodiments;
• 10 illustrates schematically and by way of example a circuit diagram of a circuit arrangement according to one or more embodiments;
• 11 Figure 11 schematically illustrates a circuit diagram of a portion of a power converter.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which there are shown, for purposes of illustration, specific embodiments in which the invention may be practiced.

In this regard, directional terminology such as "top", "bottom", "bottom", "front", "back", "back", "front", "back" etc. may be used with reference to the orientation of the figures being described will. Because parts of embodiments can be arranged in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It goes without saying that further embodiments can be used and structural and logical changes can be made without departing from the scope of protection of the present invention. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

Reference will now be made in detail to the various embodiments, one or more examples of which are illustrated in the figures. Each example is provided for purposes of explanation and is not to be construed as limiting the invention. For example, features illustrated or described as part of one embodiment may be used for or in conjunction with other embodiments to yield yet another embodiment. It is intended that the present invention cover such modifications and variations. The examples are described using specific language which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For the sake of clarity, the same elements or manufacturing steps have been denoted by the same reference numerals in the different drawings, unless otherwise indicated.

The term “horizontal” as used in this description aims to describe an orientation that is essentially parallel to a horizontal surface of a semiconductor substrate or a semiconductor region. This can be the surface of a wafer or a bare chip, for example.

The term “vertical”, as used in this description, aims to describe an orientation which is arranged essentially perpendicular to the horizontal surface, i.e. parallel to the normal direction of the surface of the semiconductor substrate or the semiconductor region.

In this description, n-doped is referred to as “first conductivity type”, while p-doped is referred to as “second conductivity type”. Alternatively, opposing doping ratios can be used, so that the first conductivity type can be p-doped and the second conductivity type can be n-doped.

In the context of the present description, the terms "in ohmic contact", "in electrical contact", "in ohmic connection" and "electrically connected" aim to describe that a low-resistance electrical connection or a low-resistance current path between two areas, sections , Areas or parts of a semiconductor device or between different connections of one or more devices or between a connection or a metallization or an electrode and an area or part of a semiconductor device. Furthermore, in the context of the present description, the term “in contact” aims to describe that there is a direct physical connection between two elements of the respective semiconductor device; for example, a transition between two elements in contact with one another may not include another intermediate element or the like.

Specific embodiments described in this description relate, without being limited thereto, to a monolithically integrated RC-IGBT or a monolithically integrated MCD, for example a monolithically integrated power RC-IGBT or a monolithically integrated power MCD, which are used within an electrical power converter e.g. a power converter for HVDC applications. For example, both a transistor section and a diode section can be implemented on a common chip in a monolithically integrated RC-IGBT. It is to be understood, however, that according to one or more of this specification Embodiments described, the transistor section and the diode section of an RC-IGBT can be arranged on chips which are separated from one another. The separated diode section can be viewed as an MCD.

As used throughout the present specification, the term "forward current" can be a current that flows in one direction through the semiconductor device, e.g., from a back side of the semiconductor device to a front side of the semiconductor device. Such a forward current can be carried, for example, by means of a transistor cell of the semiconductor device. Furthermore, as used throughout the present specification, the term "reverse current" can be a current that flows through the semiconductor device in a different direction, for example from a front side of the semiconductor device to a rear side of the semiconductor device. For example, such a reverse current can be carried by a diode cell and / or by an auxiliary cell of the semiconductor device, as will be described in more detail below. In certain embodiments, the semiconductor device can be configured to carry both forward current and reverse current. In other words, the semiconductor device can be operated in both a forward current mode and a reverse current mode, for example when the semiconductor device is an RC-IGBT. In further embodiments, the semiconductor device may only be configured to carry a load current in a single direction, such as the reverse direction, and not a forward current, e.g., when the semiconductor device is an MCD. In other words, the term “reverse current” or “reverse current mode”, as used in the present description, can refer to a load current direction that is typical for an MCD, e.g. a load current flowing, in a technical current direction, from an anode section of an MCD flows to a cathode region of an MCD. It is therefore understood that the term “reverse current” within the present description typically refers to the load current that is carried through an MCD or through a diode section of an RC-IGBT. Therefore, when referring only to an MCD here, the term "reverse current" is used to describe a load current flowing in one direction from an anode section to a cathode region, although such a load current direction would ordinarily not be described as a reverse current, but rather as a Forward current of an MCD.

The term “power semiconductor device” as used in this specification aims to describe a semiconductor device on a single chip with high voltage blocking and / or high current loading capacities. In other words, the power semiconductor devices are intended for high currents, typically in the ampere range, e.g., up to several hundred amps, and / or high voltages, typically above 1,000 V, more typically 6,000 V and higher.

For example, power semiconductor devices can be used for so-called high voltage direct current (HVDC) transmission applications. This type of energy transfer can be used to transport a large amount of electrical energy over a long distance of several hundreds of kilometers, even several thousand kilometers. In short, an alternating current (AC) or alternating voltage is generated by an AC generator such as a wind turbine. After the conversion to the high voltage level, the AC voltage / the AC current is rectified by a conversion station to a direct current (DC) or a DC voltage. The DC voltage / current is fed into an HVDC transmission line. A further conversion station for converting the received DC energy into AC energy for further distribution can be installed at a receiving end of the HVDC transmission line.

One approach is to use RC-IGBT in such conversion stations. For example illustrates 11 schematically a circuit diagram of a section of a power converter 5 , which is briefly discussed below: The power converter 5 has a so-called modular multilevel converter (MMC) topology. The MMC topology is generally suitable for applications in HVDC transmission. The power converter 5 includes a converter branch that has a first RC-IGBT 51 and a second RC-IGBT 52 includes. The converter branch is coupled to the AC connections 55-1 and 55-2 for receiving and / or outputting an AC voltage. On the other hand, the converter branch is coupled with DC connections, for example with a capacitor 53 that can be used to get one through the first RC-IGBT 51 and the second RC-IGBT 52 to buffer rectified DC voltage or to get one through the first RC-IGBT 51 and the second RC-IGBT 52 to buffer the reversed DC voltage.

The first RC-IGBT 51 includes a first transistor 511 and a first diode 512 , whereby these two components can be implemented on a common chip. Accordingly, the second RC comprises IGBT 52 a second transistor 521 and a second diode 522 , whereby these two components can also be implemented on a common chip. The first diode 511 and the second diode 522 Also known as "freewheeling diodes" (FWD), are configured to carry a load current in a direction that is the opposite of one of the Transistors 511 and 521 carried load current, which is a forward direction. The change in direction of the load current is also referred to as “commutation”, eg the load current from the second transistor 521 to the second diode 522 commutate or from the second diode 522 to the second transistor 521 .

There may be situations in which an overload current may have to be temporarily routed through the converter branch, such as through the second RC-IGBT 52 . Such a situation can arise, for example, due to a short circuit between the DC connections of the converter (also known as a “DC pole-to-pole fault”). In other situations, the overload current can come from the AC side. However, such an overload current, which can be a multiple of a nominal load current, typically exceeds the current-carrying capacity of the free-wheeling diodes, for example the current-carrying capacity of the free-wheeling diode 522 .

For example, the overload current, e.g., the reverse overload current, can be at least ten times as high as the rated load current or even higher, such as about twenty times as high as the rated load current. Accordingly, a load current density within the RC-IGBT in an overload situation could increase by a corresponding factor, such as ten, twenty and so on.

Especially with the second RC-IGBT 52 can be a thyristor 54 to the second diode 522 be connected in parallel in order to increase the current carrying capacity. In other words, the thyristor represents 54 another current path outside the RC-IGBT 52 When it is detected that the load current is in the reverse direction, ie that from the second diode 522 guided load current, exceeds a certain value, the thyristor 54 be switched on, so a significant part of the overload current through the thyristor 54 to be led.

Therefore, the power converter can 5 withstand an overload current. However, such an additional thyristor could 54 , which is another power semiconductor device to be controlled, the complexity of the power converter 5 increase. For example, it may be desirable to provide means that enable the implementation of a less complex power converter, for example the implementation of a less complex power converter that is suitable for at least temporarily withstanding an overload current.

1 FIG. 11 schematically illustrates a portion of a vertical cross section of a semiconductor device 1 according to one or more embodiments. The semiconductor device 1 includes a semiconductor region 11 , which has charge carriers of a first conductivity type. For example, the semiconductor area 11 mainly a weakly n-doped area (n-area). For example, the semiconductor region 11 a drift region of the semiconductor device 1 include.

The semiconductor device 1 comprises a transistor cell 1-1 , being a semiconductor channel region 111 in the transistor cell 1-1 is included.

The semiconductor channel region 111 has a first doping concentration of charge carriers of a second conductivity type which is complementary to the first conductivity type. For example, is the semiconductor channel region 111 mainly a normally p-doped semiconductor region (p-region). In one embodiment, the semiconductor channel region 111 a so-called body area of the semiconductor device 1 include or be. For example, the semiconductor channel region 111 be configured to have an inversion layer within the semiconductor region 11 as a function of an electrical control potential to generate the semiconductor channel region 111 is fed.

Accordingly, a transition forms between the semiconductor channel region 111 and the semiconductor field 11 a first pn junction 11-1 . As in 1 displayed, the first pn junction can be 11-1 in the semiconductor field 11 with a certain distance from a surface 11-5 of the semiconductor field 11 extend.

It is also in the semiconductor field 11 a semiconductor auxiliary area 112 contain. The semiconductor auxiliary area 112 is in close proximity to the semiconductor channel area 111 arranged. The semiconductor auxiliary area 112 is different from the semiconductor channel region 111 and has a second doping concentration of charge carriers of the second conductivity type, wherein the second doping concentration is higher than the first doping concentration. For example, this is the semiconductor auxiliary area 112 mainly a highly doped p region (p ^{+ region} ).

Accordingly, forms a transition between the semiconductor auxiliary area 112 and the semiconductor field 11 a second pn junction 11-2 . The second pn junction 11-2 is the same or deeper in the semiconductor area 11 like / as the first pn junction 11-1 arranged. For example, is the distance between the surface 11-5 and the second pn junction 11-2 greater than the distance between the first pn junction 11-1 and the surface 11-5 .

For example, is the second pn junction 11-2 arranged at a depth which is a few nm, such as about 50 nm, 100 nm or 500 nm or other values in the range between 50 nm and 1 μm, deeper than the depth of the first pn junction 11-1 is.

Further is the semiconductor auxiliary area 112 closest to the semiconductor channel area 111 compared to any other semiconductor region of the semiconductor device 1 , which comprises charge carriers of the second conductivity type and which has a further pn junction to the semiconductor region 11 forms. Such further semiconductor areas are within 1 not displayed; For example, such semiconductor regions comprise a p ⁺ collector layer. For example, the semiconductor auxiliary area 112 be a p ^{+ region} closest to the semiconductor channel region 111 compared to any other p-type region of the semiconductor device 1 , regardless of whether this further p-region is a highly doped p-region or a weakly doped p-region or a normally doped p-region.

For example, the second doping concentration is at least twice as high as the first doping concentration, such as about ten times as high, or even higher than ten times as high as the first doping concentration. The second doping concentration can be at least one order of magnitude (1E3) higher than the first concentration.

For example, the semiconductor device is 1 an RC-IGBT. According to another example, the semiconductor device is 1 an MCD.

In one embodiment, the semiconductor device is 1 operable in both a forward current mode and a reverse current mode, e.g., when the semiconductor device 1 is an RC-IGBT. In another embodiment, the semiconductor device is 1 operable only in a reverse current mode, e.g., when the semiconductor device 1 is an MCD.

In the forward current mode, a load current from the semiconductor area 11 in a forward direction (shown in 1 with the reference symbol FC). For example, is the semiconductor channel region 111 configured to direct at least a portion of the rated load current in the forward direction. In the reverse current mode, a load current is from the semiconductor area 11 led in the opposite direction.

For example, the semiconductor device is 1 , for example an RC-IGBT, designed to be operated at an operating frequency of several hundred Hz. At a rate corresponding to such an operating frequency, the rated load current between a diode cell (in 1 not shown) of the semiconductor device 1 which is a reverse direction and a transistor cell of another semiconductor device (in 1 not shown), which is a forward direction, commutate. For this purpose, the charge carrier density within the semiconductor region 11 preferably kept below a certain level in order to enable commutation robustness of the diode cell during nominal conditions.

As mentioned at the outset, the semiconductor device 1 are suitable for use within a section of a power converter. Such a section may be required to withstand an overload current that can be a multiple of a rated load current for which the semiconductor device is capable 1 is designed under nominal conditions. For example, the overload current can be ten times or even higher, such as about 20 times, as high as the rated load current. For this purpose, the semiconductor auxiliary area 112 can be used in an overload situation to reduce the charge carrier density within the semiconductor region 11 temporarily to increase it to the semiconductor area 11 to enable the overload current to be passed in the reverse direction. In 1 such an overload current in the reverse direction is indicated with the reference symbol ROLC. The semiconductor auxiliary area 112 may be configured to conduct at least a portion, preferably at least a significant portion, of such overload current in the reverse direction. In other words, the reverse overload current can make the second pn junction 11-2 cross. Furthermore, the semiconductor auxiliary area 112 with a load connection, such as an anode connection or an emitter connection (in 1 not shown) of the semiconductor device 1 be electrically connected by means of a low-resistance current path in order to enable receiving, conducting and outputting of at least part of the reverse overload current. Therefore, the semiconductor auxiliary area 112 according to one embodiment, be configured not only to serve as an additional charge carrier source, but also as a reverse overload current-carrying element of the semiconductor device 1 .

When carrying the forward load current, the forward load current may, for example, be a first load current path within the semiconductor device 1 follow, such a first load current path being the first pn junction 11-1 crosses, for example in a direction that is essentially perpendicular to a transition region of the first pn junction 11-1 is. When carrying the reverse overload current, the reverse overload current can follow a second load current path, which is the second pn junction 11-2 crosses, for example in a direction which is essentially perpendicular to a transition region of the second pn-junction 11-2 is. Furthermore, the first load current path can be the semiconductor channel region 111 cross and / or the second load current path can cross the semiconductor auxiliary area 112 cross.

In one embodiment, the semiconductor device may 1 have an edge termination structure which is an active area of the semiconductor device 1 surrounds, both the Edge termination structure as well as the active area part of the semiconductor area 11 could be. The semiconductor device 1 may be configured to carry the load current mainly by means of the active area during rated operation, and the semiconductor device 1 can also be configured to carry the load current by means of both the active area and the edge termination structure during the overload condition. Furthermore, the load current density can be distributed essentially uniformly between the edge termination structure and the active region during the overload state, at least more uniformly than in nominal operation.

For example, the reverse overload current (ROLC) can be detected by an application such as a gate driver, which is described in more detail below. In the case of a ROLC, the diode cell (in 1 not shown) of the semiconductor device 1 eg not necessarily blocking against a voltage; typically there is no so-called reverse recovery process in a ROLC case. Rather, the current zero crossing can be defined by the AC power grid. As a result, commutation robustness may no longer be a requirement during a ROLC case.

Referring only to ROLC cases, the semiconductor device must 1 therefore do not necessarily have commutation robustness. Therefore, the provision of the semiconductor device 1 that are advantageous between a nominal state that meets the regular commutation robustness and an overload state that sacrifices the commutation robustness in favor of significantly reduced ROLC line losses, ie higher ROLC robustness.

The above-mentioned exemplary functional aspect relating to the overload current capacity of the in 1 illustrated semiconductor device 1 will be explained in more detail with reference to the remaining drawings. Before going into detail regarding the functional aspect, however, further examples of structures of semiconductor devices that are also suitable for fulfilling the functional aspect will be described with reference to FIG 2 to 5 explained.

2 schematically illustrates a portion of a vertical cross section of a semiconductor device 1 , for example an RC-IGBT, according to one or more further embodiments. The semiconductor device 1 comprises a transistor cell 1-1 that have a structure similar to that in 1 illustrated transistor 1-1 having. The semiconductor device further includes 1 an adjacent diode cell 1-2 .

The diode cell 1-2 can be configured to carry a nominal load current in the reverse direction RC, for example by means of a semiconductor anode region 113 . The semiconductor anode region 113 has a third doping concentration of charge carriers of the second conductivity type. For example, the third doping concentration is lower than the second doping concentration of charge carriers in the semiconductor auxiliary region 112 . The semiconductor anode region 112 can mainly be a normally p-doped region (p-region). Accordingly, a transition forms between the semiconductor anode region 113 and the semiconductor field 11 a third pn junction 11-3 .

For example, the diode cell 1-2 configured not to carry a load current in the forward direction. The diode cell 1-2 can be configured to ensure that there is no inversion layer within a path, such as an ohmic path or a unipolar path, between the semiconductor region 11 and the semiconductor source regions 114 and / or the gate electrodes 121 arises.

The second pn junction 11-2 between the semiconductor auxiliary area 112 and the semiconductor field 11 is as deep or deeper than / than the third pn junction 11-3 arranged. For example, is the distance between the third pn junction 11-3 and the surface 11-5 smaller than the distance between the second pn junction 11-2 and the surface 11-5 . For example, is the second pn junction 11-2 arranged at a depth which is a few nm, such as about 50 nm, 100 nm or 500 nm, other values in the range between 50 nm and 1 μm, deeper than the depth of the third pn-junction 11-3 is.

The semiconductor device 1 can do a variety of first trenches 13th include, at least two of these first trenches 13th in the diode cell 11-2 may be included. Each first trench extends vertically into the semiconductor region 11 and includes a first electrode 131 , which may be a source electrode or a gate electrode, and a first dielectric 132 , with each first dielectric 132 the first electrode 131 of the respective first trench 13th from the semiconductor body 11 isolated. As in 2 displayed, the semiconductor anode region 113 between two first trenches 13th may be arranged and in contact with the first dielectrics 132 of the first two trenches 13th be.

The semiconductor device 1 can also have a plurality of second trenches 12th comprise, at least two of these second trenches 12th in the transistor cell 1-1 may be included. Every second ditch 12th extends vertically into the semiconductor region 11 and can be a gate electrode 121 and a second dielectric 122 include. Every other dielectric 122 isolates the gate electrode 121 of respective second trench 12th from the semiconductor field 11 .

The transistor cell 1-1 can furthermore semiconductor source regions 114 that are in contact with the semiconductor channel regions 111 are. For example, the semiconductor source regions include 114 Charge carriers of the first conductivity type, with a charge carrier density of the semiconductor source regions 114 higher than the charge carrier density of the semiconductor region 11 can be. The semiconductor source regions are for example 114 n ⁺ regions and the semiconductor region 11 is mainly an n ^{- region} . As in 2 illustrated, the semiconductor auxiliary area 112 in contact with the adjacent semiconductor channel regions 111 his and between two second trenches 12th be arranged.

In one embodiment, the semiconductor device is 1 configured to conduct the load current in the forward direction (FC) when a voltage is applied between a collector terminal and a cathode terminal (not shown) of the semiconductor device, respectively 1 and an emitter terminal and an anode terminal (not shown) of the semiconductor device, respectively 1 is greater than 0 V (V _CE > 0 V). In other words, the semiconductor device can 1 configured to block reverse load current when the voltage is greater than 0V.

Furthermore, the semiconductor device 1 be configured to conduct the load current in the reverse direction (RC) when a voltage is applied between a collector terminal and a cathode terminal (not shown) of the semiconductor device, respectively 1 and an emitter terminal and an anode terminal (not shown) of the semiconductor device, respectively 1 is less than 0 V (V _CE <0 V).

The emitter connection (not shown) can be connected to the semiconductor source regions 114 be electrically connected and the anode terminal (not shown) can be connected to the semiconductor anode regions 113 be electrically connected. The collector terminal (not shown) may be electrically connected to a semiconductor collector region (not shown) that is in contact with the semiconductor region 11 can be and below the semiconductor region 11 can be arranged, and the cathode connection (not shown) can be electrically connected to a semiconductor cathode region, the at least parts of the semiconductor region 11 may include.

3 Fig. 10 illustrates a portion of a vertical cross section of a semiconductor device 1 according to one or more further embodiments. Accordingly, the semiconductor device 1 a variety of transistor cells 1-1 include and the semiconductor auxiliary area 112 can outside of the transistor cells 1-1 be arranged. For example, each semiconductor auxiliary area is 112 from each semiconductor channel region 111 by means of at least one of the second trenches 12th Cut. In other words, a second trench 12th between a respective semiconductor auxiliary area 112 and a respective semiconductor channel region 111 be arranged. The respective semiconductor auxiliary area 112 can with both the first dielectric 132 one of the first trenches 13th as well as the second dielectric 122 of the second trench 12th be in contact with that of the semiconductor auxiliary area 112 from the semiconductor channel area 111 separates.

The combination of the semiconductor auxiliary area 112 , the adjacent first ditch 13th and the adjacent second trench 12th can be an auxiliary cell 1-3 represent. As in 3 displayed, the semiconductor device 1 a multitude of such auxiliary cells 1-3 and a plurality of transistor cells 1-1 as well as a variety of diode cells 1-2 include. For example, each transistor cell is 1-1 of two adjacent auxiliary cells 1-3 adjacent. Every diode cell can 1-2 of two auxiliary cells 1-3 be adjacent, as in 3 displayed.

In relation to 3 it is understood that according to one or more embodiments, the transistor cells 1-1 who have favourited diode cells 1-2 and the auxiliary cells 1-3 can be implemented on a common chip, for example to form a monolithically integrated RC-IGBT. Alternatively, the diode cells 1-2 and the auxiliary cells 1-3 be implemented on a separate chip, e.g. to form an MCD.

According to one embodiment, for example, if the semiconductor device 1 from 3 is an RC-IGBT, a respective diode cell 1-2 at a greater distance from a respective transistor cell 1-1 arranged as the auxiliary cells 1-3 . In other words, a distance between a respective auxiliary cell 1-3 and a respective transistor cell 1-1 be less than a distance between a respective diode cell 1-2 and the transistor cell 1-1 . Or it can be a cell that is closest to a respective transistor cell 1-1 is arranged, either another transistor cell 1-1 or an auxiliary cell 1-3 but not a diode cell according to one example 1-2 . The placement of the diode cell 1-2 at a greater distance from the transistor cell 1-1 compared to a distance between the auxiliary cell 1-3 and the transistor cell 1-1 can be used for the injection of charge carriers into the semiconductor area 11 during rated operation (no overload current) of the semiconductor device 1 be supportive.

In one embodiment, the density of the auxiliary cells 1-3 in relation to the total available area of the semiconductor region 11 over the entire chip of the semiconductor device 1 be essentially constant. For example, the Density of the auxiliary cells contained in the active area 1-3 essentially equal to the density of the auxiliary cells 1-3 contained in the edge termination structure surrounding the active area. With continued reference to the total available area of the semiconductor region 11 can also increase the density of the transistor cells 1-1 and the density of the diode cells 1-2 contained in the edge termination structure are each lower than the density of the transistor cells 1-1 or the density of the diode cells 1-2 included in the active area.

In a further embodiment, with reference to the total available area of the semiconductor region 11 more auxiliary cells 1-3 within the edge termination structure of the semiconductor device 1 be arranged as the number of auxiliary cells 1-3 that are within the active area of the semiconductor device 1 are arranged. In other words, the density of the auxiliary cells 1-3 be higher within the edge termination structure than the density of the auxiliary cells 1-3 within the active area.

As stated above, the semiconductor device 1 be configured to carry the load current mainly by means of the active area during the rated operation, and the semiconductor device 1 may further be configured to carry the load current by means of both the active area and the edge termination structure during the overload condition. For this purpose, the transistor cells 1-1 and the diode cells 1-2 mainly within the active area of the semiconductor device 1 be arranged and the auxiliary cells 1-3 can mainly be within the edge termination structure of the semiconductor device 1 be arranged. Therefore, the density of the transistor cells 1-1 and the diode cells 1-2 within the active area of the semiconductor device 1 be comparatively high in order to make it possible to carry the load current in the forward direction and the reverse direction mainly by means of the active area during nominal operation. Furthermore, the density of the auxiliary cells 1-3 within the edge termination structure of the semiconductor device 1 be comparatively high to enable the overload current to be conducted in the reverse direction by means of both the active area and the edge termination structure during the overload condition of the reverse current mode.

According to the above, the ratio between the volume of the semiconductor auxiliary region (s) 112 and the semiconductor anode region (s) 113 in a direction from a center of the active region to the edge termination structure of the semiconductor device 1 climb. In addition, the ratio between the volume of the semiconductor auxiliary area (s) 112 and the semiconductor channel region (s) 111 in a direction from the center of the active area to the edge termination structure of the semiconductor device 1 climb.

According to a further embodiment, of which a portion of a vertical cross section in a perspective view in FIG 4th illustrated, the semiconductor device 1 have a stripe cell configuration. In this embodiment there are no separate auxiliary cells 1-2 provided; rather, the semiconductor auxiliary areas are 112 each in a respective transistor cell 1-1 contain. The semiconductor auxiliary areas 112 each extend deeper into the semiconductor region 11 than the adjacent semiconductor channel regions 111 . The second pn junctions are accordingly 11-2 created by transitions between the semiconductor auxiliary areas 112 and the semiconductor field 11 be formed at a greater distance from the surface 11-5 arranged as the first pn junctions 11-1 .

According to yet another embodiment, of which a portion of a vertical cross section is shown in a perspective view in FIG 5 is illustrated, the semiconductor auxiliary areas 112 in a horizontal direction in areas of both a diode cell 1-2 as well as a transistor cell 1-1 of the semiconductor device. In this embodiment, the semiconductor auxiliary areas are 112 essentially deeper in the semiconductor field 11 arranged as the semiconductor channel regions 111 , for example such that the semiconductor auxiliary areas 112 on the one hand and the semiconductor channel regions 111 on the other side of each other by parts of the semiconductor region 11 are separated from each other. In one embodiment, the semiconductor auxiliary regions 112 and the semiconductor channel regions 111 form a pnp-FET (pnp field effect transistor).

With continued reference to 5 can the semiconductor auxiliary areas 112 in contact with the respective adjacent second trenches 12th be. Furthermore, the semiconductor auxiliary areas 112 in contact with the respective adjacent first trenches 13th be. For example, the semiconductor auxiliary areas extend 112 about as deep into the semiconductor area 11 like the first trenches 13th and the second trenches 12th and are not in contact with the semiconductor channel areas 111 . It should be noted that the in 5 illustrated structure with the in 4th or 3 illustrated structure can be combined.

With further reference to 5 it is understood that according to one or more embodiments, the transistor cells 1-1 and the diode cells 1-2 and the semiconductor auxiliary areas 112 can be implemented on a common chip, for example to form a monolithically integrated RC-IGBT. Alternatively, the diode cells 1-2 and the semiconductor auxiliary areas 112 on be implemented on a separate chip, e.g. to form an MCD.

Functional aspects of the 1 to 5 illustrated semiconductor devices 1 explained in more detail. For this purpose it is additionally based on 6th Reference is made to a circuit diagram of a circuit arrangement 3 schematically illustrated on 7th 14, which schematically illustrates a flowchart of a method of operating a semiconductor device, and FIG 8th 14, which schematically and by way of example illustrates a diagram indicating an amount of charge Q held in the semiconductor device 1 and is in reverse current mode depending on a voltage of your gate signal.

For example, if the semiconductor device to be operated is an RC-IGBT, the voltage V can be the difference between the electrical potential of a gate terminal connected to the gate electrodes 121 is electrically connected, and the electrical potential of an emitter connection which is connected to the semiconductor source regions 114 electrical connected. Such a voltage V can be what is commonly referred to as “V _GE ” in the context of RC-IGBTs. If the semiconductor device to be operated is an MCD, the voltage V can be the difference between the electrical potential of a gate terminal connected to the gate electrodes 121 is electrically connected, and the electrical potential of an anode terminal connected to the semiconductor anode regions 113 and the semiconductor auxiliary fields 112 can be electrically connected.

In short, the in 6th illustrated circuit arrangement 3 a semiconductor device 1 , e.g. an RC-IGBT or an MCD that has a structure similar to or identical to that in one or more of 1 to 5 may have illustrated structures. The circuit arrangement also includes 3 a gate driver 2 who is with the semiconductor device 1 is operatively coupled and the one gate signal generator 21 for generating a gate signal 2-1 and an overload current detector 22nd for receiving a measurement signal 2-2 which is based on an existing one of the semiconductor device 1 guided load current in the reverse direction. For example, to implement the in 7th illustrated procedure 4th the gate driver 2 can be used, which is described in more detail below.

The following explanation mainly relates to embodiments in which the in 6th illustrated semiconductor device 1 implemented as an RC-IGBT. It goes without saying, however, that the same operating principles apply analogously to the semiconductor device 1 in the form of an MCD can be applied when the semiconductor device 1 is only operated in reverse flow mode. For this purpose, the semiconductor device must 1 from 6th not necessarily a transistor section 1-A but may comprise essentially only one gate-controlled diode section in accordance with one or more embodiments 1-B include, for example, by one or more of the diode cells 1-2 and one or more of the auxiliary cells 1-3 can be formed.

For operating the semiconductor device 1 can the gate signal 2-1 the gate electrodes 121 are provided, for example by means of the gate signal generator 21 . For example, when the semiconductor device 1 is operated in the nominal state of reverse current mode (no overload current), the gate signal 2-1 with a voltage V mainly within an in 8th indicated nominal voltage range R ₁ is provided, wherein this nominal voltage range R ₁ comprises values which are equal to or greater than the critical voltage V _crit . The nominal voltage range R ₁ may include a threshold voltage V _th. For example, a voltage V higher than the threshold voltage V _th can be an inversion channel in the semiconductor region 11 produce. Even though 8th indicates that the critical voltage V _{crit can be} less than 0 V and that the threshold voltage V _{th can be} greater than 0 V, it should be pointed out that the values of the voltages can be modified by means of various semiconductor structures. It should also be noted that V _th can be almost identical to V _crit in certain configurations.

When the semiconductor device 1 Eg if an RC-IGBT is, the gate signal generator can 21 the gate signal under nominal conditions 2-1 with at least two alternating values, the values being within the nominal voltage range R ₁ , for example at an operating frequency of several hundred Hz. The semiconductor device 1 turns on and off at the operating frequency. When turned on, the reverse semiconductor device can 1 (as in 1 to 6th exemplified) lead a forward load current FC, for example by means of the transistor cells 1-1 such as by means of the semiconductor channel regions 111 and the semiconductor source regions 114 .

For example, when coupled to an external load circuit, such as an AC power grid, the semiconductor device 1 a reverse load current RC must lead, for example by means of the diode cells 1-2 such as by means of the semiconductor anode regions 113 , can occur.

Furthermore, the gate electrodes 121 be configured in forward current mode to the semiconductor device 1 based on the received Gate signal 2-1 off to block the flow of a load current in the forward direction (FC).

During such rated operation at the operating frequency, the semiconductor device may be required 1 Has commutation robustness. For example, the semiconductor device must 1 make sure more with the semiconductor device 1 coupled devices can withstand changes in the direction of the load current at a rate appropriate to the frequency of operation, e.g., changes from a reverse load current to a forward load current. For this purpose it may be necessary that the total amount of in the semiconductor area 11 contained charge Q a critical amount Q _crit , as in 8th displayed, does not exceed when the semiconductor device 1 is in reverse flow mode. In other words, the density of charge carriers must be within the semiconductor region 11 sometimes kept below a certain level to ensure commutation robustness during nominal operation.

As the amount of in the semiconductor field 11 contained charge Q from the voltage V of the gate signal 2-1 may depend, it may be required that during rated operation of the semiconductor device 1 , which is in the nominal state of reverse current mode (no overload current), the voltage of the gate signal 2-1 remains predominantly within the nominal voltage range R _1. For example, during nominal operation in the reverse current mode, only the semiconductor anode region is turned on 113 for injecting charge carriers into the semiconductor area 11 used. That means: by means of the semiconductor anode area 113 becomes a first charge carrier density within the semiconductor region 11 caused to it the semiconductor field 11 to enable a nominal load current to be carried in the reverse direction. However, the semiconductor auxiliary area will 112 during rated operation in the reverse current mode of the semiconductor device 1 preferably not used, eg neither for charge carrier injection nor as a load current-carrying element. For example, the load current crosses the semiconductor auxiliary area during nominal operation 112 Not. For example, it can be ensured that the semiconductor auxiliary area 112 essentially no charge carriers in the semiconductor region during nominal operation at the operating frequency 11 injected. For example, the semiconductor auxiliary area 112 be configured to avoid charge carriers in the semiconductor auxiliary area 11 to inject when the gate signal 2-1 is provided with a voltage V within the nominal voltage range R ₁ .

However, if it is detected that the reverse load current RC is substantially larger than the rated load current for which the semiconductor device 1 is designed in the nominal state, the gate signal 2-1 with a voltage V within an in 8th indicated overload voltage range R2 be provided, for example by means of the gate signal generator 21 . For example, they are all in the overload voltage range R2 contained voltage values smaller than any voltage value contained _{in the nominal voltage range R 1.}

By the gate signal 2-1 with a voltage V within the in 8th overload voltage range shown as an example R2 is provided, the semiconductor device 1 when in reverse current mode, placed in an overload condition, during which the total amount of charge carriers within the semiconductor region 11 is increased significantly, for example by means of the semiconductor auxiliary area 112 . In other words, the semiconductor auxiliary area 112 with the gate electrodes 121 be electrically coupled, for example capacitively coupled, in such a way that the semiconductor auxiliary region 112 Charge carriers in the semiconductor area 11 injected when the gate signal 2-1 is provided with a voltage within the overload voltage range R ₂ . In this case, both inject the semiconductor anode region 113 as well as the semiconductor auxiliary field 112 such charge carriers in the semiconductor region 11 that a second charge carrier density within the semiconductor region 11 is caused, wherein the second charge carrier density is significantly higher than the first charge carrier density, which during nominal operation of the semiconductor device 1 is available. Due to the increased carrier density, the semiconductor device is 1 configured to carry a reverse overload current ROLC. Furthermore, the semiconductor auxiliary area 112 in the overload state as a load current-carrying element of the semiconductor device 1 serve, that is, at least part of the reverse overload current can use the second pn junction 11-2 cross and can cross the semiconductor auxiliary area 112 traverse. For this purpose, the semiconductor auxiliary area 112 with a load contact of the semiconductor device 1 be electrically connected by means of an ohmic current path to make it possible to receive and output the part of the reverse overload current.

For example, the semiconductor device 1 operated in the overload condition by the gate signal 2-1 is provided with a voltage V within the overload voltage range R ₂ for at least a minimum duration. For example, the minimum duration has a length of at least 100 microseconds, such as 1 ms, 10 ms or 100 ms or other values within the range from 100 microseconds to 100 ms. In other words, the overload condition can last at least as long as the minimum duration. Furthermore, the length of the minimum duration can be a multiple of the reciprocal value of the operating frequency of the semiconductor device 1 can be operated in the nominal state.

When the minimum duration is over, that is, when the ROLC situation is over, the semiconductor device can 1 can also be operated in the forward current mode and again in the nominal state of the reverse current mode.

In one embodiment, the semiconductor device may 1 can be used within a power converter that is coupled to an AC power grid, e.g., within a power converter that has an MMC topology that is used for an HVDC application. The frequency of the voltage of the AC power grid can be 50 Hz, 60 Hz or similar values, for example. If a grid fault occurs, a current limiter or other protective device typically integrated within the AC power grid can respond to such a fault. For example, such a current limiter can react within a duration that corresponds to a sine half-wave or a multiple thereof, e.g. within a duration of 10 ms in the case of a 50 Hz AC power grid or within a duration of 8.33 ms in the case of a 60 Hz AC power grid. For example, the minimum duration lasts at least as long as the duration of such a sine half-wave of the AC power network with which the power converter including the semiconductor device 1 can be coupled. For example, the minimum duration is longer than 10 ms, 20 ms or longer than 30 ms.

During the overload condition, the gate signal generator 21 make sure the voltage V of the gate signal 2-1 remains within the overload voltage range R _2. For example, it is not ensured during the overload state that the semiconductor device 1 Has commutation robustness. Rather, the semiconductor device 1 no commutation robustness when it is in the overload state.

For example, the nominal voltage range R ₁ comprises voltage values between +15 V and -15 V and the overload _{voltage range R 2} comprises voltage values between -15 V and -40 V. It goes without saying that these exemplary ranges are due to corresponding variations in the structure, doping concentrations, doping materials and / or semiconductor materials in the semiconductor device 1 can be modified. However, the overload _{voltage range R 2} typically does not include any voltage values that are part of the nominal voltage range R ₁ .

According to the foregoing, the semiconductor auxiliary area 112 and the semiconductor anode region 113 can be viewed as a controllable charge carrier injector configured to inject charge carriers into the semiconductor region 11 to inject and which is responsive to a control signal, this control signal by means of the generated gate signal 2-1 can be generated, for example by the gate signal generator 21 of the gate driver 2 as stated above. In other words, an effective efficiency of the anode of the area consisting of the semiconductor auxiliary area (s) 112 and the semiconductor anode area (s) 113 by means of the gate signal 2-1 be controllable. Furthermore, the area comprising the semiconductor auxiliary area (s) 112 and the semiconductor anode region (s) 113 operated as the controllable charge carrier injector when the first electrodes 131 and the gate electrodes 121 have approximately the same electrical potential, for example when the first electrodes 131 and the gate electrodes 121 are both at gate potential, the gate potential being the electrical potential of a gate terminal of the semiconductor device 1 can be (cf. gate connection explained below 33 ). It is also understood that, according to one or more embodiments, both the semiconductor anode region 113 as well as the semiconductor auxiliary field 112 may be configured not only to serve as a charge carrier source, but also to serve as a respective reverse load current carrying element of the semiconductor device 1 to serve.

In order to control such a charge carrier injector, the semiconductor auxiliary area 112 with the gate electrodes 121 be capacitively coupled. The gate signal 2-1 can the gate electrodes 121 be provided. By providing the gate signal 2-1 with a voltage within the overload voltage range R ₂ can also be within the semiconductor region 11 contained charge carrier density can be increased significantly, for example by a factor of 1E2 compared to the first charge carrier density. It should be noted that the increase in the charge carriers can also depend on the amplitude of the reverse overload current. Due to the increased charge carrier density, the semiconductor device has 1 possibly no longer commutation robustness; the semiconductor device 1 however, it may then be able to carry the reverse overload current ROLC without suffering damage.

With regard to the embodiments according to 2 some of the reverse load current can also flow through the transistor cell 1-1 be guided when the semiconductor device 1 is in the nominal state of reverse current mode, when about the semiconductor auxiliary area 112 attached to the semiconductor channel regions 111 adjoins, is not used and, for example, no charge carriers in the semiconductor area 11 injected. The additional diode cell 1-2 is at a greater distance from the transistor cell 1-1 arranged so that they allow sufficient injection of charge carriers, such as holes, into the Semiconductor area 11 during rated operation of the semiconductor device 1 can ensure.

Now, taking a closer look at the in 6th schematically illustrated circuit arrangement 3 is the gate driver 2 with the semiconductor device to be controlled 1 , e.g. an RC-IGBT, operatively coupled. In 6th is the semiconductor device to be controlled 1 illustrated by means of a circuit symbol. In a simplified manner, the semiconductor device comprises 1 a transistor section 1-A , hereinafter referred to as transistor 1-A and a diode section 1-B , hereinafter referred to as the freewheeling diode 1-B that is referred to the transistor 1-A is connected anti-parallel. Both the transistor 1-A as well as the freewheeling diode 1-B can be implemented on a common chip. Alternatively, the transistor 1-A and the freewheeling diode 1-B , as illustrated above, can be implemented on chips that are separated from one another and thereby form, for example, an IGBT and an MCD that is separate therefrom.

The transistor 1-A can be one or more of the transistor cells 1-1 for carrying a forward load current comprise and the freewheeling diode 1-B can be one or more of the diode cells 1-2 for carrying reverse load current as discussed above. Still starting from a simplified way, one can use the anode of the freewheeling diode 1-B be assumed to be both the semiconductor anode region 113 as well as the semiconductor auxiliary field 112 which is preferably used only during the overload condition. The cathode of the freewheeling diode 1-B can at least partially from the semiconductor field 11 consist.

The gate driver 2 that with the semiconductor device to be controlled 1 is operatively coupled, comprises the gate signal generator 21 and the overload current detector 22nd . The overload current detector 22nd is with the gate signal generator 21 operatively coupled to the gate signal generator 21 indicate that the existing load current in the reverse direction exceeds a threshold value. To the semiconductor device 1 can be controlled by the gate signal generator 21 with the gate electrodes 121 by means of a gate connection 33 be electrically coupled.

With regard to a technical current direction, the forward load current (FC) can also be used by means of a collector connection 32 into the semiconductor device 1 and from the semiconductor device 1 by means of an emitter connection 31 be decoupled. Accordingly, still in terms of an engineering current direction, reverse current (RC or ROLC) becomes in the semiconductor device 1 by means of the emitter connection 31 fed and from the semiconductor device 1 by means of the collector connection 32 decoupled. As explained above, the semiconductor device 1 be configured to conduct the load current in the forward direction (FC) when there is a voltage across the collector terminal 32 and the emitter terminal 31 of the semiconductor device 1 is greater than 0 V (V _CE > 0 V). Furthermore, the semiconductor device 1 be configured to conduct the load current in the reverse direction (RC) when there is a voltage across the collector terminal 32 and the emitter terminal 31 is less than 0 V (V _CE <0 V). The emitter connection 31 can with the semiconductor source regions 114 be electrically connected. The collector connection 32 may be electrically connected to a semiconductor collector region which, as explained above, is in contact with the semiconductor region 11 can be and below the semiconductor region 11 can be arranged.

It is understood that if the semiconductor device 1 is an MCD, the collector connection 32 rather, it would be referred to as the "cathode connection" and the emitter connection 31 rather, it would be referred to as “anode connection”, as already explained above. Still, the connections 31 and 32 hereinafter referred to simply as “collector connection 31” and “emitter connection 32”.

In order to detect an overload current, the overload current detector receives 22nd the measurement signal 2-2 . This measurement signal 2-2 can, for example, by means of a shunt connected to the semiconductor device 1 connected downstream or upstream. As an alternative or in addition to this, the measurement signal 2-2 be provided by a Rogowski coil and / or by any other means for generating the measurement signal 2-2 are suitable so that the measurement signal 2-2 on the amplitude of the existing of the semiconductor device 1 guided load current. This means for generating the measurement signal 2-2 can be part of the overload current detector 22nd be.

Regarding the in 7th schematically illustrated method 4th it should be noted that this procedure 4th may be a semiconductor device 1 according to the in 1 to 6th to operate schematically and exemplarily illustrated embodiments. For the sake of simplicity, it will be referred to these exemplary embodiments in the following.

Accordingly, the semiconductor device to be operated 1 (in 7th not shown) may be operable in at least one of a forward current mode and a reverse current mode and may be a semiconductor region 11 and a controllable charge carrier injector, wherein the controllable charge carrier injector is configured to inject charge carriers into the semiconductor region 11 to inject. As stated above, the semiconductor device 1 when the semiconductor device 1 an RC-IGBT is capable of operating in both the forward current mode and the reverse current mode. Alternatively, the semiconductor device 1 when the semiconductor device 1 an MCD is, for example, only operated in reverse flow mode.

The semiconductor device 1 can also have a gate electrode 121 include, wherein the gate electrode 121 is electrically coupled to the controllable charge carrier injector for receiving a gate signal 2-1 is configured. In a first step 41 becomes in the reverse current mode of the semiconductor device 1 detects whether one of the semiconductor area 11 guided load current in the reverse direction exceeds a threshold value or not. When the existing load current in the reverse direction does not exceed the threshold value, the semiconductor device becomes 1 operated in a nominal state (see step 42 ) by the gate signal 2-1 is provided with a voltage within a nominal voltage range R ₁ , so that the gate electrode causes the charge carrier injector to have a first charge carrier density within the semiconductor region 11 caused to it the semiconductor field 11 to enable a nominal load current to be carried in the reverse direction. When the load current in the reverse direction exceeds the threshold value, the semiconductor device becomes 1 operated in an overload condition (see step 43 ) by providing the gate signal with a voltage within an overload voltage range R ₂ , so that the gate electrode causes the charge carrier injector to cause a second charge carrier density within the semiconductor region in order to bring it to the semiconductor region 11 to enable an overload current to be conducted in the reverse direction, the second charge carrier density being higher than the first charge carrier density.

For example, the forward load current, when operated in the forward current mode, may be the first load current path within the semiconductor device 1 follow, such a first load current path being the first pn junction 11-1 crosses, for example in a direction that is essentially perpendicular to a transition region of the first pn junction 11-1 runs. Furthermore, the first load current path can be the semiconductor channel region 111 cross, ie, the semiconductor channel region 111 may be configured to act as a forward load current carrying element of the semiconductor device 1 to serve. For this purpose, the semiconductor channel region 111 with an emitter terminal of the semiconductor device 1 such as connecting 31 , as in 6th illustrated to be electrically connected.

When the semiconductor device 1 is operated in the overload state of the reverse current mode, the reverse overload current can follow the second load current path, which is the second pn junction 11-2 crosses, for example in a direction which is essentially perpendicular to a transition region of the second pn-junction 11-2 runs. Furthermore, the second load current path can be the semiconductor auxiliary region 112 cross, ie the semiconductor auxiliary area 112 may be configured to act as a reverse overload current carrying element of the semiconductor device 1 to serve. For this purpose, the semiconductor auxiliary area 112 with an anode terminal of the semiconductor device 1 such as connecting 31 , as in 6th illustrated to be electrically connected.

When the semiconductor device 1 is operated in the nominal state of the reverse current mode, the nominal reverse load current can follow a third load current path, which is the third pn junction 11-3 crosses, for example in a direction that is essentially perpendicular to a transition region of the third pn junction 11-3 runs. Furthermore, the third load current path can be the semiconductor anode region 113 cross, ie, the semiconductor anode 113 may be configured to act as a reverse load current carrying element of the semiconductor device 1 to serve. The semiconductor anode region can be used for this purpose 113 to the anode terminal of the semiconductor device 1 such as connecting 31 , as in 6th illustrated to be electrically connected.

For example, the gate driver 2 according to the procedure 4th operate; in other words, can be used to implement the method 4th a gate driver 2 be used.

The following is based on 10 showing a circuit diagram of another circuit arrangement 3 illustrated schematically and by way of example according to one or more embodiments, and on 9A to 9D Reference is made to the method of operating the circuit arrangement 3 from 10 illustrate schematically and by way of example according to one or more embodiments.

In the 10 illustrated circuit arrangement 3 has a structure similar to that in 11 illustrated power converters 5 which has already been discussed above. The circuit arrangement 3 can also be a power converter or a part thereof and, for example, be used for HVDC use such as for an HVDC application. The circuit arrangement accordingly comprises 3 on one side the AC connections 35-1 and 35-2 for receiving and / or outputting an AC voltage and on the other hand DC connections 36-1 and 36-2 for receiving and / or outputting a DC voltage.

The circuit arrangement 3 also includes a semiconductor device 1 , such as referring to 6th discussed, and one more Semiconductor device 1' . The other semiconductor device 1' may have a structure similar to that of the semiconductor device 1 exhibit. According to the in 10 schematically illustrated embodiment is, for example, the semiconductor device 1 an RC-IGBT and the other semiconductor device 1' another RC-IGBT 1 .

It should be noted that the other RC-IGBT 1' does not necessarily have to include semiconductor auxiliary regions or does not necessarily have to include a controllable charge carrier injector or does not necessarily have to be configured for operation in an overload state.

With further reference to the circuit configuration of the circuit arrangement 3 can the collector connection 32 of the RC-IGBT 1 with the AC connector 35-1 be connected, and the emitter terminal 31 of the RC-IGBT 1 can be used with both the AC connector 35-2 as well as the DC connection 36-2 be connected. Since the RC-IGBT 1 configured to carry the reverse overload current (ROLC), an additional thyristor can be installed between the AC connections 35-1 and 35-2 is coupled and with the freewheeling diode 1-B of the RC-IGBT 1 is connected in parallel, can be omitted. As stated above, a ROLC situation can arise, for example due to a short circuit between the DC connections 36-1 and 36-2 (also referred to as "DC pole-to-pole fault") or the like.

The collector connection 32 of the RC-IGBT 1 is also with an emitter connection 31 ' furthermore RC-IGBT 1' connected. The other RC-IGBT 1' comprises a transistor 1'-A and a freewheeling diode 1'-B, with a collector terminal 32 ' furthermore RC-IGBT 1' with the DC connector 36-1 connected is.

With reference to 9A to 9D exemplary methods for operating the circuit arrangement are now described 3 described in more detail.

In general, the circuit arrangement 3 operated by the gate signal 2-1 the gate connection 33 of the RC-IGBT 1 is provided and by another gate signal 2-1 ' the other RC-IGBT 1' provided. For example, the gate signal 2-1 through the gate driver 2 provided in 6th is illustrated schematically. The further gate signal 2-1 ' can be provided by a similar gate driver. In 10 no gate drivers are illustrated.

Each of the 9A to 9D shows the voltage V of the gate signal 2-1 and 2-1 ' over time t. The respective upper graph shows the course of the voltage of the further gate signal 2-1 ' to that of the gate connection 33 ' furthermore RC-IGBT 1' is provided, and the respective lower graph shows the course of the voltage of the gate signal 2-1 to that of the gate connection 33 of the RC-IGBT 1 provided.

It goes without saying that 9A to 9D map the situation in which the RC-IGBT 1' carries the load current while operating in forward current mode and the RC-IGBT 1 conducts the current while operating in reverse current mode. Of course, the RC-IGBT can 1 can also be operated in forward current mode and the RC-IGBT 1' can also be operated in reverse flow mode. However, the latter situation is not discussed in more detail below.

9A and 9C illustrate exemplary operating methods during normal operation of the circuit arrangement 3 , ie in situations where there is no overload current. During normal operation of the RC-IGBT 1 and 1' these can be operated at a nominal operating frequency that is essentially identical to the reciprocal value of a switching duration T, which is defined by the difference between t ₃ and t ₀ . For example, the nominal operating frequency is a few hundred Hz.

The transistor 1'-B of the further RC-IGBT 1' can be switched off at t = t ₀ by adding the voltage V of the further gate signal 2-1 ' is changed from V ₁ to V ₂ . Both V ₁ and V ₂ can be used in the in 8th indicated nominal voltage range R ₁ may be included, where V _{1 can be} regarded as a switch-on voltage and V ₂ as a switch-off voltage. For example, V _{1 is} 15 V and V ₂ is -15 V. After a short delay of, for example, a few microseconds, the voltage of the gate signal 2-1 that the gate connection 33 of the RC-IGBT 1 is provided, can be changed from V ₂ to V ₁ at t = t ₁ . Alternatively, the voltage of the gate signal 2-1 , as in 9C illustrated, can be changed from V ₂ to V ₁ after a greater delay, for example at t = t _4. Before the transistor 1'-A of the further RC-IGBT 1' is switched on again at t = t ₃ , the voltage of the gate signal 2-1 can be changed from V ₁ to V ₂ at t = t ₂ . The short controlled pulse of the gate signal 2-1 according to 9C can also be referred to as a "desaturation pulse". Such a desaturation pulse can reduce losses. The time difference between t ₃ and t ₂ can be similar to the time difference between t ₀ and t ₁ and can be a few 100 ns or a few microseconds; for example, the time difference between t ₃ and t _{2 can be} within the range from 500 ns to 3 microseconds. This can ensure that the DC connections 36-1 and 36-2 not by means of the transistors switched on at the same time 1-A and 1'-A be short-circuited. When the transistor 1'-A furthermore RC-IGBT 1' is switched on, a load current can flow from the collector connection 32 ' to the emitter connection 31 ' (technical current direction) via the transistor 1'-A flow. So can the other RC-IGBT 1' can be operated in the forward current mode when it is turned on. If it is switched off, the other RC-IGBT 1' conduct a reverse current flowing from the emitter terminal 31 ' to the collector connection 32 ' by means of the freewheeling diode 1'-B flows. In such a situation, the further RC-IGBT 1' operated in a reverse flow mode.

Further aspects of such rated RC-IGBT operating methods, as in 9A and 9C illustrated by way of example can be found in D. Werber, “6.5 kV RCDC For Increased Power Density in IGBT Modules”, Proceedings of the 26th International Symposium on Power Semiconductor Devices &IC's, 15.-19. June, pages 35-38, Waikoloa, Hawaii (2014) , which is hereby incorporated by reference in its entirety. For example, the operating methods disclosed in this publication, such as with respect to FIG 7c this publication explains also on the circuit arrangement 3 , as in 10 illustrated schematically in the present description.

For example, if the one from the RC-IGBT 1 guided reverse current does not exceed the threshold value, the RC-IGBT can 1 operated at the rated operating frequency by changing the voltage of the gate signal 2-1 T alternates between the switch-on _{value V 1} and the switch-off _{value V 2} at least once within each switchover period.

With reference to the 9B and 9D an overload current situation will now be discussed in more detail. For example, due to a fault on the DC side, an overload current must flow from the circuit arrangement 3 be guided. In such a case, both signals could 2-1 and 2-1 ' be provided with a voltage V ₂ , as in FIG 9B displayed. This could be sufficient to carry an overload current if a further external path is also provided, for example by means of a thyristor 54 as in relation to 11 explained. However, since such an external current path is not part of the circuit arrangement 3 will be the RC-IGBT 1 put in the overload state by the gate signal 2-1 is provided with a voltage V _OL , as in 9D displayed. The voltage V _OL can be contained in the overload _{voltage range R 2} and can be -40 V, for example. Therefore, the voltage V _OL can be substantially less than V ₂ . This situation is in 9D illustrated. The provision of the voltage V _OL activates the in the RC-IGBT 1 included semiconductor auxiliary areas 112 , which has already been explained in detail with reference to the preceding drawings.

Furthermore, the RC-IGBT 1 be operated continuously in the overload state for at least a minimum period. In one embodiment, the minimum duration is at least as long as the duration of a sine half-wave of an AC power network with which the RC-IGBT 1 can be coupled. Therefore, in the case of a 50 Hz AC power grid, the minimum duration can be at least, for example, 1 * 10 ms, 2 * 10 ms or 3 * 10 ms. Furthermore, such a minimum duration can be equal to or longer than a multiple of the switching duration T, such as 3 * T, 4 * T or even longer, such as 10 * T or 20 * T. For example, the nominal operating frequency is 500 Hz (T = 2 ms). In such a case, the minimum duration can be 10 ms, for example.

It should be noted, however, that during rated operation of the RC-IGBT 1 the voltage of the gate signal 2-1 does not necessarily have to be continuously within the nominal voltage range R ₁ . Rather, the value of the voltage of the gate signal can be used before the load current is commutated 2-1 are no longer than a maximum duration within the overload voltage range R ₂ . Such a maximum duration can be the same as or shorter than a fraction of the switching duration. For example, such a maximum duration during which the voltage of the gate signal 2-1 can lie within the overload voltage range R ₂ , for example 10 microseconds, 5 microseconds, or 2 microseconds. The reason for this type of operation may be to avoid the RC-IGBT 1 shows parasitic behavior during a transition from reverse flow mode to forward flow mode. Such behavior could lead to high losses.

It should also be pointed out that the statements made above regarding the voltage ranges R ₁ and R ₂ deal with a situation in which the respective RC-IGBT 1 or 1' operated in reverse flow mode.

In the above, some drawings showed only parts of a semiconductor device and not a complete semiconductor device. For the sake of clarity of illustration, other features of a semiconductor device have not been shown since such other features are well known to those skilled in the art. For example, it is known to those skilled in the art that the semiconductor anode field 113 in contact with one on the surface 11-5 arranged diffusion barrier layer can be. It is also known to those skilled in the art that the semiconductor source region 114 in electrical contact with one also on the surface 11-5 arranged metallization layer can be. For example, the surface represents 11-5 a front side of the respective semiconductor device 1 dar, where 1 to 5 a rear side of the respective semiconductor device 1 not illustrate schematically. Furthermore, such a rear side can be a semiconductor collector region of the respective semiconductor device 1 include, for example, when the semiconductor device 1 is an RC-IGBT, or a cathode region if the semiconductor device 1 a MCD is. The semiconductor collector region or the cathode region can comprise one or more n-doped regions and / or one or more p-doped regions. In summary, any of the above-listed semiconductor devices 1 a gate terminal connected to the gate electrodes 121 is electrically connected, an emitter connection which is connected to the semiconductor source region (s) 114 is electrically connected, and / or a collector connection which is connected to a rear-side metallization of the respective semiconductor device 1 is electrically connected, include. The respective semiconductor device can 1 receive and output the load current. The respective semiconductor device can 1 the gate signal 2-1 receive.

Each of the semiconductor devices listed above is, for example, a power RC-IGBT or a power MCD, which are suitable for use within a power converter, such as within a power converter for HVDC applications, e.g. within a power converter using an MMC topology having.

For example, the forward load current flows from the rear side to the front side of the respective semiconductor device 1 and the reverse load current flows from the front to the rear of the respective semiconductor device 1 , with such a current direction within 1 to 3 is shown schematically and wherein the current direction can be the so-called technical current direction. In a further embodiment, the reverse load current flows from the rear side to the front side of the respective semiconductor device 1 and the forward load current flows from the front to the rear.

In one embodiment, the respective semiconductor device 1 contacted by a front-side contactor and a rear-side contactor in such a way that a load current flows into the semiconductor region 11 and from the semiconductor field 11 can be coupled, for example from / to a load current transmission line or cable. The front contactor and / or the rear contactor can be configured to carry an overload current, for example an overload current that is many times higher, such as 15 or 20 times higher than a rated load current for which the respective semiconductor device is 1 is designed. For example, the front-side contactor and / or the rear-side contactor includes a number of bonding wires, the number of bonding wires being configured for carrying the overload current. Furthermore, both the front side and the rear side can have a contact surface which is sufficiently large to receive / output the overload current.

In summary, a semiconductor device according to the embodiments described above, when it is in the reverse current mode, which is also referred to as “diode mode”, can be in at least one of a nominal state in which the semiconductor device has commutation robustness and an overload state in which the semiconductor device has an overload current can lead in a reverse direction and in which the semiconductor device does not necessarily have to have commutation robustness.

The embodiments described above include the recognition that, on the one hand, the parallel connection of a thyristor with a freewheeling diode of an RC-IGBT can increase the complexity of a power converter. On the other hand, it is recognized that under nominal conditions in which the RC-IGBT is operated at a nominal switching frequency, it is necessary for the RC-IGBT to have commutation robustness. For this purpose, the charge carrier density within the semiconductor area of the RC-IGBT must not exceed a certain level under nominal conditions. During nominal conditions, the RC-IGBT can operate at the nominal switching frequency, e.g. several hundred Hz, and a load current can commutate between the free wheeling diode cell of the RC-IGBT (reverse direction) and a transistor cell of another RC-IGBT (forward direction) at a rate that corresponds to the switching frequency. The charge carrier density should therefore be restricted in order to enable such a high-rate load current commutation.

However, since a semiconductor device according to one or more of the aforementioned embodiments comprises a semiconductor auxiliary region or the controllable charge carrier injector, the semiconductor device can be operated in the overload state. In the overload state, the controllable charge carrier injector or the auxiliary semiconductor area, which can be part of the controllable charge carrier injector, is used to temporarily increase the charge carrier density within the semiconductor area in order to enable the semiconductor area to conduct the overload current in the reverse direction. Due to the increased charge carrier density, the semiconductor device has low conduction losses. In the overload state, the semiconductor device may no longer have commutation robustness due to this increased charge carrier density. However, since the semiconductor device is preferably not switched over, ie switched on or off, when it is in the overload state, this potential loss of commutation robustness does not have a negative effect on the switching capacitances of the semiconductor device. In other words, it is the commutation of the load current during the overload condition preferably excluded. If the semiconductor device is not operated in the overload state, e.g. operated in the forward current mode or in the nominal state of the reverse current mode, the semiconductor auxiliary region is preferably not used, whereby the charge carrier density within the semiconductor region is kept sufficiently low to ensure commutation robustness of the semiconductor device.

Features of further embodiments are defined in the dependent claims. The features of further embodiments and the features of the embodiments described above can be combined with one another in order to form additional embodiments, as long as these features are not explicitly described as being alternatives to one another.

In order to facilitate understanding of the exemplary embodiments schematically illustrated in the drawings, some of the electrodes have been 121 and 131 marked with a "G", which can be an abbreviation for "Gate", and / or with an "S", which can be an abbreviation for "Source". Therefore, the gate electrodes 121 with a gate connection of the respective semiconductor device 1 be electrically connected and the first electrodes 131 can be connected to an emitter connection (also called an “anode connection”) of the respective semiconductor device 1 be electrically connected.

As stated above, the semiconductor region 11 consist mainly of a semiconductor ^{drift region, for example an n -} drift region, with the pn junctions 11-1 , 11-2 and 11-3 of a respective transition between the semiconductor channel region 111 , the semiconductor auxiliary field 112 and the semiconductor anode region 113 can be formed on the one hand and the semiconductor drift region on the other hand.

Furthermore, the overload current, for example the reverse overload current, as stated above, can be at least ten times higher than the rated load current or even about twenty times as high as the rated load current. Accordingly, there could be a load current density within the semiconductor region 11 of the semiconductor device 1 in an overload situation increase by a corresponding factor, such as ten, twenty and so on.

Furthermore, within this description, the term “doping concentration” can relate to an integral doping concentration or to an average doping concentration or to a plate charge carrier concentration of a specific semiconductor region. Therefore, for example, a statement that a specific semiconductor region has a certain doping concentration that is higher or lower than a doping concentration of another semiconductor region can indicate that the respective mean doping concentrations of the semiconductor regions differ from one another.

For example, in the semiconductor auxiliary area 112 present second doping concentration an average doping concentration in relation to the total volume of the semiconductor auxiliary region 112 be. Furthermore, in the semiconductor channel region 111 present first doping concentration a mean doping concentration in relation to the total volume of the semiconductor channel region 111 be.

In one embodiment, this is in the vicinity of the second pn-junction 11-2 , for example in an area of the semiconductor auxiliary area 112 at a distance between 10 nm and 100 nm, such as at a distance between 20 nm and 50 nm from the second pn junction 11-2 Existing second doping concentration is at least 30% higher than the first doping concentration which is in the vicinity of the first pn junction 11-1 is present, for example in a region of the semiconductor channel region 111 at a distance between 10 nm and 100 nm, such as at a distance between 20 nm and 50 nm from the first pn junction 11-1 . However, the second doping concentration in said area can be even higher, for example twice as high, ten times as high or even higher.

In the above, embodiments relating to semiconductor devices, embodiments relating to circuit arrangements comprising a semiconductor device and embodiments relating to methods for operating a semiconductor device were explained. For example, these semiconductor devices are silicon (Si) based. A monocrystalline semiconductor region or layer, for example the semiconductor regions, is accordingly 11 , 111 , 112 , 113 , 114 of exemplary embodiments, typically a monocrystalline Si region or a Si layer. In further embodiments, polycrystalline or amorphous silicon can be used.

It goes without saying, however, that the semiconductor regions 11 , 111 , 112 , 113 , 114 may be made from any semiconductor material suitable for making a semiconductor device. Examples of such materials include, but are not limited to, elementary semiconductor materials such as silicon (Si) or germanium (Ge), Group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V Semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaP), aluminum gallium nitride (AIGaN), aluminum indium nitride (AllnN), indium gallium nitride (AllnN) or indium gallium nitride (InGaN) InGaAsP) and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name a few. The semiconductor materials mentioned above are also referred to as “homojunction semiconductor materials”. When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AIGaN) - aluminum gallium indium nitride (AIGalnN) -, indium gallium nitride (InGaN) - aluminum gallium indium nitride (AIGalnN) -, aluminum gallium nitride (AIGalnN) -, aluminum gallium nitride (AIGalnN) -, aluminum gallium nitride (AIGallium nitride) (GaIGallium nitride) () Gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AIGaN), silicon silicon carbide (SixC1-x) and silicon-SiGe heterojunction semiconductor materials. The materials Si, SiC, GaAs and GaN are mainly used for power semiconductor device applications at present.

Spatially relative terms such as "below", "below", "lower", "above", "upper" and the like are used for ease of description to explain the arrangement of one element relative to a second element. These terms are intended to encompass various orientations of the particular device in addition to orientations other than those described in the figures. Furthermore, terms such as “first”, “second” and the like are also used to describe various elements, areas, sections, etc. and are not to be understood as limiting. The same terms refer to the same elements throughout the description.

As used herein, the terms “having”, “containing”, “including”, “comprising”, “showing” and the like are open-ended terms that indicate the presence of named elements or features, but do not exclude additional elements or features. The articles “a” and “der / die / das” aim to include the plural as well as the singular, unless the context clearly indicates otherwise.

Against the background of the above range of variations and applications, it is to be understood that the present invention is not to be limited by the preceding description or by the accompanying drawings. Rather, the present invention is limited only by the following claims and their legal equivalents.

Claims (15)

A semiconductor device (1) comprising: - A semiconductor region (11), the semiconductor region (11) having charge carriers of a first conductivity type; - A transistor cell (1-1) contained in the semiconductor region (11); - A semiconductor channel region (111) contained in the transistor cell (1-1), the semiconductor channel region (111) having a first doping concentration of charge carriers of a second conductivity type which is complementary to the first conductivity type, and wherein a transition between the semiconductor channel region (111) and the semiconductor region (11) forms a first pn junction (11-1); - A semiconductor auxiliary region (112) contained in the semiconductor region (11) and different from the semiconductor channel region (111), the semiconductor auxiliary region (112) having a second doping concentration of charge carriers of the second conductivity type, a transition between the semiconductor auxiliary region (112) and the semiconductor region (11 ) forms a second pn junction (11-2), the second pn junction (11-2) being arranged deeper in the semiconductor region (11) than the first pn junction (11-1), and wherein the semiconductor auxiliary region (112 ) is arranged closest to the semiconductor channel region (111) compared to every other semiconductor region of the semiconductor device (1) which comprises charge carriers of the second conductivity type and which forms a further pn junction to the semiconductor region (11); and - The semiconductor channel region (111) is delimited by a first trench (13) and a second trench (12), the first trench (13) comprising a first electrode (131) and a first dielectric (132), the second trench being a Gate electrode (121) for controlling the transistor cell (1-1) and a second dielectric (122), the respective dielectric (132, 122) the respective electrode (131, 121) of the respective trench (13, 12) from the semiconductor body (11) isolated, wherein the semiconductor auxiliary region (112) is arranged in contact with the first and the second trench (12, 13) and with a further first trench (13). Semiconductor device (1) according to Claim 1 , further comprising a semiconductor source region (114) which is contained in the transistor cell (1-1) and is in contact with the semiconductor channel region (111), wherein the semiconductor source region (114) comprises charge carriers of the first conductivity type. Semiconductor device (1) according to Claim 1 or 2 , further comprising a diode cell (1-2) contained in the semiconductor region (11), wherein the diode cell (1-2) comprises a semiconductor anode region (113), and wherein the semiconductor anode region (113) has a third doping concentration of charge carriers of the second conductivity type and wherein the second doping concentration is higher than the third doping concentration. Semiconductor device (1) according to Claim 3 wherein a transition between the semiconductor anode region (113) and the semiconductor region (11) forms a third pn junction (11-3) and wherein the second pn junction (11-2) is arranged at the same depth or lower in the semiconductor region (11) like / as the third pn junction (11-3). Semiconductor device (1) according to Claim 3 or 4th wherein at least two first trenches (13) are contained in the diode cell (1-2), the semiconductor anode region (113) being arranged between two of the first trenches (13) and in contact with the first dielectrics (132) of the two first trenches (13) is. Semiconductor device (1) according to one of the preceding claims, further comprising an auxiliary cell (1-3) contained in the semiconductor region (11), wherein the auxiliary cell (1-3) comprises the semiconductor auxiliary region (112) and is adjacent to the transistor cell (1-1) is arranged. Semiconductor device (1) according to one of the preceding Claims 3 to 5 and after Claim 6 , wherein a distance between the auxiliary cell (1-3) and the transistor cell (1-1) is smaller than a distance between the diode cell (1-2) and the transistor cell (1-1). The semiconductor device (1) according to any one of the preceding claims, further comprising a plurality of the second trenches (12), each second trench (12) comprising a gate electrode (121) and a second dielectric (122). Semiconductor device (1) according to one of the preceding claims, wherein the semiconductor auxiliary region (112) and the semiconductor channel region (111) are separated from one another by parts of the semiconductor body (11). Semiconductor device (1) according to one of the preceding Claims 1 to 8th wherein the semiconductor auxiliary region (112) and the semiconductor channel region (111) are in contact with each other. Semiconductor device (1) according to Claim 8 , wherein at least two of the second trenches (12) are contained in the transistor cell (1-1), wherein - at least one of the second trenches (12) is arranged between the semiconductor auxiliary region (112) and the semiconductor channel region (111), both the semiconductor auxiliary region (112) and the semiconductor channel region (111) is in contact with the second dielectric (122) of the at least one second trench (12); or - the semiconductor auxiliary region (112) is arranged at the same depth or deeper in the semiconductor region (11) as / than the second trenches (12) and is arranged separately from the semiconductor channel region (111). Semiconductor device (1) according to one of the preceding claims, wherein the second doping concentration of the semiconductor auxiliary region (112) is at least twice as high as the first doping concentration of the semiconductor channel region (111). The semiconductor device (1) according to any one of the preceding claims, wherein the semiconductor device (1) is operable in at least one of a forward current mode and a reverse current mode, the semiconductor channel region (111) being configured to carry at least a portion of a rated load current in a forward direction (FC) when the semiconductor device (1) is operated in the forward current mode, and wherein the semiconductor auxiliary region (112) is configured to conduct at least a portion of an overload current in a reverse direction (ROLC) when the semiconductor device (1) is operated in the reverse current mode. Semiconductor device (1) according to one of the preceding claims, wherein the second pn junction (11-2) is arranged at a depth at least 50 nm deeper than the depth of the first pn junction (11-1). Semiconductor device (1) according to one of the preceding claims, wherein the second doping concentration is at least 30% higher than the first doping concentration.

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