DE102006059394B4 - Integrated circuit and method for its manufacture - Google Patents

Abstract

A method of manufacturing an integrated circuit (26), comprising the steps of:
Providing a semiconductor wafer (10) having a first and a second surface (12, 14),
Producing a wafer cavity (16; 44 ') under at least one defined wafer section (18) in the region of the first surface (12),
- generating a circuit structure (20) in the defined wafer portion (18), and
- Separating the defined wafer portion (18) from the semiconductor wafer (10), wherein the wafer portion (18) is released in a first process flow so that it is held only via web-like connections (24) on the remaining semiconductor wafer (10), and wherein the web-like connections (24) are separated in a second process sequence, characterized in that the wafer cavity (16; 44 ') is produced by first providing a substrate wafer (32) which, in the region of the first surface (12), is made from p doped silicon (34) is that the p-doped silicon (34) in the region of the defined wafer portion (18) by means of an anodic etching process in porous silicon (42, 44) is transformed with a plurality of pores, and that the porous Silicon (42, 44) is then subjected to a heat treatment (45), in the course of which the pores on the first surface (12) at least largely close again, the he required material comes from a deeper layer (44) of the porous silicon.

Description

• - Bereitstellen eines Halbleiterwafers mit einer ersten und einer zweiten Oberfläche,
• - Erzeugen eines Waferhohlraums unter zumindest einem definierten Waferabschnitt im Bereich der ersten Oberfläche,
• - Erzeugen einer Schaltungsstruktur in dem definierten Waferabschnitt, und
• - Heraustrennen des definierten Waferabschnitts aus dem Halbleiterwafer, wobei der Waferabschnitt in einem ersten Prozessablauf so freigestellt wird,

dass er nur noch über stegartige Verbindungen an dem verbleibenden Halbleiterwafer gehalten wird, und wobei die stegartigen Verbindungen in einem zweiten Prozessablauf aufgetrennt werden.The present invention relates to a method for producing an integrated circuit, comprising the steps:

• Providing a semiconductor wafer having a first and a second surface,
• Producing a wafer cavity under at least one defined wafer section in the region of the first surface,
• Generating a circuit structure in the defined wafer section, and
• Separating the defined wafer section from the semiconductor wafer, wherein the wafer section is thus released in a first process sequence,

that it is held only on web-like connections to the remaining semiconductor wafer, and wherein the web-like compounds are separated in a second process flow.

Such a procedure is over WO 2005/104223 A1 known.

In particular, the present invention relates to a method for producing so-called chips with an integrated electronic circuit, wherein the chips or the chip material are very thin. Chips according to the invention can have a thickness of significantly less than 100 μm, advantageously a thickness of about 50 μm and less, particularly preferably a thickness of about 20 μm. Such thin chips are well suited for the production of so-called 3D chips, in which several thin chips, each with an integrated circuit stacked on each other. Moreover, due to the small thickness of the material, such thin chips have some flexibility so that they can be applied to flexible carrier materials, e.g. a plastic film, can be used.

One way of making such thin chips with an integrated circuit is to first fabricate the integrated circuit on a semiconductor wafer having a thickness of, for example, 500 μm to 800 μm. After the integrated circuit is fabricated, the back side of the semiconductor wafer is removed by a mechanical and / or chemical process. Subsequently, the semiconductor wafer, which typically carries a plurality of integrated circuits, must be singulated to the chips. Conventionally, this is done by sawing, cutting, cutting or scribing and breaking. A method of separating semiconductor wafers into chips is known in DE 40 29 973 A1 described.

The procedure described has the disadvantage that a significant portion of the wafer material is lost unused by the removal. Furthermore, relatively large distances between the individual chips must be provided on a wafer, so that there is enough space for sawing, cutting loops, etc. available.

Typical distances here are in the order of 150 μm. All this has a detrimental effect on the cost of manufacturing thin integrated circuits, i. Chips with material thicknesses of less than 150 μm.

The aforementioned WO 2005/104223 A1 describes a method in which a multiplicity of vertical trenches are first produced on the first surface of the semiconductor wafer by an anisotropic etching process. Subsequently, the opened first surface is closed again by an epitaxial layer and the semiconductor wafer is subjected to a heat treatment (annealing). As a result, individual closed channels are to be formed below the first surface. In a further anisotropic etching process then vertical accesses to the hidden channels are created. Subsequently, the inner walls of the channels and the vertical access are provided by an oxidation process with an oxide layer. The channels and vertical accesses surround a wafer portion on the first surface where a circuit structure is then conventionally created. Subsequently, the oxide layer in the channels and vertical accesses is removed by a further etching process, so that the wafer section is connected only via web-like connections on its underside with the rest of the wafer. These connections are broken up by tearing the wafer section upwards out of the remaining semiconductor wafer, wherein a torsional movement is additionally proposed. With this method chips with a thickness of less than 10 microns can be produced.

In this known method, the production of the deep-lying oxide layers below the Waferabschitt and their subsequent selective etching out consuming and difficult. In addition, this method has the disadvantage that the formation of the web-like connections depends to a great extent on individual process parameters, which can vary in many ways. Therefore, the formation of web-like compounds with precisely defined properties is extremely difficult, if possible at all. If the web-like connections become too thick, there is a considerable risk that the chip will be damaged when it breaks out. If they get too thin, the necessary stability for the generation of the circuit structure is missing.

The reproducibility of the web-like connections and process reliability can therefore only be guaranteed with great effort, if at all.

From an article by Overstolz et al. entitled "A Clean Wafer-Scale Chip-Release Process Without Dicing Based on Vapor Phase Etching", 17th IEEE International Conference on Micro Electro Mechanical Systems, January 2004, pages 717 to 720, discloses a micromechanical sensor, namely a Inclinometer to dissolve out of a silicon material solely by different etching processes. The starting material is an SOI wafer (Silicon on Insulator). Trenches and holes are etched from both the front and back of the wafer material to release the tilt sensor. In addition, the oxide layer located in the semiconductor material is partially etched out by bringing hydrofluoric acid vapor through the holes at the front and back into the interior of the semiconductor wafer.

US 6,165,813 A describes a method for detaching thin chips attached to a flexible substrate by bending the substrate. US Pat. No. 6,521,068 B1 describes a method of dicing chips from a substrate by heating a region underneath the chip with a laser.

JP 2002-299500 A describes the removal of chips by means of a so-called dummy substrate.

Finally, in the prior art, the production and use of porous silicon is known. DE 197 52 208 A1 discloses a method of making a membrane sensor wherein a thin layer of silicon carbide or silicon nitride is deposited over a region of porous silicon. The porous silicon is then removed as sacrificial material with ammonia. As a result, a cavity which thermally decouples the sensor membrane from the remaining substrate is formed under the membrane layer of silicon carbide or silicon nitrite.

A similar process for making a piezoresistive pressure sensor with a monocrystalline silicon free suspended membrane is disclosed in a paper by Armbruster et al., "Surface Micromachining of Monocrystalline Silicon Membranes Using a Silicon Micro Grid of Sintered Porous Silicon", Technical Digest of Eurosensors XVIII, Rome, September 12-15, 2004, pages, 22/23. In this method, a p-doped silicon substrate is provided in a first step with shallow n-doped regions and with deep n ⁺ doped regions. The shallow n-doped regions form a lattice structure on the surface of the p-doped silicon substrate. Subsequently, the p-doped silicon substrate is converted below the lattice structure into porous silicon. For this purpose, the regions of the p-doped substrate below the n-doped lattice regions are undercut in concentrated hydrofluoric acid. A subsequent sintering process results in the sintered porous silicon forming a cavity below the lattice structure. Over the grid structure, an epitaxial layer is then applied, which forms the sensor membrane of the pressure sensor. The cavity formed by means of the porous silicon is closed again in this way.

US 2005/0029224 A1 describes a method in which a monocrystalline silicon layer is epitaxially grown on a layer of porous semiconductor material. The porous semiconductor material can be produced by an anodic etching process followed by a heat treatment. The monocrystalline layer can be detached later

Furthermore, porous silicon is used in the so-called ELTRAN process (epitaxial layer TRANsfer), with the aid of which SOI wafers can be produced. The procedure is described in a paper by T. Yonehara and K. Sakaguchi entitled "ELTRAN; Novel SOI-Wafer Technology "in JSAP International no. 4, July 2001 appeared.

Against this background, it is an object of the present invention to provide an alternative method to produce thin integrated circuits as inexpensively and with high quality and yield. It is also an object of the invention to provide an integrated circuit which can be easily and inexpensively manufactured by such a method.

This object is achieved according to one aspect of the present invention by a method of the type mentioned above in which the wafer cavity is produced by providing a substrate wafer which is in the region of the first surface of p-doped silicon in which the p-doped Silicon is converted in the region of the defined wafer portion by means of an anodic etching process in porous silicon having a plurality of pores, and in which the porous silicon is then subjected to a heat treatment, during which the pores on the first surface at least largely close again the required material comes from a deeper layer of porous silicon.

Preferably, in this way, a plurality of wafer cavities are produced in the region of the first surface of the semiconductor wafer, wherein the individual wafer cavities are separated from one another by lateral walls. Accordingly, will formed a plurality of wafer sections, under each of which is a separate wafer cavity. Preferably, a circuit structure is generated in each defined wafer section, so that a plurality of thin chips with the same or different circuit structures can be produced in a common process run.

According to a further aspect of the invention, this object is achieved by an integrated circuit with a circuit structure which is formed in a semiconductor material having at least a first material layer and a second material layer, wherein the first and the second material layer are arranged one above the other, the circuit structure substantially is formed in the first material layer, and wherein residues of separated web-like compounds are arranged in the region of the second material layer, the second material layer containing p-doped porous silicon, which has been subjected to a heat treatment.

The new method has the advantage that the individual wafer cavities can be produced with a very high reproducibility and process reliability, which enables a high yield in the production of thin chips. In addition, the web-like connections, which hold the individual defined wafer sections prior to separation, can be dimensioned and placed very precisely. This applies both to web-like connections on the lateral periphery of the wafer sections and also to web-like connections below the defined wafer sections. The latter support the remainder of the exposed wafer section in a column-like manner down on the remaining semiconductor wafer, as is in principle known from the aforementioned WO 2005/104223 A1 is known. In contrast to the procedure described there, low, vertical, web-like connections within the wafer cavity can be created very simply and with high reproducibility with the invention, as described below with reference to a preferred exemplary embodiment. Moreover, with the same technology and in a common process sequence, vertical, lateral as well as both variants of bar-type connections can be made, so that the new method is much more flexible in terms of the suspension of the future chips. The "suspension" of the future chips can therefore be better optimized for the subsequent process steps by web-like connections are arranged with relatively precisely defined dimensions either on the lateral periphery and / or below the defined wafer sections. Thus, the stability of the wafer and the fracture behavior of the chips can be optimized during separation.

Overall, the new method thus allows a well manageable, cost-effective and high-quality production of thin integrated circuits. The object mentioned is therefore completely solved.

In one embodiment of the invention, the wafer cavity is produced under the defined wafer section as a closed wafer cavity.

In this embodiment, the wafer cavity is closed to the outside and thus hidden in the semiconductor wafer. There is no conscious access from outside into the cavity. Such a cavity has the advantage that the semiconductor wafer of the cavities can be stored in stock, whereby the production process can be better rationalized and made even more cost-effective.

It is particularly preferred if the wafer cavity is formed as a closed cavity during the entire production process, because then penetration of impurities is excluded in the cavity. This preferred embodiment can be realized well with the aid of the porous silicon, since the pore formation in the anodic etching process can be varied as a function of the anode current and the exposure time. In other words, the wafer cavity is always covered here by porous semiconductor material. The porous semiconductor material has pores. However, these pores are spatially very narrow openings, which are widely scattered over a relatively large area in relation to the pore size. It is therefore a largely closed ceiling over the cavity. This configuration leads to a very uniform surface above the cavities, so that the semiconductor material available for the production of the circuit structures is of higher quality. Therefore, this embodiment enables a further increase in the yield.

In a further embodiment, the porous silicon has an areal extent which corresponds to the areal extent of the defined wafer section.

In this embodiment, a wafer cavity is produced under the defined wafer section, which is laterally expanded just so far that the defined wafer section "floats" over the remaining semiconductor wafer. The surface expansions of cavity and wafer section are largely the same. Alternatively, it would also be possible to produce wafer cavities whose surface area laterally is significantly larger than that of the defined wafer sections. In contrast, the preferred embodiment has a greater stability, which contributes to the further increase of the yield.

In a further embodiment, a multiplicity of local, n-doped regions are produced in the p-doped silicon of the substrate wafer before the p-doped silicon is converted into porous silicon by means of the anodic etching process.

This embodiment is particularly preferred because n-doped regions are not attacked in the course of the anodic etching process. Therefore, the dimensions of the wafer cavities and the position and dimensions of the web-like connections in this embodiment can be set very precisely.

In a further embodiment, a first group of strip-type n-doped regions is generated, which form an n-doped lattice structure with enclosed p-doped facets on the first surface. Preferably, the p-doped facets have a lateral surface area corresponding to the areal extent of the defined wafer sections, i. the p-doped facets form the defined wafer sections for receiving the circuit structures.

With these embodiments, the size of the hidden wafer cavities can be set very accurately because the strip-like areas act as partitions between the cavities. Furthermore, with the aid of such strip-like n regions, the lateral spacing between the wafer sections can be adjusted, so that the available wafer surface can be subdivided optimally in order to obtain efficient land use. With relatively wide strip-like areas, for example, the stability of the wafer surface can be increased despite the hidden cavities. Narrow areas enable particularly efficient use of space. Since n-doped regions can be formed very accurately with the aid of known masking methods, this embodiment allows a very exact division of the wafer.

In a further embodiment, a second group of punctiform n-doped regions is generated, wherein at least one punctiform n-doped region is arranged in the region of the defined wafer section. Preferably, at least one punctiform n-doped region is arranged in each facet.

With this configuration, very precise web-like connections can be formed on the underside of the defined wafer sections, such vertical webs on the underside preventing or at least reducing a strong bending of the material over the cavity. Therefore, this embodiment allows a very flexible design of the process flow as well as a stable suspension of the wafer sections during the production of the circuit structures.

In a further embodiment, at least one annular n-doped region is generated, which is preferably arranged concentrically with respect to the substrate wafer, wherein the punctiform n-doped regions are distributed substantially uniformly within the annular n-doped region.

This configuration makes it possible to prepare vertical web-like connections on the entire surface of the semiconductor wafer without making solid facets or subdivisions. The user thus has the opportunity to individually determine the chip area of the future chips, since the entire surface of the wafer, which lies within the annular n-doped region, can be freely suspended. Therefore, even chips with different chip area can be individually produced on a wafer.

In a further embodiment, after the heat treatment, an epitaxial layer is applied to the porous silicon, wherein the circuit structure is generated at least predominantly in the epitaxial layer. Preferably, the circuit structure is completely disposed in the epitaxial layer.

In the preferred embodiments of the invention, the epitaxial layer is produced over the entire surface of the entire surface of the semiconductor wafer, resulting in a semiconductor wafer having on the one hand hidden cavities and on the other hand a very uniform, preferably monocrystalline surface. Such a surface is advantageous because it facilitates a largely error-free generation of the circuit structures with a high yield. Any defect in the semiconductor material on the surface of the wafer carries the risk of process errors that degrade the yield. In the preferred embodiments of the invention, the epitaxial layer is produced on a substantially flat surface, which is a significant advantage over the method WO 2005/104223 A1 represents.

In a further refinement, after the circuit structure has been generated, the defined wafer section is freed such that web-like connections are formed on a lateral periphery of the wafer section. Preferably, the defined wafer section is freed by etching trenches into the depths of the wafer at the sides of the wafer section, preferably by an anisotropic etching process.

Lateral web-like connections have the advantage that the defined wafer section can be broken with the aid of shear forces from the remaining semiconductor wafer relatively easily. The risk of damage to the circuit structure in the defined wafer section is comparatively low. Furthermore, can be adjusted by the choice of the lateral distance between the web-like compounds and the surface areas in which the circuit structures are generated, a freely selectable "safety margin", which contributes in a simple manner to further increase the yield. In addition, lateral web-like connections lay the break points on the lateral periphery of the chips, so that the chip bottoms can be made relatively uniform, which is advantageous in stacking thin chips.

In a further embodiment, the wafer section is arranged in the semiconductor wafer in the [100] -direction or in the [110] -direction and the web-like connections are arranged at the corners or side edges of the wafer section.

This embodiment is preferred because the refractive behavior of semiconductor wafers is different depending on the position of a fracture edge relative to the crystal lattice. With this configuration, the forces that are required for the separation of lateral web-like connections, minimize, whereby the risk of unwanted damage is further minimized.

In a further refinement, the p-doped silicon in the region of the defined wafer section is converted by means of the anodic etching process into an upper layer of porous silicon having a multiplicity of finer pores and into a lower layer having a multiplicity of larger pores.

The penetration depth and pore size of the layers can be varied in producing the porous regions by, for example, varying the current density of the current flowing through a hydrofluoric acid solution to the substrate wafer used as the anode. By creating a large pore lower (lower) layer and a finer pored upper (higher) layer, a hidden wafer cavity can be formed without having to fully open the top of the semiconductor wafer. This is advantageous because it allows a higher quality of material to be produced on the surface of the semiconductor wafer. As a result, the yield can be further increased.

In a further embodiment, a substrate wafer is provided which has on the first surface an upper layer and an underlying lower layer, wherein the upper layer is a more p-doped silicon than the lower layer. Advantageously, the porous silicon is formed in the more heavily p-doped upper layer, whereas the lower p-doped lower layer serves merely as a supporting substrate material.

The embodiment is advantageous because with the aid of the different dopings, it is possible to compensate for material stresses which inevitably arise due to the formation of the wafer cavities or cavities. Due to the different dopings, breakage due to such material stresses can be avoided.

In a further embodiment, the remaining semiconductor wafer is ground off after the separation of the defined wafer section and provided as a substrate wafer for the production of further integrated circuits.

This embodiment is particularly advantageous because it allows efficient utilization of the semiconductor material. Therefore, this embodiment leads to a particularly cost-effective production of thin chips with integrated circuits.

It is understood that the features mentioned above and those yet to be explained below can be used not only in the particular combination given, but also in other combinations or in isolation, without departing from the scope of the present invention.

• 1 eine vereinfachte Darstellung zur Erläuterung eines bevorzugten Ausführungsbeispiels des neuen Verfahrens,
• 2 eine vereinfachte Darstellung zur Erläuterung der Prozessfolge, mit deren Hilfe der Waferhohlraum unter einem definierten Waferabschnitt erzeugt wird,
• 3 eine schematische Draufsicht auf einen Halbleiterwafer, der mit Hilfe des neuen Verfahrens bearbeitet wird,
• 4 eine schematische Darstellung der Vereinzelung der Chips in einer bevorzugten Variante des neuen Verfahrens,
• 5 einen Ausschnitt aus dem Halbleiterwafer aus 3 in einem seitlichen Querschnitt,
• 6 einen Teil eines vereinzelten Chips mit einer integrierten Schaltung in einem seitlichen Querschnitt ähnlich wie in 5, und
• 7 eine schematische Draufsicht auf einen Halbleiterwafer ähnlich zu dem aus 3, wobei ein großer Hohlraum innerhalb einer ringförmigen Begrenzungswand vorgesehen ist.

Embodiments of the invention are illustrated in the drawings and are explained in more detail in the following description. Show it:

• 1 a simplified representation to illustrate a preferred embodiment of the new method,
• 2 5 is a simplified representation to explain the process sequence with the aid of which the wafer cavity is produced under a defined wafer section;
• 3 a schematic plan view of a semiconductor wafer, which is processed by means of the new method,
• 4 a schematic representation of the separation of the chips in a preferred variant of the new method,
• 5 a section of the semiconductor wafer 3 in a lateral cross section,
• 6 a part of a single chip with an integrated circuit in a lateral cross-section similar to in 5 , and
• 7 a schematic plan view of a semiconductor wafer similar to that from 3 wherein a large cavity is provided within an annular boundary wall.

In 1 is a semiconductor wafer with the reference numeral 10 designated. The semiconductor wafer 10 has a first surface 12 and an opposing second (lower) surface 14 , Below the first surface 12 is a cavity 16 arranged so that a wafer section 18 is mounted "suspended" above the cavity. As in 1a) is shown, the semiconductor wafer has a plurality of such cavities 16 which are hidden inside the semiconductor material.

In a first embodiment of the invention, such a semiconductor wafer 10 provided ( 1a) , Subsequently, in the wafer sections 18 above the cavities 16 each generates a circuit structure in a conventional manner. The circuit structure is in 1b at the reference number 20 shown schematically. It lies in preferred embodiments in [100] or [110] direction with respect to the crystal lattice of the wafer material. The wafer section 18 with the circuit structure 20 forms a future chip with an integrated circuit, which now consists of the semiconductor wafer 10 must be removed.

This is done in the embodiment shown in that a plurality of trenches 22 in the surface 12 of the semiconductor wafer 10 etched into it, with the individual trenches 22 through web-like areas 24 are separated from each other. In the preferred embodiment, the trenches are 22 latticed on the surface 12 of the semiconductor wafer 10 distributed and they form a pattern of vertical and horizontal trenches. There, where a vertical and a horizontal ditch 22 is a web-like area 24 remained, which was not etched. Four trenches each surround a wafer section 18 with the integrated circuit structure 20 , Accordingly, here is each wafer section 18 only at its four corners by the web-like connections 24 held. Alternatively, the wafer sections could 18 also be held over web-like connections, not at the corners, but for example at the center of the side edges of each wafer section 18 are arranged. In addition to the bridge-like areas 24 at the lateral periphery of the individual wafer sections 18 web-like connections can also be provided on the underside of the individual wafer sections, as described below with reference to FIGS 2 . 5 and 6 is described. The new method makes it possible, web-like connections optionally only below the defined wafer sections 18 To arrange only at their lateral periphery or combined both down and at the lateral periphery.

As in 1c is shown, the individual wafer sections 18 from the grid of trenches 22 be broken out, and you get in this way chips 26 with an integrated semiconductor structure.

2 shows a preferred embodiment to a semiconductor wafer 10 to 1 manufacture. According to 2 initially becomes a substrate wafer 32 provided, which consists of monocrystalline, weakly p-doped silicon. According to 2 B becomes the substrate wafer 32 at its top with an upper layer 34 made of stronger p-doped silicon. In preferred embodiments, this is done by the top of the substrate wafer 32 is provided in a known manner with further doping atoms, wherein the doping may be about 10 ¹⁸ here. The substrate wafer 32 now has an upper layer 34 with a stronger p-doping and a lower layer 36 with a weaker p-doping. Also, in the upper layer 34 n-doped regions 38 . 40 educated. These are preferably n ⁺ -doped regions, ie the regions 38 . 40 are provided with a high concentration of n-doping atoms. The training of the areas 38 . 40 can be done by known methods, such as ion implantation or other conventional masking technique.

According to 2c then become porous layers 42 . 44 in the heavily p-doped layer 34 generated. For this purpose, the substrate wafer 32 in a preferred embodiment as an anode in a solution of hydrofluoric acid and alcohol, so that a current can flow through the solution to the substrate wafer. As a result, porous silicon forms in the region of the upper layer 34 wherein the pore size can be varied by varying the current density. In the preferred embodiment, a fine-pored layer 42 on the surface of the substrate wafer and a large pore layer 44 underneath it. A more detailed description of the preparation of these layers is contained in the aforementioned publication by Yonehara / Sakaguchi, to which reference is expressly made here in relation to the production of porous silicon layers.

According to 2d becomes the wafer with the porous layers 42 . 44 then a heat treatment 45 exposed, for example, at about 1100 ° C. As a result, the pores in the upper fine-pored layer 42 at least largely close, leaving the top layer 42 again in a largely uniform, monocrystalline layer 42 ' is transformed. Below that is the 44 ' whose pore size has increased so much that it is almost impossible to speak of a material layer. The large-pored layer 44 ' now forms the cavity that is in 1 with the reference number 16 is designated. Within this cavity still isolated webs (not shown here) may remain, which are the upper layer 42 ' connect to the underlying substrate material. Such webs may result from process variations and practical limitations in creating the cavity 16 his. In addition, vertical connecting bridges with the help of n-doped areas 40 be generated selectively, as further below with reference to 5 and 6 is explained in more detail with reference to a practical example.

According to 2f will be another layer next 48 as a topcoat on the surface of the layer 42 ' applied. In a preferred exemplary embodiment, this is a monocrystalline epitaxial layer with a dopant adapted for the subsequent component, which is present on the entire surface of the wafer, including the layer 42 ' is grown up. The dopant may optionally be of the n- or p-type. This gives a semiconductor wafer 10 according to the process steps according to 1 is provided as starting material.

How to get in 2f can recognize the cavity extends 44 ' between the lateral n-doped regions 38 , to some extent the lateral boundaries of the cavity 44 ' form. The lateral surface extent of the cavity 44 ' is here designated by W. In the preferred embodiments, the cavity has 44 ' a rectangular and preferably at least substantially square base, as in the 1a to 1c is shown. Accordingly, the lateral surface extent of the cavity 44 ' in the depth of the viewing direction also W.

How to get in 3 can recognize, the n-doped regions run 38 strip-like over the entire wafer 10 , It owns the wafer 10 a first group of stripe-like n-doped regions 38 and a second group of n-doped strip-like regions 38 ' , each orthogonal to each other, so that the strip-like areas 38 . 38 ' facets 50 form. The lateral surface extent of each facet 50 corresponds to the cavity 44 ' below the surface of the wafer 10 , Within the cavities can (but need not) punctual n-doped regions 40 be arranged after the formation of the cavity 44 ' serve as selective vertical support connections for the otherwise freely suspended wafer section.

As from the synopsis of 1 and 2 can be seen corresponds to the lateral surface extent W of the cavity 16 and approximately the lateral surface extent of the wafer section 18 in which the circuit structure 22 is produced. Thus determines the lateral surface extent of the porous layers 42 . 44 also the chip area of the later chip 26 , In other words, the lateral surface extent of the porous layers 42 . 44 approximately equal to the area of the future chips.

4 shows a preferred embodiment for separating the chips 26 , The chips 26 be here with the help of a gripping tool 52 that captures the chips 26 (more precisely, the wafer sections 18 still at the web-like connections 24 hang) with vacuum sucks. By pressure from above (arrow 54 ) become the web-like connections 24 broken up by the single chip 26 is pushed down into the cavity. Then the chip can 26 with the gripping tool 52 be picked up and processed further. Alternatively or additionally, the chip 26 also by tensile forces and / or torsional forces from the wafer 10 to be broken out. Preferably, the gripping tool is a pick-and-place tool as used for handling SMD components.

Among the advantages of in 1 and 2 It is heard that the remaining semiconductor wafer 10 after removing all chips 26 can be recycled. For this purpose, the semiconductor wafer 10 with the remaining web areas 24 ( 4d ) ground and polished on its upper side, resulting in 4e at the reference number 56 is shown symbolically. This yields a (somewhat thinner) substrate wafer 32 , the process sequence again 2 can be subjected.

As in 4 is shown grips the gripping tool 52 the individual chips 26 largely congruent. Accordingly, the gripping tool 52 in the area of its lower gripping surface 58 formed approximately the same size as the lateral surface extent of the chip 26 , This allows the gripping tool 52 the sensitive chips 26 hold securely. The risk of damage when breaking out of the semiconductor wafer 10 is further minimized.

In 5 is a partial section of the wafer 10 shown in a side, sectional view. The representation in 5 was the inclusion of a correspondingly cut wafer 10 imitated with the help of an electron microscope, since the recording itself can not be duplicated in sufficient quality. For the sake of good order, however, it should be noted that the illustration in 5 not exactly true to scale. Like reference numerals designate the same elements as before.

As in 5 can be seen, can be with the help of the procedure described hidden cavities 44 ' produce a relatively sharp separation between the overlying layer 42 ' and the underlying substrate material 32 form. Since the n-doped areas, here the area 40 in which anodic etching process is not attacked, the cavities end up 44 ' at such an n-doped region. If the n-doped region has a local, point-like extent, in this way a local, bar-like anchor point is created, via which the epitaxial layer 48 on the supporting substrate material 32 is supported.

In contrast, when the n-type doped regions are striped through the semiconductor wafer 10 run, create a lateral boundary walls, the adjacent cavities 44 ' separate from each other and accordingly facets form, as in 3 are shown.

6 shows a partial section of a chip 26 with an integrated circuit structure 20 which was produced according to the new method. How to compare to 5 can recognize, became the chip 26 by breaking up the local, web-like connection 40 from the underlying substrate material 32 separated. The chip 26 thus has a first, upper layer of material, essentially from the epitaxial layer 48 is formed. In this material layer, in the preferred embodiments, the circuit structure 20 implemented. Below is a second, lower material layer 42 ' arranged essentially from the former fine-pored and by material enrichment again largely closed layer 42 is formed. On the bottom of the layer 42 ' There is a certain waviness or roughness, which is mainly due to the fractures in the region of the n-doped regions 38 . 40 results.

7 shows the top view of a substrate wafer 32 ' with an annular n-doped region 62 which is concentric around the periphery 64 of the wafer is arranged. Within the annular n-doped region 62 are a variety of local, punctual n-doped areas 40 largely evenly distributed. Now, when the porous silicon is generated in this substrate wafer, a continuous, closed cavity is formed which extends over a majority of the entire wafer surface. Within this cavity, the punctiform n-doped regions form 40 vertical support points with which the porous layer 42 ' is supported down. Such a wafer allows the user to increase the area of his chips 26 individual and variable. Therefore, the substrate wafer is suitable 32 ' especially good for stockpiling. The individual chip areas, the user then through vertical trenches 22 as they are in 1 are shown subdivide. Due to the vertical support points at the punctiform n-doped areas 40 You can also on lateral web-like connections 24 without. However, you can also additionally lateral web-like connections 24 during the etching of the trenches 22 let stand to get an even more stable suspension of the chip area.

Claims (14)

A method of fabricating an integrated circuit (26) comprising the steps of: - providing a semiconductor wafer (10) having first and second surfaces (12, 14), - producing a wafer cavity (16; 44 ') under at least one defined wafer portion ( 18) in the region of the first surface (12), - generating a circuit structure (20) in the defined wafer section (18), and - separating out the defined wafer section (18) from the semiconductor wafer (10), the wafer section (18) in one first process sequence is released so that it is held only via web-like connections (24) on the remaining semiconductor wafer (10), and wherein the web-like connections (24) are separated in a second process sequence, characterized in that the wafer cavity (16; 44 ') is produced by first providing a substrate wafer (32), which in the region of the first surface (12) consists of p-doped silicon (34) that the p-doped In the region of the defined wafer section (18), silicon (34) is converted into porous silicon (42, 44) having a multiplicity of pores by means of an anodic etching process, and the porous silicon (42, 44) is subsequently subjected to a heat treatment (45). during which the pores on the first surface (12) at least largely close again, wherein the material required for this purpose comes from a lower layer (44) of the porous silicon. Method according to Claim 1 characterized in that the wafer cavity is created under the defined wafer portion (18) as a closed wafer cavity (16; 44). Method according to Claim 1 or 2 , characterized in that the porous silicon has a surface area (W) corresponding to the surface area of the defined wafer portion (18). Method according to one of Claims 1 to 3 , characterized in that in the p-doped silicon (34) of the substrate wafer (32) a plurality of local, n-doped regions (38, 40) is generated before the p-doped silicon (34) by means of the anodic etching process is converted into porous silicon (42, 44). Method according to Claim 4 , characterized in that a first group of strip-like n-doped regions (38) is generated, the form the first surface of an n-doped lattice structure (38, 38 ') with enclosed p-doped facets (50). Method according to Claim 4 or 5 , characterized in that a second group of punctiform n-doped regions (40) is generated, wherein at least one punctiform n-doped region in the region of the defined wafer portion (18) is arranged. Method according to Claim 6 , characterized in that an annular n-doped region (62) is produced, which is preferably arranged concentrically to the substrate wafer (32), wherein the punctiform n-doped regions (40) within the annular n-doped region (62) substantially evenly distributed. Method according to one of Claims 1 to 7 , characterized in that after the heat treatment (45) an epitaxial layer (48) is applied to the porous silicon (46), wherein the circuit structure (20) is generated at least predominantly in the epitaxial layer (48). Method according to one of Claims 1 to 8th , characterized in that the defined wafer portion (18) is released after the production of the circuit structure (20) so that on a lateral periphery of the wafer portion (18) web-like, local connections (24) arise. Method according to one of Claims 1 to 9 , characterized in that the wafer section (18) is arranged in the semiconductor wafer (10) in the [100] direction or in the [110] direction, and in that the web-like local connections (24) at corners or at side edges of the wafer section (18). to be ordered. Method according to one of Claims 1 to 10 , characterized in that the p-doped silicon (34) in the region of the defined wafer portion (18) by means of the anodic etching process in an upper layer (42) of porous silicon having a plurality of finer pores and in a lower layer (44). is transformed with a variety of larger pores. Method according to one of Claims 1 to 11 characterized in that the substrate wafer (32) has on the first surface (12) an upper layer (34) and an underlying lower layer (36), the upper layer (34) being a more p-type doped silicon than the one lower layer (36). Method according to one of Claims 1 to 12 , characterized in that the remaining semiconductor wafer (10) after the separation of the defined wafer portion (18) ground and provided as a substrate wafer (32) for the production of further integrated circuits (26). An integrated circuit having a circuit structure (20) formed in a semiconductor material having at least a first material layer (48) and a second material layer (42 '), wherein the first and second material layers (48, 42') are stacked the circuit structure (20) in the first material layer (48) is formed, and wherein remnants of separated web-like compounds (40) in the region of the second material layer (42 ') are arranged, wherein the second material layer (42') p-doped porous silicon contains, which has been subjected to a heat treatment (45).

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