DE10115885A1 - Management system for real-time interrupt requests e.g. for computing and processing resources units, includes priority decoder for each of three planes - Google Patents

Abstract

A system for managing interrupts has a priority decoder (10,Bn,Cn) with several interrupt inputs (int-i) to which are connected several interrupt sources (B1,B2).The priority decoder (10,Bn,Cn) has a circuit for conversion of a signal present at the interrupt input (int-i) into a vectorally coded address of the corresponding interrupt source, which is outputted at the address (addrh) of the priority decoder (10,Bn,Cn) and supplied to a CPU. An Independent claim is given for a method for managing interrupt requests of system devices.

Description

The invention relates to a system and a method for Manage interrupt requests, especially in one Real-time system.

The resources of a computing and processing unit (CPU) are usually limited and therefore must have individual sys units are made available sequentially. to The system devices send requests for computing power so-called interrupts to a CPU, which then requests the carries out another task. The interrupt signals can be un have different priorities and will be accordingly processed their priority. An example of an inter rupt with high priority is e.g. B. that of a FIFO Memory that threatens to overflow and is therefore read out got to.

It is known to receive interrupt signals from system devices to transmit a so-called host, which, if present, ner interrupt request a register in polling mode reads to determine the address of the interrupt source. The host first reads out the register, determines it the address of the interrupt source and the data read out then triggers an associated procedure that is initiated by the CPU will work.

This system has the disadvantage that the readout of the register ters is relatively expensive, which is particularly the case with a large Large number of interrupt sources to slow down the sys leads.

It is therefore the object of the present invention to provide a sys system and a procedure for managing interrupt requests  to create that works much easier and works faster.

The essential inventive idea is according to the invention in it, a vector (Poin ter) to deliver as the interrupt address that is on the interrupt source shows.

The system according to the invention comprises at least one priori tatsdecoder with multiple interrupt inputs at which ver different interrupt sources are connected. The priori tatsdecoder comprises a circuit for converting an am input signal present in a vectorial coding te address, especially in a binary coded interrupt Address vector. The priority decoder also has an address output at which the interrupt address vector is output, as well as an interrupt output from which an interrupt signal is given, the interrupt signal and the interrupt ad ressvektor be fed to a CPU.

The system is preferably cascaded, the Interrupt connected to the priority decoder of a level K swell preferably again at least one priority each rity decoder of a next level K + 1, at whose In interrupt inputs of another level ne K + 2 are connected. The priority decoder of each level K preferably each comprise a circuit for converting an interrupt signal present at its interrupt input into a vectorially, in particular binary, coded address of the corresponding interrupt source that the CPU as part of an overall address vector is supplied.

From a global perspective, the system for administration is processing of interrupts preferably in several levels kaska built up, with each level (K) at least one priority rity decoder, which is an interrupt source for a front level (K - 1) and at its interrupt input  several interrupt sources of a subsequent (K + 1-th) Level are connected.

The interrupt sources of the last level Z, on the other hand, are "ur neuter "interrupt sources, i.e. system facilities that can send a processing request to the CPU.

The priority decoders of a level K preferably comprise ei ne circuit for converting one at its interrupt input interrupt signal present in a vector-coded ad address of the corresponding interrupt source.

The interrupt address vectors each correspond to one corresponding address output of the priority decoder of a specific Level output.

Each level (except the first and last) includes before preferably a logic gate, whose input matches the address the priority decoder of this level over data buses is connected and at the output there is one at the input de address of an interrupt source is switched through.

An address vector is thus provided in each level K, which points to the interrupt source of a level K + 1.

Furthermore, an address register can be provided, on the Input the coded address vectors, preferably each level ne, are guided, and at the exit on from the on total address vector formed in the adjacent address vectors gate is output.

The circuit described above essentially works according to the following procedure:
Evaluating the interrupt inputs of a priority decoder;
Select and acknowledge an interrupt with the highest priority;
Converting the interrupt signal into an address of the corresponding interrupt source; and
Output of the address in the form of a coded address vector.

The acknowledgment of an interrupt by a priority decoder a level K causes the priority decoder of the level K + 1, whose interrupt has been confirmed, by selecting ei one of its own interrupt inputs begins. I.e. the end select a particular interrupt by a priority de coder is only carried out if this is done by a priority rity decoder of the previous level (K - 1) by an ent speaking (acknowledge) signal was released.

A is preferably used for the selected interrupt input Penalty bit set. This will make the corresponding interrupt input blocked, and a new processing request from the same interrupt source is only processed when other ge any interrupts pending at the interrupt input were working.

Conversely, only interrupts are selected, if for their No penalty bit was set at the input.

All interrupt inputs are preferably sampled se within a period of the system clock.

The system for managing interrupts is preferably in remaining deadlock-free, d. that is, after selecting and confirming of a certain interrupt, a subsequent one (on a any other interrupt input of the priority decoder pending) interrupt signal is held until the selected interrupt was processed.

The priority decoder of the first level (A) preferably evaluates First select its interrupt inputs and choose a priority second level (B). This then evaluates selects its interrupt inputs and selects a priority decoder  the third level (C) etc. The evaluation of the interrupts takes place from a lower level K towards one higher level K + 1.

The interrupt to be sent to the CPU is preferably solan held until one priority decoder each Level has evaluated its interrupt inputs. In a sys system with N levels in which a priority decoder inter evaluates rupte inputs in one clock cycle, this takes N Clock cycles.

The interrupt signals of the individual priority decoders are preferably edge triggered.

The interrupt inputs of the priority decoder are preferred scanned in order of priority.

The penalty bits set for the interrupt inputs are preferably reset if no selectable interrupt is present at the interrupt input without a penalty bit.

The invention is described below with reference to the attached figures exemplified in more detail. Show it:

Fig. 1 shows the construction of an interrupt system in accordance with a prior ferred embodiment of the invention; and

Fig. 2 is a flow chart to explain the management of the interrupts.

In Fig. 1 a cascaded in several levels A, B, C on built system for managing interrupts is shown. The first level A comprises a priority decoder 10 with a plurality of interrupt inputs int_i, to which a number of interrupt sources B1, B2 of a second level B are connected. The priority decoder 10 serves to prioritize interrupts, ie to select interrupts according to their priority, and further comprises one. Interrupt output int_o, at which an interrupt signal is output if an interrupt signal present at the intupi input int_i has been selected.

The priority decoder 10 also has a circuit for converting a signal present at the interrupt input int_i into a vector, binary-coded address. The corresponding address vector is output at the address output addrh, the address vector pointing to the interrupt source (priority decoder B1 or B2) of the next level (B).

The address output AddrH of the priority decoder 10 is connected to ei nem register 17, the output from the priority decoder 10 address vector is of an overall ad ressvektors one ingredient, that is, on the causative interrupt a specific, a processing requesting, interrupt source the last level, shows.

The interrupt sources of the second level B are further priority decoders B1, B2, the interrupt output int_o of which are connected to the input int_i of the priority decoder 10 , and which have an address output addrm, each of which is connected to an address input addrm_i of a logic gate 16 .

At the interrupt input int_i of the priority decoder B1, B2 of the second level B, a plurality of interrupt sources are in turn connected, which can transmit appropriate interrupt signals to the priority decoder B1, B2. After the selection of an possibly arriving interrupt signal, a priority deco of B1, B2 outputs a corresponding binary-coded address vector via an address bus to a logic gate 16 at its address output addrm.

In the system, all address buses on one level should have one Gates linked, at whose address output addrm_o the am  Input addrm_i current address is switched through. at In a low active system, all address buses of one Level can be linked with an AND gate while at linked to a high active system with an OR gate should be.

There are several priorities as interrupt sources of the third level C. tatsdecoder C1-C6 provided, each an interrupt gang int_i and an interrupt output int_o.

The address outputs addrl of the priority decoder C1-C6 are in turn connected via corresponding address buses to address inputs addrl_i of two logic gates 13 , 14 , which are designed in particular as AND gates.

At the interrupt inputs int_i the priority decoder C1-C6 are multiple system devices (not shown) closed by means of an interrupt computing power of CPU can request.

The priority decoders C1-C6 in turn output an address vector corresponding to the respective interrupt source, the address outputs addrl of a first group of priority decoders C1-C3 with a first logic gate 13 , and the address outputs addrl of a second group of priority decoders C4-C6 with one second logic gate 14 are connected.

The address outputs addrl_o of the logic gates 13 , 14 are connected to the address input addrl_i of a further logic gate 15 . At the address output addrl_o of the logic gate 15 , the address of the original interrupt source is finally output and the register 17 is supplied via an address bus.

The register 17 thus receives the address addrh of the intent source of the second level B, the address addrm of the interrupt source of the third level C and the address addrl of the system requesting the interrupt, each in the form of an address vector. Taken together, the individual address vectors form an overall address vector which points directly to the original interrupt source.

Each priority decoder 10 , Bn, Cn preferably has an actuation input and / or output (not shown), wherein an acknowledgment output of a priority decoder of a level K is connected to an acknowledgment input of a priority decoder of a level K + 1 in order to select a particular one its int_i input to acknowledge the interrupt signal. Subsequent interrupts are no longer accepted until the selected interrupt has been processed.

The priority decoder of the first level (A) preferably evaluates First select its interrupt inputs, select a priority second level (B) and confirms this with tel of an acknowledge bit. This then evaluates its Inter rupte inputs and selects a third-party priority decoder level (C) off etc. The interrupts are evaluated thus from a lower level K towards a higher one Level K + 1 (from right to left in the figure).

The interrupt to be sent to the CPU is preferably retained until a priority decoder Bn, Cn of levels B, C has evaluated its interrupt inputs. In the system shown with 3 levels, in which a priority deco which evaluates its interrupt inputs int_i in one clock cycle, it takes 3 clock cycles until an interrupt is output by the priority decoder 10 .

FIG. 2a, b shows a typical work flow as it is carried out by ei nem priority decoder in FIG. 1 constructed Sys tem, with a low-active system is adopted in the present example. The process flow also applies to a high-active system.

In step 20 , the priority decoder first checks whether no interrupt for a specific interrupt source has been confirmed at its confirmation output (the designation "n" means negative or low-active). If no, ie an interrupt for this address has already been confirmed, a query is made in step 21 as to whether there is no interrupt. If no, the procedure is ended; if yes, a penalty bit and the variable ack_no are set to 1 for this confirmation output. In addition, all bits of the address vector addr are set to 1 (see step 29 ).

Returning to step 20 , if no confirmation has been given for a specific address, a variable x is set to 0 (step 22 ). In step 23 , a query is made as to whether the variable is smaller than a number n (n is the number of interrupt sources connected to a priority decoder).

If no, all bits of a vector pen and thus all penalty bits are set to 0 in step 27 . If yes, a query is made in step 25 as to whether an interrupt is present at an interrupt input x for which no penalty bit is set. If no, the next interrupt input is evaluated. For this, the variable x is incremented in step 24 .

If yes, it is checked in step 26 whether a confirmation has been received at the confirmation input (this is only required for priority decoders of levels B, C,..., Not for level A). If yes, the address variable addr receives the value of the variable x and the interrupt is confirmed (ack_no (x) <= 0; step 28 ).

The end of the routine is reached in step 30 .

An interrupt to be sent from the priority decoder 10 of the first level A to the CPU is preferably held until a priority decoder Bn, Cn of levels B, C has evaluated its interrupt inputs. The course of this process is shown in Fig. 2b.

First, it is checked in step 31 whether there is no interrupt at an interrupt input with a specific address addr or whether no confirmation has been issued at this address. If no, a delay variable intdly is set to 0 and an interrupt is output at the output of the priority decoder 10 (cf. step 33 ). Otherwise, the delay variable is intdly set to 1 and no interrupt is issued (step 32 ).

LIST OF REFERENCE NUMBERS

A First level
B Second level
C Third level
int interrupt signal
int_i interrupt input
int_o interrupt output
addrl address output
addrm address output
addrh address output
addrl1 address vector
addrl2 address vector
B1, B2 priority decoder of the second level
C1-C6 third level priority decoder

10

First level priority decoder

13-16

logic gates

17

address register

20-34

Steps in the process

Claims (16)

1. System for managing interrupts, comprising a Pri ority decoder (10, Bn, Cn), with multiple interrupt inputs (int_i), to which several interrupt sources (B1, B2) are indicated are closed, and an address output (addrh), the priority decoder (10, Bn, Cn) a circuit for Um convert a signal at the interrupt input (int_i) into a vector-coded address of the corresponding Inter rupt source, which at the address output (addrh) of the Priori tättsdecoders (10, Bn, Cn) output and fed to a CPU becomes. 2. System according to claim 1, characterized, that the system is cascaded in several levels, the interrupt sources each having a priority decoder (B1, B2) of a second level (B), with several In Terrupte inputs (int_i) at which several interrupt sources are connected, as well as an address output (addrm), whereby the priority decoder (B1, B2) of the second level (B) one Circuit for converting one at its interrupt input (int_i) applied interrupt signal in a vectorial ko dated address of the corresponding interrupt source (C1-C6) have the CPU as part of an overall address vector (addr) is supplied. 3. System according to claim 1 or 2, characterized, that the system is cascaded in several levels, is set up, an interrupt source of a Kth level each has a priority decoder at its interrupt Inputs (int_i) each interrupt signals from interrupt sources are supplied to the K + 1-th level, and the Priority decoder of the K th level a circuit for switching an interrupt signal present at its input a vector-coded address of the corresponding interrupt source  the K + 1-th level, which the CPU as Be part of a total address vector (addr) is supplied. 4. System according to claim 3, characterized, that the last level interrupt sources are system setup that send a processing request to the CPU can. 5. System according to any one of the preceding claims, characterized in that each level with a plurality of priority decoders (Bn, Cn) has an associated logic gate ( 13 , 14 , 16 ), the inputs of which with the address outputs (addrl, addrm) of a group of priority decoders (Bn, Cn) are connected, and at the output (addrl_o, addrm_o) an interrupt address vector of an interrupt source (Cn) is output. 6. System according to one of the preceding claims, characterized in that a further logic gate ( 15 ) is provided, the input (addrl_i) of which is connected to the address outputs (addrl_o) of upstream logic gates ( 13 , 14 ) of the same level (C), and at its address output (addrl_o) an interrupt address vector of the interrupt source of the next level (K + 1) is output. 7. System according to one of the preceding claims, characterized, that the system has cascading nested levels, each level (A-C) around a priority decoder (10, Bn, Cn) of the address of an interrupt source connected to it le can output as a binary coded address vector. 8. A method for managing interrupt requests from system devices of a system with at least one priority decoder (10, Bn, Cn) with an address output (addrl, addrm, addrh), to whose interrupt input (int_i) several interrupt sources are connected, comprising the following steps:
Sampling the interrupt input (int_i), selecting and acknowledging an interrupt with the highest priority; and
Output of the address of the associated interrupt source in the form of an interrupt address vector at the output (addrl, addrm, addrh) of the priority decoder (10, Bn, Cn). 9. The method according to claim 8, characterized, that a penalty bit for a selected interrupt input (int_ix) is set, which means that this Inter rupts prevented until others at the interrupt input (int_i) pending interrupts have been processed. 10. The method according to claim 8 or 9, characterized in that all interrupt inputs (int_ix) of the priority decoder ( 10 ) are sampled during a system cycle. 11. The method according to any one of claims 8 to 10, characterized, that an interrupt signal is only selected if for whose interrupt input (int_ix) does not set a penalty bit has been. 12. The method according to any one of claims 8 to 11, characterized, that after selecting and detecting an interrupt on gang (int_i) of a priority decoder (10, Bn, Cn) further In interrupt signals are held until the off selected interrupt was processed. 13. The method according to any one of claims 8 to 12,  characterized, that the interrupt inputs (int_i) of a priority decoder (10, Bn, Cn) who are scanned in order of priority the. 14. The method according to any one of claims 8 to 13, characterized, that set penalty bits are reset if none Interrupt without penalty bit more at the interrupt input (int_i) is applied. 15. The method according to any one of claims 8 to 14, characterized, that a priority decoder (10, Bn, Cn) of a level K one Priority decoder (10, Bn, Cn) of a level K + 1 selecting of an interrupt signal and thereby causes that this its interrupt inputs (int_i) in the next clock cycle evaluates. 16. The method according to any one of claims 8 to 15, characterized, that in a cascaded system of priority de c or the first level (A) an Inter to be sent to the CPU sends the main signal only when all selected Priority decoder of subsequent levels (B, C,...) Their Inter have evaluated rupte inputs (int_i).