CN222126516U - Chip packaging structure, packaging module and electronic equipment - Google Patents

Abstract

The application discloses a chip packaging structure, a packaging module and electronic equipment, which comprise a packaging substrate, a first bare chip and a first decoupling capacitor, wherein the packaging substrate comprises a first hard board part and a soft board part, the first hard board part comprises a plurality of first pins, a plurality of second pins, a plurality of first conductive structures and a plurality of second conductive structures, the soft board part comprises a plurality of third conductive structures, part of the first pins are respectively and electrically connected with the second pins through the first conductive structures, the other part of the first pins are respectively and electrically connected with the second conductive structures, the second conductive structures are respectively and electrically connected with the third conductive structures, and the first decoupling capacitor is arranged on the first hard board part and is electrically connected with power pins in the second pins. Based on the decoupling capacitor, the first hard board part can have enough power pins and areas to set the decoupling capacitor, so that the PDN impedance of the chip packaging structure is reduced, and the integrity of power signals is ensured.

Description

Chip packaging structure, packaging module and electronic equipment

Technical Field

The present application relates to the field of semiconductor packaging technology, and in particular, to a chip packaging structure, a packaging module, and an electronic device.

Background

In order to remove noise coupled to the power pins of the chip package structure and provide a stable power to the chip package structure, it is necessary to provide decoupling capacitors electrically connected to the power pins in the chip package structure. However, as the integration level of the chip package structure is higher, it is difficult for the chip package structure to have a sufficient number of power pins and a sufficient area to set the decoupling capacitor, which results in a larger impedance of the power distribution network (Power Distribution Network, PDN) and affects the integrity of the power signal.

Disclosure of utility model

The application discloses a chip packaging structure, a packaging module and electronic equipment, which are used for reducing impedance of a power distribution network.

The application discloses a chip packaging structure, which comprises a packaging substrate, wherein the packaging substrate comprises a first hard plate part and a soft plate part which are connected, the first hard plate part comprises a plurality of first pins, a plurality of second pins, a plurality of first conductive structures and a plurality of second conductive structures, the soft plate part comprises a plurality of third conductive structures, the plurality of first pins and the plurality of second pins are respectively positioned on two opposite sides of the first hard plate part, the plurality of first conductive structures penetrate through the first hard plate part, one part of the first pins is respectively and electrically connected with the plurality of second pins through the plurality of first conductive structures, the other part of the first pins is respectively and electrically connected with the plurality of second conductive structures, the plurality of second conductive structures are respectively and electrically connected with the plurality of third conductive structures, the other part of the first pins comprises signal pins, the first dies are respectively and electrically connected with the first dies, the first dies are electrically connected with the first power supply decoupling capacitors, and the first decoupling capacitors are arranged on the first dies and the first power supply decoupling capacitors.

Based on this, through making the partial first pin of first hard board portion be connected with the third conductive structure electricity of soft board portion through a plurality of second conductive structures, can reduce the quantity of signal pin in the second pin of first hard board portion, and then can set up enough quantity power pin and first decoupling capacitor electricity in the second pin of first hard board portion and be connected for first hard board portion has sufficient area to set up first decoupling capacitor, and then can reduce the PDN impedance of chip packaging structure, guarantees the integrality of power signal.

In some embodiments, the flexible sheet portion includes a first flexible layer, a conductive layer on a side of the first flexible layer, and a second flexible layer on a side of the conductive layer facing away from the first flexible layer, the conductive layer including the plurality of third conductive structures, the first flexible layer, the conductive layer, and the second flexible layer extending from the first stiff sheet portion to the flexible sheet portion. Based on this, the wiring and pin space can be extended by the soft board portion connected to the first hard board portion.

In some embodiments, the flexible board portion further comprises a first shielding layer and a second shielding layer, wherein the first shielding layer is located on one side of the first flexible layer, which is away from the conductive layer, and the second shielding layer is located on one side of the second flexible layer, which is away from the conductive layer. Based on this, interference of external signals to signals on the flexible board portion can be shielded.

In some embodiments, the materials of the first flexible layer and the second flexible layer include a liquid crystal polymer material or a high frequency flexible electronic material including a polyimide flexible material or a polytetrafluoroethylene material.

In some embodiments, the flexible board portion further includes a plurality of third pins electrically connected with the plurality of third conductive structures, respectively. Based on this, the flexible board portion can be electrically connected to a device such as a connector.

In some embodiments, the chip package structure further includes a second hard board portion, the second hard board portion further includes a plurality of fourth pins and a plurality of fourth conductive structures, the plurality of fourth pins are respectively electrically connected with the plurality of fourth conductive structures, and the plurality of fourth conductive structures are respectively electrically connected with the plurality of third conductive structures. Based on the structure, the soft board part can be electrically connected with another chip packaging structure, so that the wiring and pin space is further expanded.

In some embodiments, the second stiffener portion further includes a plurality of fifth pins and a plurality of fifth conductive structures, the plurality of fifth pins and the plurality of fourth pins being located on opposite sides of the second stiffener portion, respectively, the plurality of fifth pins being electrically connected to the plurality of fourth pins through the plurality of fifth conductive structures that extend through the second stiffener portion, the chip package structure further includes a second die and a second decoupling capacitor, the second die and the second decoupling capacitor being disposed in the second stiffener portion, the second die being electrically connected to the plurality of fifth pins, the second decoupling capacitor being electrically connected to the plurality of fourth pins. Based on this, a plurality of chip interconnect structures can be realized.

In some embodiments, the flex circuit portion leads from a film layer above the core layer of the first stiff circuit portion, or the flex circuit portion leads from a film layer below the core layer of the first stiff circuit portion, or the chip package structure includes a plurality of flex circuit portions that lead from different sides or layers of the first stiff circuit portion.

In a second aspect, the application discloses a packaging module, which comprises a printed circuit board and the chip packaging structure as defined in any one of the above, wherein the chip packaging structure is arranged on one side of the printed circuit board.

In a third aspect, the application discloses an electronic device comprising a packaging module as described above.

Drawings

In order to more clearly describe the embodiments of the present application or the technical solutions in the background art, the following description will describe the drawings that are required to be used in the embodiments of the present application or the background art.

Fig. 1 is a schematic cross-sectional view of a package substrate of a chip package structure.

Fig. 2 is a schematic cross-sectional structure of a chip package structure according to an embodiment of the present application.

Fig. 3 is a schematic plan view of a package substrate according to an embodiment of the present application.

Fig. 4 is a schematic cross-sectional structure of the package substrate shown in fig. 3 along a cutting line AA.

Fig. 5 is a schematic plan view of another package substrate according to an embodiment of the present application.

Fig. 6 is a schematic cross-sectional view of a flexible board portion of another package substrate according to an embodiment of the present application.

Fig. 7 is a schematic cross-sectional view of another package substrate according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

As shown in fig. 1, fig. 1 is a schematic cross-sectional structure of a package substrate of a chip package structure, the package substrate includes a substrate body 10, a plurality of first pins 11 and a plurality of second pins 12, the first pins 11 and the second pins 12 are respectively located at two opposite sides of the substrate body 10, and the first pins 11 and the second pins 12 are electrically connected through wires in a plurality of conductive layers 100 inside the substrate body 10 and vias 101 electrically connected with wires of two adjacent conductive layers 100. Of the plurality of first pins 11 and second pins 12, some of the first pins 11 and second pins 12 are power pins (e.g., white pins in fig. 1), and other first pins 11 and second pins 12 (e.g., dark pins in fig. 1) are signal pins or ground pins.

To remove noise coupled to the power pins of the chip package structure and provide a stable power supply to the chip package structure, decoupling capacitors are typically provided in the chip package structure that are electrically connected to the power pins in the second pins 12. However, as the integration level of the chip package structure is higher, the number of signal pins in the plurality of first pins 11 and the plurality of second pins 12 is higher, and the number of power pins is lower, so that it is difficult for the chip package structure to have a sufficient number of power pins electrically connected with the decoupling capacitor, and the PDN impedance is higher. In addition, as the number of signal pins increases, the total area of signal lines and the total area of power lines of each conductive layer 100 in the substrate main body 10 increase, so that the chip package structure is difficult to have enough area to set the decoupling capacitor, which results in larger PDN impedance and affects the integrity of the power signal.

Although the decoupling capacitor may be embedded by hollowing out the substrate body 10, this may result in a high cost of the chip package structure.

Based on this, the application discloses a chip packaging structure, the packaging substrate comprises a hard board and a soft board, the number of signal pins in the second pins of the hard board is reduced by arranging part of signal pins in the second pins of the hard board on the soft board, the number of power pins in the second pins of the hard board is increased, the area of a region in which decoupling power supplies are arranged in the hard board is increased, and a sufficient number of decoupling capacitors are arranged in a low-cost mode to reduce PDN impedance.

As an alternative implementation of the disclosure, an embodiment of the present application discloses a chip package structure, as shown in fig. 2, fig. 2 is a schematic cross-sectional structure of the chip package structure disclosed in the embodiment of the present application, where the chip package structure includes a package substrate 1, a first die 2, a first decoupling capacitor 3, and so on.

As shown in fig. 3 and fig. 4, fig. 3 is a schematic plan view of a package substrate according to an embodiment of the present application, and fig. 4 is a schematic cross-sectional view of the package substrate shown in fig. 3 along a cutting line AA, where the package substrate 1 includes a first hard plate portion 1a and a soft plate portion 1b connected to each other. The first hard plate portion 1a includes a substrate main body 10, a plurality of first pins 11, a plurality of second pins 12, a plurality of first conductive structures 13, and a plurality of second conductive structures 14. The soft board portion 10b includes a plurality of third conductive structures 15.

The first pins 11 and the second pins 12 are respectively located at two opposite sides of the substrate body 10 of the first hard board portion 1a, the first conductive structures 13 penetrate through the substrate body 10 of the first hard board portion 1a, and a part of the first pins 11 in the first pins 11 are respectively electrically connected with the second pins 12 through the first conductive structures 13. The second conductive structures 14 are located inside the substrate body 10 of the first hard board portion 1a, another part of the first pins 11 is electrically connected to the second conductive structures 14, and the second conductive structures 14 are electrically connected to the third conductive structures 15. Wherein another part of the first pins 11 of the plurality of first pins 11 includes a signal pin.

As shown in fig. 2, the first die 2 is disposed on the first hard plate portion 1a, and the first die 2 is electrically connected to the plurality of first pins 11. Wherein the chip package structure may comprise one or more first dies 2. The first die 2 may be electrically connected to the first device through a portion of the first pins 11, the first conductive structures 13, and the second pins 12, or may be electrically connected to the second device through another portion of the first pins 11, the first conductive structures 14, and the third conductive structures 15, where the first device and the second device may be the same device or different devices. The first device may be a PCB board, etc., and the second device may be a PCB board, a connector, or other package substrate structure, etc.

As shown in fig. 2, the first decoupling capacitor 3 is disposed on the first hard board portion 1a, or the first decoupling capacitor 3 is disposed on a side of the first hard board portion 1a facing away from the first die 2, and the first decoupling capacitor 3 is electrically connected to a power supply pin of the plurality of second pins 12. Of course, in some embodiments, the first decoupling capacitor may be disposed on the side of the first hard board portion 1a having the first die 2, and the first decoupling capacitor may be electrically connected to the power supply pins of the plurality of first pins 11, which is not described herein.

As shown in fig. 4, by making a portion of the first pins 11 of the first hard board portion 1a electrically connected to the plurality of third conductive structures of the soft board portion 1b through the plurality of second conductive structures 14, the number of signal pins in the second pins 12 of the first hard board portion 1a can be reduced, and further, a sufficient number of power pins can be disposed in the second pins 12 of the first hard board portion 1a to be electrically connected to the first decoupling capacitor 3, so that the first hard board portion 1a has a sufficient area to dispose the first decoupling capacitor 3, and further, the PDN impedance of the chip package structure can be reduced, and the integrity of the power signal is ensured. And the manufacturing cost of the chip packaging structure is lower.

And, can realize the space extension to first hard board portion 1a through soft board portion 1b, can make first hard board portion 1a have more spaces to set up more wiring, guarantee the transmission quality of signal, soft board portion 1b also can set up more wiring moreover, guarantee the transmission quality of signal.

The first hard plate portion 1a has a hardness greater than that of the soft plate portion 1b, that is, the first hard plate portion 1a is a hard substrate that is not easily bendable, and the soft plate portion 1b is a flexible substrate that is easily bendable. Furthermore, the first conductive structure 13 and the second conductive structure 14 each comprise a trace and a via. The third conductive structure 15 includes at least a trace.

In some embodiments, the area of the soft board portion 1b is larger than the first hard board portion 1a, so that more first pins 11 are led out from the soft board portion 1 b. Of course, the present application is not limited thereto, and in other embodiments, the area of the soft board portion 1b may be smaller than or equal to the first hard board portion 1a.

In some embodiments of the present application, as shown in fig. 4, the flexible board 1b includes a first flexible layer 101, at least one conductive layer 100 located on one side of the first flexible layer 101, and a second flexible layer 102 located on a side of the at least one conductive layer 100 facing away from the first flexible layer 101. There is also a flexible conductive material between adjacent conductive layers 100. The conductive layer 100 includes a plurality of third conductive structures 15, and the first flexible layer 101, the conductive layer 100, and the second flexible layer 102 extend from the first hard plate portion 1a to the soft plate portion 1b.

Wherein the material of the first flexible layer 101 and the second flexible layer 102 is a flexible dielectric material. In some embodiments, the materials of the first flexible layer 101 and the second flexible layer 102 include liquid crystal polymer (Liquid Crystal Polymer, LCP) materials or high-frequency flexible electronic materials including polyimide flexible materials or polytetrafluoroethylene materials, etc. Since the LCP material becomes liquid crystalline under high temperature conditions and becomes a high molecular polymer dielectric layer having a crystalline orientation under low temperature conditions, it has a low dielectric constant and a low degree of freedom, and can be used for fine circuit fabrication and the like.

Note that, when the first hard plate portion 1a is manufactured, the first flexible layer 101 may be made to replace a part of the dielectric layer in the first hard plate portion 1a and extend to the soft plate portion 1b, and then when the conductive layer 100 is manufactured, the conductive layer 100 may be made to extend from the first hard plate portion 1a to the soft plate portion 1b, and further, the plurality of third conductive structures 15 may be formed by etching the conductive layer 100. The trace width and the pitch of the third conductive structures 15 may be adjusted according to the actual process, for example, the trace width and the pitch are increased to reduce the processing difficulty.

In some embodiments, the soft board portion 1b is led out from the film layer above the core layer of the first hard board portion 1a, so that crosstalk of signals at larger vias of the core layer can be reduced, wiring and vias on signal paths can be reduced, and signal transmission quality can be improved. In other embodiments, the soft board portion 1b is led out from the film layer below the core layer of the first hard board portion 1a, and although crosstalk of signals at larger vias of the core layer cannot be reduced, routing and vias on the signal path can be reduced, so as to improve signal transmission quality. Based on this, a signal (e.g., PCIE signal or DDR signal) having a high quality requirement can be led out from the flexible board portion 1 b.

In other embodiments, as shown in fig. 5, fig. 5 is a schematic plan view of another package substrate according to an embodiment of the present application, the chip package structure may include a plurality of soft board portions 1b, and the plurality of soft board portions 1b may be led out from different sides or different layers of the first hard board portion 1 a.

In some embodiments of the present application, as shown in fig. 6, fig. 6 is a schematic cross-sectional structure of a flexible board portion of another package substrate disclosed in the embodiment of the present application, where the flexible board portion 1b further includes a first shielding layer 103 and a second shielding layer 104, the first shielding layer 103 is located on a side of the first flexible layer 101 facing away from the conductive layer 100, and the second shielding layer 104 is located on a side of the second flexible layer 102 facing away from the conductive layer 100, so as to shield interference of external signals on signals in the third conductive structure 15. Of course, the outer sides of the first shielding layer 103 and the second shielding layer 104 may also have an insulating film or the like, which is not described herein.

In some embodiments, the first shielding layer 103 and the second shielding layer 104 may be a mesh-like structure. The material of the first shielding layer 103 and the second shielding layer 104 may be metal or the like. Of course, the application is not limited thereto, and in other embodiments, the shielding effect may be achieved by using a ground layer instead of the shielding layer.

In some embodiments of the present application, as shown in fig. 4, the flexible board portion 1b further includes a plurality of third pins 16, and the plurality of third pins 16 are electrically connected to the plurality of third conductive structures 15, so that the flexible board portion 1b is electrically connected to a PCB board or the like through the plurality of third pins 16.

Of course, the present application is not limited thereto, and in other embodiments, as shown in fig. 7, fig. 7 is a schematic cross-sectional structure of another package substrate according to an embodiment of the present application, the chip package structure further includes a second hard board portion 1c, the second hard board portion 1c further includes a plurality of fourth pins 17 and a plurality of fourth conductive structures 18, the plurality of fourth pins 17 are electrically connected to the plurality of fourth conductive structures 18, and the plurality of fourth conductive structures 18 are electrically connected to the plurality of third conductive structures 15.

On the basis, in some embodiments, the second hard board portion 1c further includes a plurality of fifth pins 19 and a plurality of fifth conductive structures 20, where the plurality of fifth pins 19 and the plurality of fourth pins 17 are respectively located on opposite sides of the substrate body of the second hard board portion 1c, and the plurality of fifth pins 19 are electrically connected to the plurality of fourth pins 17 through the plurality of fifth conductive structures 20 penetrating through the substrate body of the second hard board portion 1 c. The chip package structure further includes a second die and a second decoupling capacitor, where the second die and the second decoupling capacitor are disposed on the second hard board portion 1c, the second die is electrically connected to the plurality of fifth pins 19, and the second decoupling capacitor is electrically connected to the plurality of fourth pins 17. Based on this, a plurality of chip interconnect structures can be realized.

It can be appreciated that in some embodiments of the present application, the chip package structure may include a plurality of second dies, a plurality of second decoupling capacitors and a plurality of second hard board portions 1c, where the plurality of second dies and the plurality of second decoupling capacitors are respectively disposed on the plurality of second hard board portions 1c, and the plurality of second hard board portions 1c are connected to different sides of the soft board portion 1 b.

As another optional implementation of the disclosure, an embodiment of the present application further discloses a packaging module, including a printed circuit board and the chip packaging structure disclosed in any one of the above embodiments, where the chip packaging structure is disposed on one side of the printed circuit board.

As another optional implementation of the disclosure, an embodiment of the present application further discloses an electronic device, including the package module disclosed in any one of the embodiments above. The electronic device can be a smart phone or a tablet computer.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples only represent a few embodiments of the present specification, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the present description, which is within the scope of the present description. Accordingly, the protection scope of the patent should be determined by the appended claims.

Claims (10)

1. A chip package structure, comprising:

The packaging substrate comprises a first hard plate part and a soft plate part which are connected, wherein the first hard plate part comprises a plurality of first pins, a plurality of second pins, a plurality of first conductive structures and a plurality of second conductive structures, the soft plate part comprises a plurality of third conductive structures, the plurality of first pins and the plurality of second pins are respectively positioned at two opposite sides of the first hard plate part, the plurality of first conductive structures penetrate through the first hard plate part, one part of the first pins is respectively and electrically connected with the plurality of second pins through the plurality of first conductive structures, and the other part of the first pins is respectively and electrically connected with the plurality of second conductive structures, and the plurality of second conductive structures are respectively and electrically connected with the plurality of third conductive structures;

A first die disposed on the first stiffener portion, the first die being electrically connected to the plurality of first pins;

The first decoupling capacitor is arranged on the first hard plate part and is electrically connected with the power supply pins of the plurality of second pins.

2. The chip package structure according to claim 1, wherein the flexible board portion includes a first flexible layer, a conductive layer located on a side of the first flexible layer, and a second flexible layer located on a side of the conductive layer facing away from the first flexible layer;

The conductive layer includes the plurality of third conductive structures, and the first flexible layer, the conductive layer, and the second flexible layer extend from the first hard plate portion to the soft plate portion.

3. The chip package structure according to claim 2, wherein the flexible board portion further includes a first shielding layer and a second shielding layer;

The first shielding layer is positioned on one side of the first flexible layer, which is away from the conductive layer, and the second shielding layer is positioned on one side of the second flexible layer, which is away from the conductive layer.

4. The chip package structure according to claim 2, wherein the materials of the first flexible layer and the second flexible layer include a liquid crystal polymer material or a high-frequency flexible electronic material including a polyimide flexible material or a polytetrafluoroethylene material.

5. The chip package structure according to any one of claims 1 to 4, wherein the flexible board further includes a plurality of third pins, and the plurality of third pins are electrically connected to the plurality of third conductive structures, respectively.

6. The chip package structure according to any one of claims 1 to 4, wherein the chip package structure further comprises a second hard board portion, the second hard board portion further comprises a plurality of fourth pins and a plurality of fourth conductive structures, the plurality of fourth pins are electrically connected with the plurality of fourth conductive structures respectively, and the plurality of fourth conductive structures are electrically connected with the plurality of third conductive structures respectively.

7. The chip package structure of claim 6, wherein the second stiffener portion further comprises a plurality of fifth pins and a plurality of fifth conductive structures, the plurality of fifth pins and the plurality of fourth pins being located on opposite sides of the second stiffener portion, respectively, the plurality of fifth pins being electrically connected to the plurality of fourth pins through the plurality of fifth conductive structures extending through the second stiffener portion;

The chip packaging structure further comprises a second bare chip and a second decoupling capacitor, the second bare chip and the second decoupling capacitor are arranged on the second hard board part, the second bare chip is electrically connected with the fifth pins, and the second decoupling capacitor is electrically connected with the fourth pins.

8. The chip package structure according to claim 1, wherein the soft board portion is led out from a film layer above a core layer of the first hard board portion, or the soft board portion is led out from a film layer below a core layer of the first hard board portion, or the chip package structure includes a plurality of soft board portions led out from different sides or different layers of the first hard board portion.

9. A packaging module, comprising a printed circuit board and the chip packaging structure of any one of claims 1-8, wherein the chip packaging structure is disposed on one side of the printed circuit board.

10. An electronic device comprising the encapsulation module of claim 9.