CN221926931U

CN221926931U - Overlay mark

Info

Publication number: CN221926931U
Application number: CN202420283507.1U
Authority: CN
Inventors: 曾炜炜; 叶峻玮
Original assignee: Nexchip Semiconductor Corp
Current assignee: Nexchip Semiconductor Corp
Priority date: 2024-02-06
Filing date: 2024-02-06
Publication date: 2024-10-29
Anticipated expiration: 2034-02-06

Abstract

The utility model provides an overlay mark, comprising: the first mark groups and the second mark groups form a central symmetrical graph, the first mark groups comprise a plurality of strip-shaped first marks, the first marks comprise a plurality of partially overlapped first sub marks and second sub marks, the first sub marks are positioned in a first material layer, the second sub marks are positioned in a second material layer, and the size of a graph formed by projecting adjacent first sub marks and adjacent second sub marks on a wafer is the same as the characteristic size of a chip area graph; the second mark groups are positioned on the inner sides of the first mark groups and in the third material layer, and one second mark group is positioned between two adjacent first mark groups; the utility model can improve the accuracy of the overlay error monitoring of the chip area and improve the grinding damage of the overlay mark.

Description

Overlay mark

Technical Field

The utility model relates to the technical field of semiconductors, in particular to an overlay mark.

Background

Photolithography is a key step in the manufacture of semiconductor integrated circuits, and the overlay accuracy (overlay) of photolithography is one of the key parameters for measuring the overlay accuracy, which refers to the offset between the upper and lower patterns of a wafer, i.e., the overlay error, and is usually measured by measuring the offset between the upper and lower overlay marks.

At present, after polysilicon is deposited on a wafer, a plurality of strip patterns are formed along a first direction by using a photolithography process and an etching process, and then the plurality of strip patterns are cut along a second direction by using the photolithography process and the etching process, wherein the first direction and the second direction intersect (are generally vertical) on a plane, and finally the needed polysilicon pattern is formed. The process of defining a polysilicon pattern by two photomasks is that a plurality of strip patterns formed by a photoetching process and an etching process which are executed along a first direction are first layer patterns, a polysilicon pattern formed by a photoetching process and an etching process which are executed along a second direction is second layer patterns, and the overlay error between the two layers of patterns has an influence on a rear layer pattern, so that the overlay error between the two layers of patterns needs to be considered when the overlay error of the rear layer is monitored, but the overlay mark of the rear layer is only aimed at forming one layer (generally aimed at the first layer pattern) of the polysilicon pattern at present, so that the overlay error of a chip area cannot be accurately monitored.

Fig. 1 is a schematic diagram of an overlay mark in the prior art. Referring to fig. 1, the overlay mark includes a plurality of first mark groups 10 and a plurality of second mark groups 20, the first mark groups 10 are located in the first material layer, the second mark groups 20 are located in the second material layer, the plurality of first mark groups 10 are central symmetry patterns, the plurality of second mark groups 20 are central symmetry patterns, the centers of symmetry of the plurality of first mark groups 10 and the plurality of second mark groups 20 coincide, the plurality of first mark groups 10 are located at the outer sides of the plurality of second mark groups 20, the first mark groups include a plurality of first marks 12, the first marks 12 are in a strip shape, wherein the first mark groups 10 are equivalent to the overlay marks (a plurality of strip patterns) of the first layer patterns, the second mark groups 20 are overlay marks of the back layer patterns, the overlay accuracy is evaluated by using the overlay errors of the overlay marks (the first mark groups 10) of the first layer patterns and the overlay marks (the second mark groups 20) of the back layer patterns, and the overlay errors of the second layer patterns are ignored, so that the overlay errors of the chip area cannot be accurately monitored; and such overlay marks in fig. 1 may cause polishing damage to the overlay marks of the back layer pattern during the polishing process.

Disclosure of utility model

The utility model aims to provide an overlay mark, which improves the accuracy of overlay error monitoring of a chip area and improves the grinding damage of the overlay mark.

In order to achieve the above object, the present utility model provides an overlay mark comprising:

The first mark groups comprise a plurality of strip-shaped first marks, the first marks comprise a plurality of partially overlapped first sub-marks and second sub-marks, the first sub-marks are positioned in a first material layer, the second sub-marks are positioned in a second material layer, and the sizes of patterns formed by projecting adjacent first sub-marks and adjacent second sub-marks on a wafer are the same as the characteristic sizes of patterns of a chip area;

And the second mark groups form a central symmetrical graph, the second mark groups are positioned on the inner sides of the first mark groups and in the third material layer, and one second mark group is positioned between two adjacent first mark groups.

Optionally, the first sub-mark and the second sub-mark are both in a strip shape.

Optionally, the plurality of first sub-marks are arranged along an X direction and extend along a Y direction, and the plurality of second sub-marks are arranged along the Y direction and extend along the X direction, wherein the X direction and the Y direction intersect.

Optionally, the extending directions of the first marks in the adjacent two first mark groups are different.

Optionally, the extension length of a first sub-mark in the first mark extending along the X direction is smaller than the extension length of a first sub-mark in the first mark extending along the Y direction, and the extension length of a second sub-mark in the first mark extending along the X direction is larger than the extension length of a second sub-mark in the first mark extending along the Y direction.

Optionally, the distance between two adjacent first sub-marks is the characteristic dimension of the chip area pattern along the Y direction, and the distance between two adjacent second sub-marks is the characteristic dimension of the chip area pattern along the X direction, so that the dimension of the pattern formed by projecting the adjacent first sub-marks and the adjacent second sub-marks on the wafer is the same as the characteristic dimension of the chip area pattern.

Optionally, the second sub-mark is located on the first sub-mark.

Optionally, the chip region pattern is a polysilicon pattern.

Optionally, the second mark group includes a plurality of strip-shaped second marks, and the extending directions of the second marks in two adjacent second mark groups are different.

Optionally, the number of the first marks in the plurality of first mark groups is the same, and the distance between two adjacent first marks in each first mark group is the same; the number of the second marks in the plurality of second mark groups is the same, and the spacing between two adjacent second marks in each second mark group is the same.

The overlay mark provided by the utility model comprises: the first mark groups and the second mark groups form a central symmetrical graph, the first mark groups comprise a plurality of strip-shaped first marks, the first marks comprise a plurality of partially overlapped first sub marks and second sub marks, the first sub marks are positioned in a first material layer, the second sub marks are positioned in a second material layer, and the size of a graph formed by projecting adjacent first sub marks and adjacent second sub marks on a wafer is the same as the characteristic size of a chip area graph; the second mark groups are positioned on the inner sides of the first mark groups and in the third material layer, and one second mark group is positioned between two adjacent first mark groups. According to the utility model, the first mark is set to be a first sub mark and a second sub mark which are partially overlapped, the size of a pattern formed by projecting the adjacent first sub mark and the adjacent second sub mark on the wafer is the same as the characteristic size of the pattern of the chip area, the unexpected technical effect can accurately obtain the real overlay error of the chip area, the overlay error monitoring accuracy of the chip area is improved, and when the single-layer overlay error generates deviation, the first sub mark or the second sub mark can be directly monitored; and the lapping damage of the overlay mark can be improved when the lapping process is performed.

Drawings

Fig. 1 is a schematic diagram of an overlay mark in the prior art.

Fig. 2 is a schematic diagram of an overlay mark according to an embodiment of the utility model.

Fig. 3 is a schematic diagram of a first mark extending along an X direction in an overlay mark according to an embodiment of the utility model.

Fig. 4 is a schematic diagram of a first mark extending along a Y direction in an overlay mark according to an embodiment of the utility model.

Fig. 5 is a schematic diagram of a chip area pattern corresponding to an overlay mark according to an embodiment of the utility model.

Wherein, the reference numerals are as follows:

10. 100-a first set of markers; 12. 120-first mark; 20. 200-a second set of markers; 22. 220-a second marker; 121-first sub-label; 122-second sub-tag; 300-chip area pattern.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

In the description of the present application, it should be understood that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," and the like indicate orientations or positional relationships based on those shown in the drawings, or those conventionally put in place when the product of the application is used, or those conventionally understood by those skilled in the art, merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element to be referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.

Furthermore, relational terms such as "first" and "second," and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or device comprising the element. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.

Fig. 2 is a schematic diagram of an overlay mark provided in this embodiment, fig. 3 is a schematic diagram of a first mark extending along an X direction in the overlay mark provided in this embodiment, and fig. 4 is a schematic diagram of a first mark extending along a Y direction in the overlay mark provided in this embodiment. Referring to fig. 2, an objective of the present utility model is to provide an overlay mark, which includes a plurality of first mark groups 100 and a plurality of second mark groups 200, wherein the plurality of first mark groups 100 and the plurality of second mark groups 200 form a central symmetrical pattern, the symmetrical centers of the plurality of first mark groups 100 and the plurality of second mark groups 200 coincide, the plurality of second mark groups 200 are located inside the plurality of first mark groups 100, and one second mark group 200 is located between two adjacent first mark groups 100; the extending directions of the adjacent two first mark groups 100 are different (one X direction, one Y direction, the X direction and the Y direction intersect, preferably the X direction and the Y direction intersect perpendicularly), and the extending directions of the adjacent second mark groups 200 are different (one X direction, one Y direction). In the present embodiment, the number of the first marker set 100 and the second marker set 200 is preferably 4 as shown in fig. 2, but is not limited thereto; the 4 first marker sets 100 form a central symmetrical pattern, the 4 second marker sets 200 also form a central symmetrical pattern, and the 4 second marker sets 200 are located inside the 4 first marker sets 100.

Each first set of marks 100 includes a plurality of first marks 120 in a stripe shape, and each second set of marks 200 includes a plurality of second marks 220 in a stripe shape. In this embodiment, the pitches of two adjacent first marks 120 in the plurality of first mark groups 100 are preferably the same, the pitches of two adjacent second marks 220 in the plurality of second mark groups 200 are preferably the same, and the pitches of two adjacent first marks 120 in the first mark groups 100 and the pitches of two adjacent second marks 220 in the second mark groups 200 are the same or different; the number of first marks 120 in the plurality of first mark groups 100 is preferably the same, and the number of second marks 220 in the plurality of second mark groups 200 is preferably the same, and the number of first marks 120 in the first mark groups 100 and the number of second marks 220 in the second mark groups 200 are the same or different, but are not limited thereto. The extending directions of the first marks 120 in the adjacent two first mark groups 100 are different (one X direction, one Y direction), and the extending directions of the second marks 220 in the adjacent two second mark groups 200 are different (one X direction, one Y direction).

Referring to fig. 3 and fig. 4, the first mark 120 includes a plurality of first sub-marks 121 and second sub-marks 122 that partially overlap, the size of a pattern enclosed by the adjacent first sub-marks 121 and the adjacent second sub-marks 122 projected on the wafer is the same as the feature size of a pattern enclosed by the adjacent first sub-marks 121 and the adjacent second sub-marks 122, in this embodiment, the overlay mark is disposed on the wafer and located in a scribe line region of the wafer, and since the first sub-marks 121 and the second sub-marks 122 are stripe-shaped and intersect in the extending direction, and the first sub-marks 121 and the second sub-marks 122 partially overlap, a pattern is enclosed between the projections of the adjacent first sub-marks 121 and the adjacent second sub-marks 122 on the wafer (for example, the feature size is the specific size of a pattern enclosed by the adjacent first sub-marks 121 and the adjacent second sub-marks 122 projected on the wafer when seen from the plane of fig. 3 and fig. 4). In this embodiment, the first sub-mark 121 and the second sub-mark 122 are each preferably in a stripe shape, and the plurality of first sub-marks 121 are arranged along the X direction and extend along the Y direction, and the plurality of second sub-marks 122 are arranged along the Y direction and extend along the X direction, wherein the X direction and the Y direction perpendicularly intersect. The second sub-marks 122 are located on the first sub-marks 121, and the adjacent two first sub-marks 121 and the adjacent two second sub-marks 122 have a pitch such that the first sub-marks 121 and the second sub-marks 122 overlap one another. Wherein fig. 3 shows one first mark 120 of the first mark group 100 extending in the Y direction, and fig. 4 shows one first mark 120 of the first mark group 100 extending in the X direction.

Fig. 5 is a schematic diagram of a chip area pattern corresponding to an overlay mark according to the present embodiment. Referring to fig. 5, in the present embodiment, the pitch of two adjacent first sub-marks 121 is the feature size of the chip region pattern 300 along the Y direction, and the pitch of two adjacent second sub-marks 122 is the feature size of the chip region pattern 300 along the X direction, so that the size of the pattern surrounded by the adjacent first sub-marks 121 and the adjacent second sub-marks 122 projected on the wafer is the same as the feature size of the chip region pattern 300 (for clarity, the chip region pattern in fig. 5 is enlarged adaptively, and the size of the pattern S in fig. 3 and 4 is different). In this embodiment, the chip region pattern 300 is a polysilicon pattern, two photomasks are required to define the polysilicon pattern when the polysilicon pattern is formed, and then the overlay error caused by the two photomasks is required to be considered, the first mark 120 includes a plurality of partially overlapped first sub-marks 121 and second sub-marks 122, and the projected pattern formed between the adjacent first sub-marks 121 and the adjacent second sub-marks 122 is the same as the feature size of the chip region pattern 300, so that the overlay error caused by the two photomasks (the first sub-marks 121 and the second sub-marks 122 reflect the overlay error caused by the two photomasks) can be well reflected; and the feature size of the projection pattern formed between the adjacent first sub-mark 121 and the adjacent second sub-mark 122 is the same as that of the chip region pattern 300, so that the grinding damage of the grinding process to the overlay mark can be improved.

In the present embodiment, the extension length of the first sub-mark 121 in the first mark 120 extending in the X direction (refer to fig. 3) is smaller than the extension length of the first sub-mark 121 in the first mark 120 extending in the Y direction (refer to fig. 4), and the extension length of the second sub-mark 122 in the first mark 120 extending in the X direction (refer to fig. 3) is larger than the extension length of the second sub-mark 122 in the first mark 120 extending in the Y direction (refer to fig. 4).

In this embodiment, the first sub-mark 121 is located in the first material layer, the second sub-mark 122 is located in the second material layer, and the second mark group 200 is located in the third material layer, where the first material layer, the second material layer, and the third material layer may be stacked from bottom to top, that is, the first sub-mark 121 and the second sub-mark 122 form an overlay mark of a front layer pattern, the second mark group 200 is an overlay mark of a rear layer pattern, the front layer pattern may be a polysilicon pattern as described above, and the rear layer pattern may be an interconnection pattern.

In summary, the overlay mark provided in the present utility model includes: the first mark groups and the second mark groups form a central symmetrical graph, the first mark groups comprise a plurality of strip-shaped first marks, the first marks comprise a plurality of partially overlapped first sub marks and second sub marks, the first sub marks are positioned in a first material layer, the second sub marks are positioned in a second material layer, and the size of a graph formed by projecting adjacent first sub marks and adjacent second sub marks on a wafer is the same as the characteristic size of a chip area graph; the second mark groups are positioned on the inner sides of the first mark groups and in the third material layer, and one second mark group is positioned between two adjacent first mark groups. According to the utility model, the first mark is set to be a first sub mark and a second sub mark which are partially overlapped, the size of a pattern formed by projecting the adjacent first sub mark and the adjacent second sub mark on the wafer is the same as the characteristic size of the pattern of the chip area, the unexpected technical effect can accurately obtain the real overlay error of the chip area, the overlay error monitoring accuracy of the chip area is improved, and when the single-layer overlay error generates deviation, the first sub mark or the second sub mark can be directly monitored; and the lapping damage of the overlay mark can be improved when the lapping process is performed.

The foregoing is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the utility model without departing from the scope of the technical solution of the utility model, and the technical solution of the utility model is not departing from the scope of the utility model.

Claims

1. An overlay mark is provided, which is a mark, characterized by comprising the following steps:

2. The overlay mark of claim 1, wherein the first sub-mark and the second sub-mark are each in the form of a bar.

3. The overlay mark of claim 2, wherein a plurality of the first sub-marks are aligned in an X-direction and extend in a Y-direction, and a plurality of the second sub-marks are aligned in a Y-direction and extend in an X-direction, wherein the X-direction and the Y-direction intersect.

4. The overlay mark of claim 3, wherein the first marks in adjacent two of the first mark sets have different directions of extension.

5. The overlay mark of claim 4, wherein an extension length of a first sub-mark in the first mark extending in the X-direction is less than an extension length of a first sub-mark in the first mark extending in the Y-direction, and an extension length of a second sub-mark in the first mark extending in the X-direction is greater than an extension length of a second sub-mark in the first mark extending in the Y-direction.

6. The overlay mark of claim 2, wherein a pitch of two adjacent first sub-marks is a feature size of the chip region pattern along the Y direction, and a pitch of two adjacent second sub-marks is a feature size of the chip region pattern along the X direction, such that a size of a pattern enclosed by the projection of the adjacent first sub-marks and the adjacent second sub-marks on the wafer is the same as the feature size of the chip region pattern.

7. The overlay mark of claim 1, wherein the second sub-mark is located on the first sub-mark.

8. The overlay mark of claim 1, wherein the chip region pattern is a polysilicon pattern.

9. The overlay mark of claim 1, wherein the second mark set comprises a plurality of stripe-shaped second marks, and wherein the second marks in adjacent two second mark sets have different extending directions.

10. The overlay mark of claim 9, wherein the number of first marks in a plurality of first mark sets is the same, and the pitch of two adjacent first marks in each first mark set is the same; the number of the second marks in the plurality of second mark groups is the same, and the spacing between two adjacent second marks in each second mark group is the same.