CN221261233U - Signal processing circuit, ultrasonic signal processing chip, and ultrasonic radar apparatus - Google Patents

Abstract

The application provides a signal processing circuit, an ultrasonic signal processing chip and an automobile ultrasonic radar device, wherein the circuit comprises: a driving circuit for outputting a driving signal; the echo signal processing circuit is used for receiving the signal to be processed and outputting an envelope curve; a threshold generation circuit for outputting an envelope curve threshold; the threshold comparison circuit is used for receiving the envelope curve and the envelope curve threshold value, comparing the envelope curve with the envelope curve threshold value and outputting a threshold comparison result; the output logic circuit is used for receiving the threshold comparison result and outputting I O logic states based on the threshold comparison result; and the timing circuit is used for receiving the driving signal and enabling the output logic circuit to output a I O logic state which is inverted according to the driving signal and the timing duration.

Description

Signal processing circuit, ultrasonic signal processing chip, and ultrasonic radar apparatus

Technical Field

The application relates to the technical field of electronics, in particular to a signal processing circuit, an ultrasonic signal processing chip and an automobile ultrasonic radar device.

Background

With the continuous development of technology, ultrasonic waves have been widely used in various fields, and because ultrasonic waves have strong directivity, slow energy consumption, and long distance of propagation in a medium, ultrasonic waves are often used for distance measurement. Typically, an ultrasonic ranging system includes an ultrasonic transmitter and an ultrasonic receiver, which are constructed as separate individual components, through which an ultrasonic signal is transmitted, and through which an echo signal is detected, the measurement of distance can be achieved. Ultrasonic radar is one of the most common sensors in automobiles. The distance is measured and calculated by transmitting ultrasonic waves through a reflective ultrasonic device and receiving returned reflected waves. In short-range measurement, the ultrasonic ranging sensor has great advantages and is used in reversing radar.

The ultrasonic sensor excites an oscillating unit of the ultrasonic sensor to oscillate by an oscillating signal. However, after the oscillation signal ends, the oscillation unit cannot stop oscillating immediately, that is, there is a residual shock after the oscillation signal ends, which may cause the echo signal to be not reliably detected, making it difficult for the ultrasonic sensor to measure in the vicinity, and a large blind area is generated. Especially when the distance is very close, how to make the ultrasonic sensor prepare for detecting echo in advance reduces the detection blind area so as to be applied to various scenes, and the problem which needs to be solved urgently at present.

It should be noted that the information disclosed in the background section of the present application is only for enhancement of understanding of the general background of the present application and should not be taken as an admission or any form of suggestion that this information forms the prior art that is well known to a person skilled in the art.

Disclosure of utility model

In view of the above, the present application provides a signal processing circuit, an ultrasonic signal processing chip and an automotive ultrasonic radar device, so as to solve the problem that in the prior art, an ultrasonic sensor is difficult to measure a distance in a neighboring area, and a large blind area is generated.

In a first aspect, an embodiment of the present application provides a signal processing circuit, including:

The output end of the driving circuit is used for outputting a driving signal; and

The input end of the echo signal processing circuit is used for receiving a signal to be processed, and the output end of the echo signal processing circuit is used for outputting an envelope curve; and

The output end of the threshold generating circuit is used for outputting an envelope curve threshold; and

A first input end of the threshold comparison circuit is electrically connected with an output end of the echo signal processing circuit to receive the envelope curve, a second input end of the threshold comparison circuit is electrically connected with an output end of the threshold generation circuit to receive the envelope curve threshold, and the threshold comparison circuit is used for comparing the envelope curve with the envelope curve threshold and outputting a threshold comparison result; and

The input end of the output logic circuit is electrically connected with the output end of the threshold comparison circuit, and the output end of the output logic circuit is used for outputting IO logic states; and

The input end of the timing circuit is electrically connected with the output end of the driving circuit, the output end of the timing circuit is electrically connected with the input end of the output logic circuit, and the timing circuit is used for enabling the output logic circuit to output an inverted IO logic state according to the driving signal and timing duration.

In one possible implementation manner, the timing circuit is configured to enable the output logic circuit to flip the output IO logic state according to the driving signal and the timing duration, where the method includes:

The timing circuit is used for starting to count a first timing duration according to the driving signal, outputting a first signal after the first timing duration is finished, starting to count a second timing duration, and outputting a second signal after the second timing duration is finished, wherein the first signal is used for controlling the output logic circuit to start outputting the inverted IO logic state, and the second signal is used for controlling the output logic circuit to stop outputting the inverted IO logic state, and the first timing duration and the second timing duration are continuous two periods of time.

In one possible implementation, the signal to be processed includes: the device comprises a driving stage, an oscillating stage and a receiving stage, wherein the end point of the oscillating stage is a first time point, and the first time point is the time point when the second timing starts; the timing circuit may start the first timing at a driving stage start time point or a number of periods after a driving stage start time point or an oscillation stage start time point or a number of periods after an oscillation stage start.

In one possible implementation manner, the signal processing circuit further includes a starting device, an input end of the starting device is electrically connected with an output end of the driving circuit, an output end of the starting device is electrically connected with an input end of the timing circuit, and the starting device is used for sending a starting signal to the timing circuit within a preset time period according to a driving signal, so that the timing circuit starts first timing.

In a possible implementation manner, the signal processing circuit further includes a configuration circuit, an output end of the configuration circuit is electrically connected to an input end of the timing circuit, and the configuration circuit is used for configuring a first timing duration and a second timing duration of the timing circuit.

In one possible implementation manner, the input end of the configuration circuit is electrically connected with the ECU, and the configuration circuit is used for configuring the first timing duration and the second timing duration of the timing circuit according to the configuration signal transmitted by the ECU.

In one possible implementation, the driving circuit includes a parameter configuration module, where the parameter configuration module is configured to configure a first timing duration and a second timing duration of the timing circuit.

In one possible implementation, the echo signal processing circuit includes:

The input end of the front-end circuit is used for receiving a signal to be processed, and the output end of the front-end circuit is used for outputting a sampling signal;

And the input end of the envelope processing circuit is electrically connected with the output end of the front-end circuit, and the output end of the envelope processing circuit is used for outputting an envelope curve.

In a second aspect, an embodiment of the present application provides an ultrasonic signal processing chip for electrically connecting with an ultrasonic transducer, including:

The signal processing circuit of any one of the first aspects;

The output end of the driving circuit is electrically connected with the ultrasonic transducer so as to drive the ultrasonic transducer to generate ultrasonic waves, and the input end of the echo signal processing circuit is electrically connected with the ultrasonic transducer so as to receive signals to be processed, which are input by the ultrasonic transducer.

In a third aspect, an embodiment of the present application provides an ultrasonic radar apparatus for an automobile, including:

The chip of the second aspect;

The ultrasonic transducer is electrically connected with the chip and is used for receiving a driving signal output by the chip to generate an ultrasonic signal, and the ultrasonic transducer is used for sending a signal to be processed to the chip and is used as a transmitting transducer and a receiving transducer;

and the ECU is electrically connected with the chip and is used for starting the chip and receiving the IO logic state output by the chip.

Compared with the prior art, the embodiment of the application judges the timing of the oscillation end through the timing circuit, thereby controlling the timing of IO overturning and recovering through the output logic circuit, having simple control logic, being capable of preparing for detecting echo signals in advance during short-distance detection, effectively detecting short-distance echoes and effectively shortening the dead zone distance.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic view of an application scenario provided in an embodiment of the present application;

Fig. 2A and fig. 2B are schematic diagrams illustrating a ranging principle of an ultrasonic system according to an embodiment of the present application;

FIG. 3 is a schematic diagram of signal processing without an obstacle in the blind zone in the prior art;

FIG. 4 is a schematic diagram of signal processing for a blind zone with an obstacle in the prior art;

FIG. 5 is a schematic diagram of a distance measurement principle of another ultrasonic system according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a distance measurement principle of another ultrasonic system according to an embodiment of the present application;

FIG. 7 is a schematic diagram of threshold comparison according to an embodiment of the present application;

Fig. 8 is a schematic diagram of signal processing without an obstacle in a blind area according to an embodiment of the present application;

fig. 9 is a schematic diagram of signal processing with an obstacle in a blind area according to an embodiment of the present application;

fig. 10 is a schematic diagram of a distance measurement principle of another ultrasonic system according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a distance measurement principle of another ultrasonic system according to an embodiment of the present application;

Fig. 12 is a schematic diagram of a distance measurement principle of another ultrasonic system according to an embodiment of the present application;

fig. 13 is a schematic diagram of signal processing with an obstacle in another blind area according to an embodiment of the present application;

fig. 14 is a schematic diagram of signal processing according to an embodiment of the present application;

FIG. 15 is a schematic diagram of another signal processing according to an embodiment of the present application;

fig. 16 is a schematic structural diagram of an ultrasonic signal processing chip according to an embodiment of the present application;

fig. 17 is a schematic structural diagram of an ultrasonic radar device for an automobile according to an embodiment of the present application.

Detailed Description

For a better understanding of the technical solution of the present application, the following detailed description of the embodiments of the present application refers to the accompanying drawings.

It should be understood that the described embodiments are merely some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one way of describing an association of associated objects, meaning that there may be three relationships, e.g., a and/or b, which may represent: the first and second cases exist separately, and the first and second cases exist separately. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

Referring to fig. 1, a schematic view of an application scenario is provided in an embodiment of the present application. In fig. 1, a vehicle 100 and an obstacle 200 are shown, wherein a plurality of ultrasonic transducers 101 are provided at the tail of the vehicle 100, when a user (possibly in the case of automatic driving) controls the vehicle 100 to reverse (possibly in any scene of lateral parking and front obstacle recognition), the ultrasonic transducers 101 can transmit ultrasonic waves and receive echo signals (the ultrasonic transducers can be two independent devices comprising an ultrasonic transmitting transducer and an ultrasonic receiving transducer or can be one device with functions of transmitting ultrasonic waves and receiving ultrasonic waves), and further the distance between the ultrasonic transducers 101 (i.e. the vehicle 100) and the obstacle 200 can be calculated, and corresponding prompt information (for example, warning sound is output through a buzzer or the obstacle distance is displayed through a display screen) can be provided for the user to assist the safe driving.

It should be noted that fig. 1 is only one possible application scenario listed in the embodiment of the present application, and should not be taken as a limitation on the protection scope of the present application. For example, the ultrasonic ranging may be applied to an application scene such as industrial automation control and construction engineering survey in addition to the detection of an obstacle by a vehicle, and in other application scenes, the obstacle may be referred to as a "detected object"; the ultrasonic transducer may be provided at a side portion or a front portion of the vehicle in addition to the rear portion of the vehicle to detect an obstacle at the side portion or the front portion of the vehicle; in addition to 4 ultrasonic transducers, a greater or lesser number of ultrasonic transducers or the like may be provided, and the embodiment of the present application is not particularly limited.

Referring to fig. 2A and fig. 2B, schematic diagrams of ranging principle of an ultrasonic system according to an embodiment of the present application are provided. As shown in fig. 2A and 2B, the ultrasonic system includes an electric control unit (Electronic Control Unit, ECU), an ultrasonic transducer chip, and an ultrasonic transducer, wherein the ultrasonic transducer chip includes a signal processing circuit. The ECU is in communication connection with the signal processing circuit, the output end of the signal processing circuit is electrically connected with the input end of the ultrasonic transducer, and the output end of the ultrasonic transducer is electrically connected with the input end of the signal processing circuit.

Specifically, in the ultrasonic system shown in fig. 2A, the input end and the output end of the ultrasonic transducer are provided, respectively. As shown in fig. 2A, two ports below the ultrasonic transducer are electrically connected as input terminals to the output terminals of the signal processing circuit, and two ports above the ultrasonic transducer are electrically connected as output terminals to the input terminals of the signal processing circuit. In the ultrasound system shown in fig. 2B, the same set of ports is used as both the input and output of the ultrasound transducer. As shown in fig. 2B, two ports below the ultrasonic transducer may be electrically connected as an input to an output of the signal processing circuit, and may be electrically connected as an output to an input of the signal processing circuit. It should be noted that the inclusion of two ports at the input and/or output of the ultrasound transducer of fig. 2A and 2B is merely an exemplary illustration and may be provided as a greater or lesser number of ports. In addition, in different implementations, there are some other forms of variations in the functional units of the ultrasound system and/or the connection relationships between the functional units, see in particular the description of the other parts of the application.

When distance detection is required, the ultrasonic transducer chip receives a trigger signal from the ECU and then generates an ultrasonic driving signal which is used for driving the ultrasonic transducer to emit ultrasonic waves (the process is called a driving stage); after the driving phase, the driving signal stops driving the ultrasonic transducer, but the ultrasonic transducer cannot immediately stop vibrating, but a periodic oscillation signal is generated (the process is called as a 'aftershock phase' and a 'oscillation phase'), and in the oscillation phase, the signal processing circuit cannot identify an echo signal (a signal reflected by an obstacle when the transmitted ultrasonic waves encounter the obstacle) because the intensity of the oscillation signal is high; after the aftershock phase, the signal processing circuit may identify the echo signal (this process is referred to as the "receive phase").

In the signal processing process, the driving signal of the driving stage, the oscillating signal of the oscillating stage and the echo signal of the receiving stage are all input into the signal processing circuit for processing. Particularly, in the case that an ultrasonic transducer is used as both an ultrasonic transmitting transducer and an ultrasonic receiving transducer, when the oscillation signal is strong, the echo reflected by the obstacle is submerged in the oscillation signal and cannot be detected, and the distance from which the echo cannot be detected is also called a blind area. The following description refers to the accompanying drawings.

Referring to fig. 3, a schematic diagram of signal processing without an obstacle in a blind zone in the prior art is shown. As shown in fig. 3, the horizontal axis represents time or a representation after conversion to distance, and the vertical axis represents the envelope signal strength value for the threshold comparison circuit. In the embodiment of the application, IO is an output signal of the ultrasonic transducer chip, the output signal is transmitted to the upper processing circuit ECU, and the upper processing circuit ECU judges whether an obstacle and an obstacle distance exist according to IO. In an example, when the envelope signal strength of the envelope curve is greater than the envelope curve threshold, then IO is the first logic, and when the envelope signal strength is less than the envelope curve threshold, IO is the second logic. Illustratively, the first logic is 0 and the second logic is 1. In other parts of this document, a logic "1" may also be referred to as a high level, and a logic "0" may also be referred to as a low level. In fig. 3, in the driving stage and the oscillating stage, since the intensity of the envelope signal is relatively large, the IO output is logic 0, when the intensity of the envelope signal gradually decreases to the threshold value, the IO output is logic 1, when the intensity of the envelope signal is larger than the threshold value again, the IO output is logic 0, which indicates that the echo reflected by the obstacle appears, and then the IO output is logic 1, in the process, the IO output signal received by the upper processing circuit ECU is logic 0-logic 1-logic 0-logic 1, and the ECU can recognize the echo in the receiving stage according to the IO output signal (logic 0 appears after logic 1).

Referring to fig. 4, a schematic diagram of signal processing with an obstacle in a blind zone in the prior art is shown. As shown in fig. 4, when the envelope signal strength has not decreased to the threshold value, it appears that echo 1 causes the envelope signal strength that should have decreased to be not decreased and the strength is still higher than the envelope curve threshold value, at this time, IO is still outputting logic 0; when the envelope signal strength continues to drop to the threshold value, IO outputs logic 1; when the envelope signal strength is again above the threshold, the IO output is logic 0, indicating that echo 2 is present, and then the IO output is logic 1. In the process, the IO output signals received by the upper processing circuit ECU are logic 0-logic 1-logic 0-logic 1, the ECU can identify echo 2 in the receiving stage according to the IO output signals (logic 0 appears after logic 1), and echo 1 appearing in the aftershock or oscillation stage cannot be detected, so that a large blind area can be generated in a short distance.

Aiming at the problems, the embodiment of the application provides a signal processing scheme, and the timing circuit is used for judging the timing of ending oscillation, so that the timing of IO overturning and recovering is controlled by the output logic circuit, the control logic is simple, and the dead zone distance can be effectively shortened. The following detailed description is directed to specific embodiments.

Referring to fig. 5, a schematic diagram of a distance measurement principle of another ultrasonic system according to an embodiment of the present application is provided. As shown in fig. 5, the signal processing circuit in the ultrasonic transducer chip further includes a driving circuit, an echo signal processing circuit, a threshold generating circuit, a threshold comparing circuit, an output logic circuit, and a timer circuit on the basis of the ultrasonic system shown in fig. 2B. It should be noted that the ultrasonic transducer chip according to the embodiment of the present application may be applied to the ultrasonic system shown in fig. 2A, and for simplicity of description, only the ultrasonic system shown in fig. 2B is used as an example.

It should be noted that, for ease of understanding, the working principle of the signal processing circuit is described by taking an application scenario of ultrasonic ranging as an example in the embodiment of the present application, but the application scenario should not be taken as a limitation of the protection scope of the present application. It will be appreciated that when the signal processing circuit is applied in other application scenarios, other types of signals may be processed based on the same principle, all of which shall fall within the scope of the present application.

With continued reference to fig. 5, the output end of the driving circuit is electrically connected to the input end of the ultrasonic transducer, the output end of the ultrasonic transducer is electrically connected to the input end of the echo processing circuit, the output end of the echo processing circuit is electrically connected to the first input end of the threshold comparison circuit, the output end of the threshold generation circuit is electrically connected to the second input end of the threshold comparison circuit, the output end of the threshold comparison circuit is electrically connected to the input end of the output logic circuit, the output end of the output logic circuit is electrically connected to the ECU, the output end of the driving circuit is also electrically connected to the input end of the timer circuit, and the output end of the timer circuit is electrically connected to the input end of the output logic circuit.

And the driving circuit is used for receiving the trigger signal sent by the ECU and generating a driving signal based on the trigger signal. In a specific implementation, the driving signal output by the driving circuit is sent to the ultrasonic transducer for driving the ultrasonic transducer to generate an ultrasonic signal and is also sent to the timing circuit, so that the timing circuit starts timing.

And the echo signal processing circuit is used for receiving the signal to be processed output by the ultrasonic transducer and outputting an envelope curve based on the signal to be processed. In one possible implementation, the echo signal processing circuit includes a pre-circuit and an envelope processing circuit, as shown in fig. 6, where an input of the pre-circuit is electrically connected to an output of the ultrasonic transducer, an output of the pre-circuit is electrically connected to an input of the envelope processing circuit, and an output of the envelope processing circuit is electrically connected to a first input of the threshold comparison circuit.

In a specific implementation, the front-end circuit comprises a sampling circuit, and the sampling circuit is used for sampling the received signal to be processed to obtain a sampling signal. As described above, the driving signal of the driving stage, the oscillating signal of the oscillating stage and the echo signal of the receiving stage are input to the echo processing circuit for processing, and thus the sampling signal includes the driving signal of the driving stage, the oscillating signal of the aftershock stage and the echo signal of the receiving stage.

In particular implementations, the sampling circuit may be an analog-to-digital converter (Analog to Digital Converter, ADC). Of course, those skilled in the art may set other types of sampling circuits according to actual needs, and the embodiment of the present application is not limited thereto.

And the envelope processing circuit is used for receiving the sampling signal output by the sampling circuit, and carrying out peak value sampling on the sampling signal to generate an envelope curve. In a specific implementation, in order to ensure sampling precision, a sampling circuit generally performs oversampling on a signal to be processed, so that the data volume of the output sampling signal is larger, and in order to reduce the data volume in a subsequent processing process, the embodiment of the application performs data extraction on the sampling signal through an envelope processing module, so as to obtain an envelope curve with smaller data volume. In the subsequent step, threshold comparison is performed based on the envelope curve, and the accuracy of the subsequent threshold comparison is not affected while the data processing amount is greatly reduced.

And the threshold generating circuit is used for outputting an envelope curve threshold. Specifically, the threshold generating circuit includes a storage unit for storing the static threshold, and the threshold generating circuit reads the static threshold in the storage unit to generate the envelope curve threshold. The memory unit may be a register, for example, in which a static threshold value may be written during obstacle detection, and the threshold generation circuit generates the envelope curve threshold value by reading the static threshold value in the register. The static threshold in the storage unit may be preset data in the system, or may be adjusted by the user according to a specific application scenario, which is not particularly limited in the embodiment of the present application.

And the threshold comparison circuit is used for receiving the envelope curve output by the envelope processing module and the envelope curve threshold output by the threshold generation circuit, and comparing the envelope curve with the envelope curve threshold to output a threshold comparison result. Specifically, the threshold comparison result may include a first logic and a second logic. Referring to fig. 7, a threshold comparison schematic diagram is provided in an embodiment of the present application. As shown in fig. 7, the envelope value of the envelope curve and the envelope curve threshold are input to the threshold comparison circuit at the same time, and the high-low level signal is output by comparing the magnitudes of the envelope curve and the envelope curve threshold. In the embodiment of the application, when a low level appears in the threshold comparison result, the detection of the obstacle is judged. Of course, the determination logic in the threshold comparison circuit may be adjusted to determine that an obstacle is detected when a high level appears in the threshold comparison result, which is not particularly limited in the embodiment of the present application.

And the output logic circuit is used for receiving the comparison result of the threshold comparison circuit and outputting the IO logic state based on the comparison result. Specifically, the IO logic state may include a first logic and a second logic. In one possible implementation, the output logic outputs a high level when the envelope value of the envelope curve is below the envelope curve threshold, i.e. the threshold comparison circuit outputs a high level, and outputs a low level when the envelope value of the envelope curve is above the envelope curve threshold, i.e. the threshold comparison circuit outputs a low level. But if the output logic circuit receives the signal output by the timing circuit, the high and low levels are output according to the signal of the timing circuit. In the embodiment of the application, when the output logic circuit outputs a low level, the detection of the obstacle is judged. Of course, the determination logic in the output logic circuit may be adjusted so that the detection of the obstacle is determined when the output logic circuit outputs a high level in the output result, which is not particularly limited in the embodiment of the present application.

The timing circuit is used for receiving the driving signal generated by the driving circuit, starting timing statistics based on the driving signal, and outputting the signal to the output logic circuit after finishing the timing statistics so that the output logic circuit outputs the inverted IO logic state in a preset time period. Specifically, the timing circuit starts timing a first timing duration according to the driving signal, outputs a first signal after the first timing duration Δt1 is completed, starts timing a second timing duration, and outputs a second signal after the second timing duration Δt2 is completed, wherein the first signal is used for controlling the output logic circuit to start outputting the inverted IO logic state, and the second signal is used for controlling the output logic circuit to stop outputting the inverted IO logic state, i.e. controlling the output logic circuit to invert the output IO logic state after receiving the first signal, if the output IO logic state is inverted from a low level to a high level, and stops outputting the inverted IO logic state after receiving the second signal, at this time, the output IO logic state output by the output logic circuit is completely dependent on the threshold comparison result of the threshold comparison circuit.

It should be noted that, the first time duration Δt1 and the second time duration Δt2 are two continuous periods, that is, after the timing circuit finishes the timing of the first time duration Δt1, the stand horse performs the timing of the second time duration Δt 2.

In another possible implementation manner, the timing circuit starts outputting the control signal after the first timing duration Δt1 is completed and ends outputting the control signal after the second timing duration Δt2 is completed according to the driving signal, where the control signal is used to control the output logic circuit to output the flipped IO logic state. The control signal is a continuously output signal, the output logic circuit outputs the inverted IO logic state only when receiving the control signal, and the output logic circuit stops outputting the inverted IO logic state immediately after receiving the control signal, wherein the IO logic state output by the output logic circuit completely depends on the threshold comparison result of the threshold comparison circuit.

In an embodiment of the present application, the signal to be processed includes: the driving signal of the driving stage, the oscillating signal of the oscillating stage and the echo signal of the receiving stage, wherein the end point of the oscillating stage is a first time point, and the first time point is a time point when the second timing starts. In specific implementation, the timing circuit designs the first timing duration Δt1 and the second timing duration Δt2 according to the oscillation phase end point, and the first timing duration Δt1 end time point, that is, the second timing duration Δt2 start time point, is only required before the second timing duration Δt2 end time point, which is not specifically required in the present application. It should be noted that, in the embodiment of the present application, the end point of the oscillation phase is a time point when the envelope curve falls below the envelope curve threshold when the oscillation phase has no near-distance echo, that is, a time point corresponding to when the envelope curve is equal to the envelope curve threshold in fig. 3.

According to the embodiment of the application, the timing circuit is used for judging the timing of ending oscillation, so that the timing of IO overturning and recovering is controlled through the output logic circuit, the control logic is simple, and the dead zone distance can be effectively shortened.

The processing procedure of the signal processing circuit provided by the application is described in detail below with reference to specific embodiments.

Referring to fig. 8, a schematic diagram of signal processing without an obstacle in a blind area according to an embodiment of the present application is provided. As shown in fig. 8, the timing circuit starts the first timing after receiving the driving signal of the driving circuit, at this time, the envelope curve is greater than the envelope curve threshold, the IO output is at a low level, after the first timing is finished, the timing circuit sends the first signal to the output logic circuit, and starts the second timing, the output logic circuit turns the IO output over after receiving the first signal, i.e. the IO output is turned over from a low level to a high level forcefully, after the second timing is finished, the timing circuit sends the second signal to the output logic circuit, after the output logic circuit receives the second signal, the forced turning over of the IO output is stopped, at this time, since there is no echo in the oscillation stage, the envelope curve is already started to be smaller than the envelope curve threshold, and therefore, according to the threshold comparison result, the IO output of the output logic circuit is still at a high level until, at the receiving stage, when the envelope curve is again greater than the envelope curve threshold, i.e. when the echo appears, the IO output turns to a low level again, and then turns to a high level. In this process, the IO signal received by the ECU is low-high-low-high, and the ECU determines that there is an echo according to the received IO signal (the ECU determines that there is an echo according to the low level generated after the high level).

If there is an obstacle in the dead zone, that is, the echo 1 is generated in the oscillation phase, the envelope curve is extended, see fig. 9, so when the second timing is finished, the output logic circuit receives the second signal, and after stopping the forced inversion of the IO output, the envelope curve is still greater than the threshold of the envelope curve, and at this time, the IO output of the output logic circuit becomes a low level according to the threshold comparison result. Then the envelope curve falls below the envelope curve threshold, the IO output of the output logic circuit is flipped again from low level to high level until echo 2 appears in the receiving stage, and when the envelope curve is again greater than the envelope curve threshold, the IO output is changed to low level again and then to high level. The IO signal received by the final ECU is low-high-low-high, indicating that there are two echoes. Therefore, by adopting the signal processing circuit of the embodiment of the application, the echo 1 and the echo 2 can be detected.

According to the embodiment of the application, by timing and forcedly pulling up the IO, stopping forcedly pulling up the IO at a corresponding time point, and then comparing the result of the IO signal output by the output logic circuit, the ECU judges whether the near-distance echo is generated, so that the logic is simple, the implementation is easy, the judgment result is accurate, the required cost is low, the performance of the ultrasonic sensor can be improved, the blind area is reduced, and the safety of a user is ensured.

In one possible implementation, the timing circuit may start the first timing at a driving phase start time point or a number of periods after a driving phase start time point or an oscillation phase start time point or a number of periods after an oscillation phase start. For example, assuming that the driving signal contains 16 pulse signals, the driving period takes 1ms from the beginning to the end, and the time from the beginning of the driving period to the time when the envelope curve decreases to the threshold value of the envelope curve when no obstacle is present is 5ms, the first timing duration Δt1 (less than 5 ms) may perform the first timing at the beginning time point of the driving period, or may start the first timing a number of periods after the beginning of the driving period, the beginning time point of the oscillating period, and a number of periods (less than 5 ms) after the beginning of the oscillating period.

In an embodiment, in order to control the time point when the timing circuit starts the first timing, the signal processing circuit further includes a starting device, see fig. 10, which is a schematic diagram of a ranging principle of another ultrasonic system according to an embodiment of the present application. As shown in fig. 10, the embodiment of the present application is further provided with a starting device on the basis of the ultrasonic system shown in fig. 6, wherein the input end of the starting device is electrically connected with the output end of the driving circuit, and the output end of the starting device is electrically connected with the input end of the timing circuit. The starting device is used for sending a starting signal to the timing circuit in a preset time period according to the driving signal so as to enable the timing circuit to start first timing. For example, the starting device may send a start signal to the timing circuit at a time point of starting 0ms, 0.5ms, 1ms, 2ms, etc. in the driving phase, and the timing circuit starts counting the first timing duration Δt1 after receiving the start signal. It should be noted that, in the embodiment of the present application, the starting device is provided with a timing module.

In a specific implementation, when the starting device does not have a timing module, a timing device may be disposed in front of the starting device to control a time point when the starting device sends a starting signal, as shown in fig. 10. The input end of the timing device is electrically connected with the output end of the driving circuit, and the output end of the timing device is electrically connected with the input end of the starting device. The timing device is used for receiving the driving signal and sending a timing end signal to the starting device in a preset time period according to the driving signal so that the starting device sends a starting signal to the timing circuit. Illustratively, the timing device may send a timing end signal to the initiating device at a point in time when the drive phase begins 0ms, 0.5ms, 1ms, 2ms, etc.

In the embodiment of the application, the driving signal just sends out and has no echo in a short time, so the starting time of the timing circuit can be delayed, and the starting time of the timing circuit can be flexibly adjusted according to different threshold curves, so that the application range is enlarged, the application of the signal processing circuit of the embodiment of the application is more flexible, and the power consumption is saved.

In one possible implementation manner, due to different ultrasonic frequencies and different circuit performances, the generated envelope curves are different, so that the oscillation ending time points are different, and in order to adapt to different ultrasonic frequencies and different circuit performances, the timing duration of the timing circuit is set to be configurable.

Referring to fig. 11, a schematic diagram of a distance measurement principle of another ultrasonic system according to an embodiment of the present application is provided. As shown in fig. 11, the embodiment of the present application further provides a configuration circuit on the basis of the ultrasonic system shown in fig. 6, wherein an output end of the configuration circuit is electrically connected with an input end of the timing circuit, and the configuration circuit can configure a first timing duration Δt1 and a second timing duration Δt2 of the timing circuit.

In another possible implementation manner, the configuration circuit can also be directly communicated with the ECU, and the user configures the first timing duration Δt1 and the second timing duration Δt2 according to the actual situation, so that the timing result is more accurate. Specifically, the time duration may be configurable by a user, where configuration parameters of the user are sent to the configuration circuit by a configuration signal transmitted by the ECU, and the configuration circuit configures the first time duration Δt1 and the second time duration Δt2 of the time circuit according to the configuration signal.

In another possible implementation manner, a parameter configuration module may be further configured in the driving circuit, where the parameter configuration module of the driving circuit configures the first timing duration Δt1 and the second timing duration Δt2 of the timing circuit.

According to the embodiment of the application, the first timing duration and the second timing duration can be flexibly adjusted according to actual conditions, so that the ultrasonic sensor can detect different distances and be used in different scenes, the adaptability and the flexibility of the ultrasonic sensor are greatly improved, the application range is expanded, the personalized function is provided, a customer can adjust according to different experimental results, and the accuracy of the ultrasonic sensor is further improved.

Referring to fig. 12, a schematic diagram of a distance measurement principle of another ultrasonic system according to an embodiment of the present application is provided. As shown in fig. 12, the embodiment of the present application is further provided with an amplifier and a filter between the sampling circuit and the ultrasonic transducer on the basis of the ultrasonic system shown in fig. 6. The amplifier can amplify the received ultrasonic signal, because the echo signal reflected by the obstacle is weak with the increase of time, so the amplification factor of the amplifier increases with the increase of time; the filter may filter the received ultrasonic signal to obtain an ultrasonic signal of a specified frequency, which may be a high-pass, low-pass or band-pass filter. It should be noted that the functions in the amplifier and the filter can be added or subtracted by those skilled in the art according to actual needs; or the amplifier and/or filter may be eliminated, as embodiments of the application are not particularly limited.

In the above embodiment, the first timing duration and the second timing duration are counted by the timing circuit, and the IO logic state is turned over in the second timing duration to detect whether the blind area has an obstacle, and in a specific implementation, the timing circuit may also be used to count the maintenance time of the IO logic state to detect whether the blind area has an obstacle, which will be described in detail below.

In another possible implementation, the timing circuit may be further configured to monitor a maintenance time of the IO logic state, and the output logic circuit determines whether to flip the output IO logic state based on the maintenance time of the IO logic state. Specifically, after receiving the driving signal sent by the driving circuit, the timing circuit starts counting the third timing time length, and outputs a third signal to the output logic circuit after counting the third timing time length, the output logic circuit judges the IO logic state output at the time after receiving the third signal, and if the IO logic state output at the time is not predicted to be the IO logic state, the output IO logic state is turned over for a period of time.

In a specific implementation, the timing end time point of the third timing duration is an oscillation phase end point. It should be noted that, in the embodiment of the present application, the end point of the oscillation phase is a time point when the envelope curve falls below the envelope curve threshold when the oscillation phase has no near-distance echo, that is, a time point corresponding to when the envelope curve is equal to the envelope curve threshold in fig. 3.

The following description is made with reference to specific embodiments.

Referring to fig. 13, a schematic diagram of signal processing with an obstacle in another blind area according to an embodiment of the present application is provided. As shown in fig. 13, assuming that the driving signal includes 16 pulse signals, the time is Δt3 which is a third time period from the start of the driving phase to the end of the oscillating phase, if Δt3 is later, the IO output is still in a low level state, it is considered that echo 1 is generated in the oscillating phase because the existence of echo 1 lengthens the time for the envelope curve to fall below the envelope curve threshold, for example, the time is elongated to Δt4. Therefore, the timing circuit is used for monitoring the maintaining time of the IO logic state, and whether the echo is generated in the oscillation stage can be judged. Specifically, after the timing circuit completes statistics of the third timing duration Δt3, a third signal is output to the output logic circuit, the output logic circuit judges the IO logic state at the moment, if the IO logic state is high level, the output IO logic state is not turned over, if the IO logic state is low level, the IO is forced to be pulled up or a high pulse is output, and the forced pulled up IO or the output high pulse represents the existence of echo 1, so that the obstacle in the blind area can be detected.

It should be noted that in the embodiment of the present application, the time for forcibly pulling up IO is very short, typically several pulses, and in a specific implementation, only the forced pulling up is finished before Δt 4.

The embodiment of the application monitors the maintenance time of the IO logic state through the timing circuit, judges whether the IO logic state is overturned or not through the output logic circuit, and has the advantages of simple control logic and effective shortening of the dead zone distance compared with the prior art that a plurality of logic circuits are needed to be matched with each other and the hardware cost is high.

In addition, since the frequency of the driving circuit is generally adjustable, such as the pulse frequency and the number of pulses, to suit different scenarios, to meet different requirements, including different transducers. In order to measure a longer distance, the ultrasonic transducer chip is generally externally connected with a transformer, and the transformer is connected with an ultrasonic transducer. However, due to the different frequencies of the transformer equivalent oscillating circuit and the transducer equivalent oscillating circuit, the envelope signal has a strong dip after the end of driving and before the start of oscillation, as shown in fig. 14, if the dip is too large beyond the threshold range, a high pulse is output, thereby causing erroneous judgment.

With continued reference to fig. 14, the timer circuit starts monitoring the holding time of the IO logic state from the start time point of the driving phase and ends monitoring the holding time of the IO logic state at the end time point of the oscillating phase, in a specific implementation, the IO logic states should be all low in the third timing period Δt3 from the start time point of the driving phase to the end time point of the oscillating phase, and if the output logic circuit finds that the IO logic state has a high level in the third timing period Δt3, for example, a high level appears after Δt5, the output logic circuit recognizes that the high level is caused by frequency mismatch or is considered to be caused by noise or other interference waves, and therefore does not output the high level, so that the IO output level at this time is forced to be pulled down, as shown in fig. 15. In particular implementations, the time to forcibly pull down the IO output level is short, as long as the oscillating signal is restored to a level greater than the threshold including the curve, due to the short duration of the high pulse caused by frequency mismatch or noise or other interfering waves. As shown in fig. 15, the Δt6 period is a period in which the output logic circuit forcibly pulls down the IO output level, and after Δt6, the output logic circuit resumes the normal output of IO. By detecting the maintenance time of the IO state, the echo signals can be screened out more accurately, and noise interference is prevented.

In specific implementation, the third timing duration Δt3 and Δt6 of the present application are configurable, and the configuration manner thereof may refer to the configuration manner of the first timing duration Δt1 and the second timing duration Δt2 in the foregoing embodiment, so that the description is concise, and the present application is not described herein.

The embodiment of the application judges that the first high-level pulse is caused by the mismatching of the frequency of the oscillating circuit when the driving phase is transited to the oscillating phase through timing, thereby controlling the output of IO, avoiding the misjudgment problem caused by mismatching of the oscillating frequency, and simultaneously having simple circuit and control logic.

In a possible implementation manner, the signal processing circuit further includes a judging circuit, and an input end of the judging circuit is electrically connected with an output end of the output logic circuit, and is used for receiving an IO logic state output by the output logic circuit, and judging an obstacle distance according to the IO logic state, so as to directly trigger an alarm system (such as a display screen, an alarm lamp, a buzzer, etc.).

In another possible implementation, the function of the determination circuit may also be implemented by the ECU. Specifically, the output end of the output logic circuit is electrically connected with the input end of the ECU, the output logic circuit can transmit the IO logic state to the ECU, and the ECU judges the obstacle distance according to the IO logic state, so that an alarm system (such as a display screen, an alarm lamp, a buzzer and the like) is directly triggered.

It should be noted that, the ultrasonic transducer in the above embodiment may be two independent devices including an ultrasonic transmitting transducer and an ultrasonic receiving transducer, or may be one device having both functions of transmitting ultrasonic waves and receiving ultrasonic waves; in addition, the ECU may be other micro-processing units having data processing capability, which is not particularly limited in the embodiment of the present application.

It should be noted that, the above signal processing circuits may be implemented by a hardware circuit, for example, the timing circuit receives a driving signal, starts timing statistics based on the driving signal, and sends a first signal and a second signal when the first timing duration and the second timing duration are over, and the output logic circuit controls the output IO logic state to turn over and recover according to the first signal and the second signal.

Corresponding to the above embodiment, the embodiment of the application further provides an ultrasonic signal processing chip.

Referring to fig. 16, a schematic structural diagram of an ultrasonic signal processing chip according to an embodiment of the present application is further provided. As shown in fig. 16, the ultrasonic signal processing chip includes a signal processing circuit, wherein an output end of the driving circuit is electrically connected with the ultrasonic transducer to drive the ultrasonic transducer to generate ultrasonic waves, and an input end of the echo signal processing circuit is electrically connected with the ultrasonic transducer to receive a signal to be processed input by the ultrasonic transducer, wherein the signal to be processed includes a driving stage, a aftershock stage and a receiving stage.

It should be noted that, for brevity, details of the embodiments of the present application may be referred to the description of the foregoing embodiments, and are not repeated herein.

Corresponding to the embodiment, the embodiment of the application also provides an automobile ultrasonic radar device.

Referring to fig. 17, a schematic structural diagram of an ultrasonic radar device for an automobile according to an embodiment of the present application is further provided. As shown in fig. 17, the automotive ultrasonic radar apparatus includes an ultrasonic transducer chip and an ultrasonic transducer, wherein the ultrasonic transducer chip and the ultrasonic transducer are electrically connected, the ultrasonic transducer chip is configured to transmit a driving signal to the ultrasonic transducer so that the ultrasonic transducer generates an ultrasonic signal, and the ultrasonic transducer is configured to transmit a signal to be processed to the ultrasonic transducer chip, i.e., the ultrasonic transducer serves as both a transmitting transducer and a receiving transducer.

In one possible implementation, the automotive ultrasonic radar apparatus further includes an ECU electrically connected to the ultrasonic transducer chip, the ECU for activating the ultrasonic transducer chip and receiving the IO logic state of the ultrasonic transducer chip output.

It should be noted that, the specific content of the ultrasonic transducer chip and the ultrasonic transducer according to the embodiments of the present application may be referred to the description of the foregoing embodiments, and for brevity of description, the description is omitted herein.

Corresponding to the above embodiment, the embodiment of the present application further provides a computer readable storage medium, where the computer readable storage medium may store a program, where when the program runs, the device where the computer readable storage medium is located may be controlled to execute some or all of the steps in the above method embodiment. In particular, the computer readable storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (random access memory, RAM), or the like.

Corresponding to the above embodiments, the present application also provides a computer program product comprising executable instructions which, when executed on a computer, cause the computer to perform some or all of the steps of the above method embodiments.

In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relation of association objects, and indicates that there may be three kinds of relations, for example, a and/or B, and may indicate that a alone exists, a and B together, and B alone exists. Wherein A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of the following" and the like means any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.

Those of ordinary skill in the art will appreciate that the various elements and algorithm steps described in the embodiments disclosed herein can be implemented as a combination of electronic hardware, computer software, and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In several embodiments provided by the present application, any of the functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a read-only memory (ROM), a random access memory (random access memory RAM), a magnetic disk, or an optical disk, etc., which can store program codes.

The foregoing is merely exemplary embodiments of the present application, and any person skilled in the art may easily conceive of changes or substitutions within the technical scope of the present application, which should be covered by the present application. The protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A signal processing circuit, comprising:

The output end of the driving circuit is used for outputting a driving signal; and

The input end of the echo signal processing circuit is used for receiving a signal to be processed, and the output end of the echo signal processing circuit is used for outputting an envelope curve; and

The output end of the threshold generating circuit is used for outputting an envelope curve threshold; and

A first input end of the threshold comparison circuit is electrically connected with an output end of the echo signal processing circuit to receive the envelope curve, a second input end of the threshold comparison circuit is electrically connected with an output end of the threshold generation circuit to receive the envelope curve threshold, and the threshold comparison circuit is used for comparing the envelope curve with the envelope curve threshold and outputting a threshold comparison result; and

The input end of the output logic circuit is electrically connected with the output end of the threshold comparison circuit, and the output end of the output logic circuit is used for outputting IO logic states; and

The input end of the timing circuit is electrically connected with the output end of the driving circuit, the output end of the timing circuit is electrically connected with the input end of the output logic circuit, and the timing circuit is used for enabling the output logic circuit to output an inverted IO logic state according to the driving signal and timing duration.

2. The signal processing circuit of claim 1, wherein the timing circuit for toggling the IO logic state of the output logic circuit for output according to the drive signal and the timing duration comprises:

The timing circuit is used for starting to count a first timing duration according to the driving signal, outputting a first signal after the first timing duration is finished, starting to count a second timing duration, and outputting a second signal after the second timing duration is finished, wherein the first signal is used for controlling the output logic circuit to start outputting the inverted IO logic state, and the second signal is used for controlling the output logic circuit to stop outputting the inverted IO logic state, and the first timing duration and the second timing duration are continuous two periods of time.

3. The signal processing circuit of claim 2, wherein the signal to be processed comprises: the device comprises a driving stage, an oscillating stage and a receiving stage, wherein the end point of the oscillating stage is a first time point, and the first time point is the time point when the second timing starts; the timing circuit may start the first timing at a driving stage start time point or a number of periods after a driving stage start time point or an oscillation stage start time point or a number of periods after an oscillation stage start.

4. The signal processing circuit of claim 2, further comprising an activation device, wherein an input of the activation device is electrically connected to an output of the driving circuit, an output of the activation device is electrically connected to an input of the timing circuit, and the activation device is configured to send an activation signal to the timing circuit for a preset period of time according to a driving signal, so that the timing circuit starts the first timing.

5. The signal processing circuit of claim 2, further comprising a configuration circuit having an output electrically coupled to an input of the timing circuit, the configuration circuit configured to configure the first timing duration and the second timing duration of the timing circuit.

6. The signal processing circuit of claim 5, wherein the configuration circuit has an input electrically connected to the ECU, and wherein the configuration circuit is configured to configure the first timing duration and the second timing duration of the timing circuit according to the configuration signal transmitted by the ECU.

7. The signal processing circuit of claim 2, wherein the drive circuit includes a parameter configuration module for configuring a first timing duration and a second timing duration of the timing circuit.

8. The signal processing circuit of claim 1, wherein the echo signal processing circuit comprises:

The input end of the front-end circuit is used for receiving a signal to be processed, and the output end of the front-end circuit is used for outputting a sampling signal;

And the input end of the envelope processing circuit is electrically connected with the output end of the front-end circuit, and the output end of the envelope processing circuit is used for outputting an envelope curve.

9. An ultrasonic signal processing chip for electrical connection with an ultrasonic transducer, comprising:

The signal processing circuit of any of claims 1-8;

The output end of the driving circuit is electrically connected with the ultrasonic transducer so as to drive the ultrasonic transducer to generate ultrasonic waves, and the input end of the echo signal processing circuit is electrically connected with the ultrasonic transducer so as to receive signals to be processed, which are input by the ultrasonic transducer.

10. An automotive ultrasonic radar apparatus, comprising:

the chip of claim 9;

The ultrasonic transducer is electrically connected with the chip and is used for receiving a driving signal output by the chip to generate an ultrasonic signal, and the ultrasonic transducer is used for sending a signal to be processed to the chip and is used as a transmitting transducer and a receiving transducer;

and the ECU is electrically connected with the chip and is used for starting the chip and receiving the IO logic state output by the chip.