CN221202538U - Fuse trimming circuit - Google Patents
Fuse trimming circuit Download PDFInfo
- Publication number
- CN221202538U CN221202538U CN202323109718.8U CN202323109718U CN221202538U CN 221202538 U CN221202538 U CN 221202538U CN 202323109718 U CN202323109718 U CN 202323109718U CN 221202538 U CN221202538 U CN 221202538U
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- CN
- China
- Prior art keywords
- trimming
- tube
- nmos
- load pmos
- nmos tube
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- 238000009966 trimming Methods 0.000 title claims abstract description 78
- 238000007493 shaping process Methods 0.000 claims description 3
- 238000007664 blowing Methods 0.000 abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 3
- 150000004706 metal oxides Chemical class 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 2
- 102000005591 NIMA-Interacting Peptidylprolyl Isomerase Human genes 0.000 description 1
- 108010059419 NIMA-Interacting Peptidylprolyl Isomerase Proteins 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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- Semiconductor Integrated Circuits (AREA)
Abstract
The fuse trimming circuit comprises at least one fuse trimming branch, wherein the fuse trimming branch comprises a trimming NMOS (N-channel metal oxide semiconductor) tube, a trimming resistor connected between a source electrode of the trimming NMOS tube and the ground, the trimming resistor is connected with a fusing pin, a drain electrode of the trimming NMOS tube is connected with a trimming output end and a drain electrode of a first load PMOS tube, and a source electrode of the load PMOS tube is connected with a power supply; the grid electrode of the trimming NMOS tube is connected with a comparison NMOS tube connected in a diode mode, the source electrode of the comparison NMOS tube is grounded through a comparison resistor, the drain electrode of the comparison NMOS tube is connected with a power supply through a second load PMOS tube, the grid electrodes of the first load PMOS tube and the second load PMOS tube are connected with a bias circuit, and the bias circuit is used for generating bias voltage for driving the load PMOS tube. The utility model can realize trimming of the internal circuit under the conditions of full blowing and partial blowing of the fuse resistor.
Description
The utility model belongs to the field of electronic circuits, and particularly relates to a fuse trimming circuit.
Background
The fuse trimming circuit is a circuit module which is used for adjusting internal parameters of a circuit by externally heightening voltage and high current on pins to cause disconnection of fuse resistance of the internal circuit and changing the output state of the circuit, and is generally provided with a plurality of groups of fuses at the same time, one group or a plurality of groups of fuses are selected to be blown, and the internal parameters of the circuit are adjusted.
In the existing fuse trimming circuit, due to the reasons of process or device limitation, enough voltage and current cannot be applied when the fuse is blown so that the fuse is completely blown, and the fuse is not completely blown, so that a current path still exists, and the uncertainty of circuit output state adjustment is caused.
Disclosure of utility model
In order to overcome the defects in the prior art, the utility model discloses a fuse trimming circuit.
The fuse trimming circuit comprises at least one fuse trimming branch, wherein the fuse trimming branch comprises a trimming NMOS (N-channel metal oxide semiconductor) tube, a trimming resistor connected between a source electrode of the trimming NMOS tube and the ground, the trimming resistor is connected with a fusing pin, a drain electrode of the trimming NMOS tube is connected with a trimming output end and a drain electrode of a first load PMOS tube, and a source electrode of the load PMOS tube is connected with a power supply VCC;
The grid electrode of the trimming NMOS tube is connected with a comparison NMOS tube connected in a diode mode, the source electrode of the comparison NMOS tube is grounded through a comparison resistor, the drain electrode of the comparison NMOS tube is connected with a power supply through a second load PMOS tube, the grid electrodes of the first load PMOS tube and the second load PMOS tube are connected with a bias circuit, and the bias circuit is used for generating bias voltage for driving the load PMOS tube.
Preferably, the bias circuit comprises a bias current input NMOS tube and a bias mirror NMOS tube, wherein the grid electrode and the drain electrode of the bias current input NMOS tube are connected, the source electrode of the bias current input NMOS tube is grounded, the source electrode of the bias mirror NMOS tube is grounded, the grid electrode of the bias mirror NMOS tube is connected with the grid electrode of the bias current input NMOS tube, the drain electrode of the bias PMOS tube is connected with the drain electrode of the bias PMOS tube, the grid electrode and the drain electrode of the bias PMOS tube are connected and connected with the grid electrodes of the first load PMOS tube and the second load PMOS tube, and the source electrode of the bias PMOS tube is connected with a power supply.
Preferably, the drain electrode of the trimming NMOS tube can be connected with the trimming output end through a shaping circuit.
The fuse trimming circuit can realize trimming of an internal circuit under the conditions of full blowing and partial blowing of the fuse resistor.
Drawings
FIG. 1 is a schematic diagram of a fuse trimming circuit according to an embodiment of the present utility model.
Detailed Description
The following describes the embodiments of the present utility model in further detail with reference to the accompanying drawings.
The fuse trimming circuit comprises at least one fuse trimming branch, wherein the fuse trimming branch comprises a trimming NMOS (N-channel metal oxide semiconductor) tube, a trimming resistor connected between a source electrode of the trimming NMOS tube and the ground, the trimming resistor is connected with a fusing pin, a drain electrode of the trimming NMOS tube is connected with a trimming output end and a drain electrode of a first load PMOS tube, and a source electrode of the load PMOS tube is connected with a power supply VCC;
The grid electrode of the trimming NMOS tube is connected with a comparison NMOS tube connected in a diode mode, the source electrode of the comparison NMOS tube is grounded through a comparison resistor, the drain electrode of the comparison NMOS tube is connected with a power supply through a second load PMOS tube, the grid electrodes of the first load PMOS tube and the second load PMOS tube are connected with a bias circuit, and the bias circuit is used for generating bias voltage for driving the load PMOS tube.
The fuse trimming circuit shown in fig. 1 includes two fuse trimming branches, during normal operation, through selecting suitable comparison resistor R0 and trimming resistor resistance value, and the current mirror proportion of first trimming NMOS tube N4 and comparison NMOS tube N3, make first trimming NMOS tube N4 drain terminal voltage be in a lower state, when trimming, for example, apply high voltage through first fuse PIN1 of first fuse trimming branch, trimming NMOS tube is typically high voltage resistant device, first trimming resistor R1 is totally blown or partly blown under high voltage, no matter whether first trimming resistor R1 is totally blown, as long as take place partial blowing, necessarily result in first trimming resistor R1's resistance value to increase substantially, and because first trimming NMOS tube N4 and comparison NMOS tube N3 are the current mirror connection, the drain terminal resistance of first trimming NMOS tube N4 is increased because of the resistance value increase of first trimming resistor R1, the current mirror copies the current of comparison NMOS tube N3, make first trimming NMOS tube N4 drain terminal voltage increase to the level, and make the output from the drain terminal of first trimming NMOS tube N4 jump level increase to the inside the output structure through the first trimming resistor N1, when the output level jump-out structure is realized, this internal trimming circuit jump-out from the first trimming resistor output side, for example, the internal trimming circuit is realized, the internal level is connected through the first trimming resistor, and the internal level-adjusting circuit is jump-up, can take place, and the internal level is output, and the internal level is adjusted, and the level is adjusted.
The shaping circuit can be one or more inverters connected in series, or a comparator, wherein the inverter is suitable for output levels with larger variation range, the comparator is suitable for output levels with smaller variation range, and whether the output level of the first trimming output end rises is judged by comparing the output level with the internal reference voltage.
The specific implementation mode of the bias circuit is shown in fig. 1, and the bias circuit comprises a bias current input NMOS tube N1 and a bias mirror NMOS tube N2, wherein the grid electrode and the drain electrode of the bias current input NMOS tube are connected, the source electrode of the bias current input NMOS tube is grounded, the source electrode of the bias mirror NMOS tube N2 is grounded, the grid electrode of the bias current input NMOS tube N1 is connected with the grid electrode of the bias PMOS tube P1, the drain electrode of the bias PMOS tube is connected with the grid electrodes of the first load PMOS tube and the second load PMOS tube, the source electrode of the bias PMOS tube P1 is connected with a power supply VCC, the bias current IB is input from the bias current input NMOS tube N1, generates bias voltage at the source electrode of the bias PMOS tube P1 through the bias current input NMOS tube N1, the bias mirror NMOS tube N2 and the bias PMOS tube P1, and is input to the grid electrodes of the first load PMOS tube P2 and the second load PMOS tube P3.
The foregoing description of the preferred embodiments of the present utility model is not obvious contradiction or on the premise of a certain preferred embodiment, but all the preferred embodiments can be used in any overlapped combination, and the embodiments and specific parameters in the embodiments are only for clearly describing the utility model verification process of the inventor and are not intended to limit the scope of the utility model, and the scope of the utility model is still subject to the claims, and all equivalent structural changes made by applying the specification and the content of the drawings of the present utility model are included in the scope of the utility model.
Claims (3)
1. The fuse trimming circuit is characterized by comprising at least one fuse trimming branch, wherein the fuse trimming branch comprises a trimming NMOS tube, a trimming resistor is connected between a source electrode of the trimming NMOS tube and the ground, the trimming resistor is connected with a fusing pin, a drain electrode of the trimming NMOS tube is connected with a trimming output end and is connected with a drain electrode of a first load PMOS tube, and a source electrode of the load PMOS tube is connected with a power supply VCC;
The grid electrode of the trimming NMOS tube is connected with a comparison NMOS tube connected in a diode mode, the source electrode of the comparison NMOS tube is grounded through a comparison resistor, the drain electrode of the comparison NMOS tube is connected with a power supply through a second load PMOS tube, the grid electrodes of the first load PMOS tube and the second load PMOS tube are connected with a bias circuit, and the bias circuit is used for generating bias voltage for driving the load PMOS tube.
2. The fuse trimming circuit of claim 1, wherein the bias circuit comprises a bias current input NMOS and a bias mirror NMOS, the bias current input NMOS has a gate and drain connected, a source grounded, a gate connected to the bias current input NMOS, a drain connected to the bias PMOS, a gate and drain connected to the first load PMOS and the second load PMOS, and a source connected to a power supply.
3. The fuse trimming circuit of claim 1, wherein the drain of the trimming NMOS is connected to the trimming output through a shaping circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202323109718.8U CN221202538U (en) | 2023-11-17 | 2023-11-17 | Fuse trimming circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202323109718.8U CN221202538U (en) | 2023-11-17 | 2023-11-17 | Fuse trimming circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN221202538U true CN221202538U (en) | 2024-06-21 |
Family
ID=91488742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202323109718.8U Active CN221202538U (en) | 2023-11-17 | 2023-11-17 | Fuse trimming circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN221202538U (en) |
-
2023
- 2023-11-17 CN CN202323109718.8U patent/CN221202538U/en active Active
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| GR01 | Patent grant | ||
| GR01 | Patent grant |