CN220664888U

CN220664888U - Infrared detector chip wafer and infrared detector

Info

Publication number: CN220664888U
Application number: CN202322225803.4U
Authority: CN
Inventors: 刘继伟; 李松华; 刘向宏; 胡汉林; 王兴祥
Original assignee: Yantai Raytron Technology Co ltd
Current assignee: Yantai Raytron Technology Co ltd
Priority date: 2023-08-18
Filing date: 2023-08-18
Publication date: 2024-03-26
Anticipated expiration: 2033-08-18

Abstract

The application discloses an infrared detector chip wafer and an infrared detector packaging structure, wherein the infrared detector chip wafer comprises a substrate wafer, an epitaxial layer, an interlayer medium, an integrated circuit and a micro-bolometer connected with the integrated circuit; the integrated circuit is provided with a through hole penetrating the interlayer dielectric, the epitaxial layer and the substrate wafer, the side wall of the through hole is provided with an insulating layer, and the through hole is filled with a conductive material so as to connect the integrated circuit with the conductive material; the lower surface of the substrate wafer is provided with a conductive structure connected with the conductive material so that the integrated circuit is connected with an external circuit through the conductive structure. According to the technical scheme, through holes are formed in the integrated circuit, conductive materials are filled in the through holes, so that the integrated circuit is connected with an external circuit through the conductive materials and the conductive structure, and the integrated circuit is not required to be connected with the external circuit through an interconnection wire led out of the integrated circuit, so that the electrical interconnection length is shortened, the interconnection reliability is improved, and the signal transmission delay and the packaging volume are reduced.

Description

Infrared detector chip wafer and infrared detector

Technical Field

The application relates to the technical field of infrared detectors, in particular to an infrared detector chip wafer and an infrared detector.

Background

Electronic components for detecting infrared radiation signals of an object are called infrared detectors. The core of the detector is a detector chip which is composed of an MEMS sensor and a CMOS readout circuit. The infrared detector is divided into a refrigeration infrared detector and an uncooled photon detector.

Microbolometers, which are the most widespread ones for uncooled infrared detectors, are MEMS (Micro-Electro-Mechanical System, microelectromechanical system) microbridge structures.

At present, the infrared detector of the MEMS micro-bolometer structure is connected with an external circuit by adopting a transverse interconnection wire bonding technology, and the technology is relatively mature, but the connection mode can lead to low interconnection reliability, delay of signal transmission and increase of the packaging volume of the infrared detector.

In summary, how to enhance interconnection reliability of uncooled infrared detectors and reduce signal transmission delay and packaging volume is a technical problem to be solved by those skilled in the art.

Disclosure of Invention

In view of the foregoing, an object of the present application is to provide an infrared detector chip wafer and an infrared detector for enhancing the interconnection reliability of the infrared detector and reducing the signal transmission delay and the packaging volume.

In order to achieve the above object, the present application provides the following technical solutions:

an infrared detector chip wafer comprises a substrate wafer, an epitaxial layer arranged on the upper surface of the substrate wafer, an interlayer medium arranged on the upper surface of the epitaxial layer, an integrated circuit arranged in the interlayer medium, and a micro-bolometer arranged on the upper surface of the interlayer medium and connected with the integrated circuit;

the integrated circuit is provided with a through hole penetrating through the interlayer medium, the epitaxial layer and the substrate wafer, the side wall of the through hole is provided with an insulating layer, and the through hole is filled with a conductive material so that the integrated circuit is connected with the conductive material;

the lower surface of the substrate wafer is provided with a conductive structure connected with the conductive material so that the integrated circuit is connected with an external circuit through the conductive structure.

Preferably, an adhesion barrier layer is further disposed in the through hole and located between the insulating layer and the conductive material.

Preferably, a seed layer is further disposed in the through hole and located between the adhesion barrier layer and the conductive material.

Preferably, the conductive structure includes a first conductive structure located at the via;

Alternatively, the conductive structure includes a second conductive structure extending from the via to outside the via; the second conductive structures are not connected.

Preferably, the first conductive structure comprises a first metallization layer and a first solder located on the lower surface of the first metallization layer.

Preferably, the second conductive structure comprises a first PI layer located at a position of the lower surface of the substrate wafer except the through hole, a second metallization layer extending from the through hole to the outside of the through hole, a rewiring layer located at the lower surface of the second metallization layer, a third metallization layer located at a preset area of the lower surface of the rewiring layer, a second solder located at the lower surface of the third metallization layer, and a second PI layer located at a position of the lower surface of the first PI layer where the second metallization layer is not arranged and a position of the lower surface of the rewiring layer where the second solder is not arranged;

the second metallization layer located at the through hole is connected with the conductive material, the second metallization layer extending out of the through hole is located on the lower surface of the first PI layer, and the preset area is an area out of the corresponding area of the through hole.

Preferably, the integrated circuit comprises a CMOS region and a multi-layer conductive circuit interconnection region, wherein the CMOS region comprises a CMOS component, the multi-layer conductive circuit interconnection region comprises a multi-layer conductive circuit interconnection layer for connecting the CMOS component and the microbolometer, and each conductive circuit interconnection layer comprises a contact hole and a conductive layer positioned at the contact hole;

the contact holes in the conductive circuit interconnection layers at the bottom layer are connected with the CMOS component, the contact holes in the rest conductive circuit interconnection layers except the conductive circuit interconnection layers at the bottom layer are connected with the conductive layers in the conductive circuit interconnection layers at the next layer, the conductive layers in the conductive circuit interconnection layers at the top layer are also connected with the micro-bolometer, and the conductive circuit interconnection layers at the top layer also comprise signal transmission conductive layers connected with the conductive materials.

The infrared detector of the wafer level package comprises the infrared detector chip wafer and a window wafer bonded above the infrared detector chip wafer, wherein the infrared detector and the window wafer form a first vacuum cavity, and a microbolometer in the infrared detector chip wafer is positioned in the first vacuum cavity.

Preferably, the window wafer exit face further comprises a getter region.

An infrared detector of pixel level package, comprising the infrared detector chip wafer as set forth in any one of the above, and a pixel packaging layer disposed on the upper surface of the infrared detector chip wafer; the pixel packaging layer and the infrared detector chip wafer form second vacuum cavities corresponding to the micro-bolometers in the infrared detector chip wafer one by one, and the micro-bolometers are respectively positioned in the corresponding second vacuum cavities.

Preferably, the pixel packaging layer comprises a cover layer provided with release holes in a region corresponding to the micro-bolometer and a sealing layer positioned on the upper surface of the cover layer.

The infrared detector of metal package or ceramic package, including the tube shell, set up in the tube shell the infrared detector chip wafer of above-mentioned arbitrary one, wherein, infrared detector chip wafer passes through electrically conductive structure wherein and links to each other with the circuit in the tube shell.

The application provides an infrared detector chip wafer and an infrared detector, wherein the infrared detector comprises a substrate wafer, an epitaxial layer arranged on the upper surface of the substrate wafer, an interlayer medium arranged on the upper surface of the epitaxial layer, an integrated circuit arranged in the interlayer medium, and a micro-bolometer arranged on the upper surface of the interlayer medium and connected with the integrated circuit; the integrated circuit is provided with a through hole penetrating the interlayer dielectric, the epitaxial layer and the substrate wafer, the side wall of the through hole is provided with an insulating layer, and the through hole is filled with a conductive material so as to connect the integrated circuit with the conductive material; the lower surface of the substrate wafer is provided with a conductive structure connected with the conductive material so that the integrated circuit is connected with an external circuit through the conductive structure.

According to the technical scheme, through holes penetrating through interlayer dielectric, epitaxial layers and substrate wafers are formed in the integrated circuit, conductive materials are filled in the through holes, so that the integrated circuit in the infrared detector can be connected with an external circuit through the conductive materials in the through holes and a conductive structure arranged on the lower surface of the substrate wafers, namely, the integrated circuit can be interconnected with the external circuit through the through holes, namely, the infrared detector can be interconnected with the external circuit through the conductive structure at the through holes, and the interconnection wires are not required to be led out from the integrated circuit to be connected with the external circuit, therefore, the electric interconnection length can be effectively shortened, the interconnection reliability is improved, the signal transmission delay is reduced, the infrared detector packaging volume can be reduced, and the infrared detector can meet the development requirements of high-density interconnection, miniaturization, high performance and multiple functions. The insulating layer is arranged on the side wall of the through hole and can block the electric conduction between the conductive material and the substrate wafer so as to ensure the reliability of the infrared detector.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings may be obtained according to the provided drawings without inventive effort to a person skilled in the art.

Fig. 1 is a schematic structural diagram of an infrared detector chip wafer according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of another infrared detector chip wafer according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of an infrared detector of a wafer level package according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of another wafer-level packaged infrared detector according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of an infrared detector with a wafer level package according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of an infrared detector with pixel-level packaging according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of another pixel-level packaged infrared detector according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a method for fabricating an integrated circuit according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a bonding a first carrier wafer according to an embodiment of the present disclosure;

FIG. 10 is a schematic diagram of an etched via according to an embodiment of the present disclosure;

FIG. 11 is a schematic view of an insulation layer, an adhesion barrier layer and a seed layer disposed in a via hole according to an embodiment of the present disclosure;

fig. 12 is a schematic view of filling conductive material in a through hole according to an embodiment of the present application;

FIG. 13 is a schematic illustration of a method of making a microbolometer in accordance with an embodiment of the present application;

FIG. 14 is a schematic diagram of bonding a second carrier wafer to a lower surface of a substrate wafer according to an embodiment of the present application;

FIG. 15 is a schematic view of disposing a first photoresist and disposing a first metallization layer according to an embodiment of the present application;

fig. 16 is a schematic view of disposing a first solder at a through hole according to an embodiment of the present application;

FIG. 17 is a schematic illustration of the preparation of a second metallization layer provided in an embodiment of the present application;

fig. 18 is a schematic diagram of preparing a second solder according to an embodiment of the present application;

FIG. 19 is a schematic illustration of another method of making a microbolometer in accordance with an embodiment of the present application;

FIG. 20 is a schematic diagram of a bonding window wafer according to an embodiment of the present disclosure;

FIG. 21 is a schematic diagram of another bonding window wafer according to an embodiment of the present disclosure;

fig. 22 is a schematic diagram of a first conductive structure 11 prepared after bonding a window wafer according to an embodiment of the present application;

fig. 23 is a schematic diagram of a second conductive structure prepared after bonding a window wafer according to an embodiment of the present application;

fig. 24 is a schematic diagram of setting a second dielectric layer according to an embodiment of the present application;

FIG. 25 is a schematic diagram of a method for fabricating a pixel encapsulation layer according to an embodiment of the present disclosure;

FIG. 26 is a schematic diagram of a first conductive structure after bonding a pixel encapsulation layer according to an embodiment of the present disclosure;

FIG. 27 is a schematic diagram of a second conductive structure after bonding a pixel encapsulation layer according to an embodiment of the present disclosure;

FIG. 28 is a schematic view of an embodiment of a cover layer according to the present disclosure;

FIG. 29 is a schematic view of a first dielectric layer and a second dielectric layer in a pixel region and with release holes provided in a cap layer according to an embodiment of the present application;

FIG. 30 is a schematic illustration of yet another method of making a microbolometer in accordance with an embodiment of the present application;

FIG. 31 is a schematic diagram of a bonding third carrier wafer according to an embodiment of the present disclosure;

wherein, the reference numerals are as follows:

1-substrate wafer, 2-epitaxial layer, 3-interlayer dielectric, 4-integrated circuit, 41-CMOS region, 42-multilayer conductive circuit interconnect region, 421-contact hole, 422-conductive layer, 423-signal transmission conductive layer, 5-via, 6-insulating layer, 7-conductive material, 8-adhesion barrier layer, 9-seed layer, 10-microbolometer, 11-first conductive structure, 111-first metallization layer, 112-first solder, 12-second conductive structure, 121-first PI layer, 122-second metallization layer, 123-second solder, 124-second PI layer, 125-rewiring layer, 13-window wafer, 14-first vacuum cavity, 15-incident surface region, 16-exit surface region, 17-solder region, 18-getter region, 19-pixel encapsulation layer, 191-cap layer, 192-release hole, 193-sealing layer, 20-second vacuum cavity, 21-first carrier wafer, 22-second carrier wafer, 23-second carrier wafer, 24-second PI layer, 25-second solder, second carrier layer, 25-second solder, third dielectric layer, third wafer, and medium.

Detailed Description

At present, an infrared detector of an MEMS structure is interconnected with an external circuit by adopting a transverse interconnection wire bonding technology, namely, an integrated circuit in the infrared detector is connected with the external circuit through a lead-out interconnection wire. This connection may result in a relatively long interconnect line, resulting in delays in signal transmission and increased packaging volume of the infrared detector.

Therefore, the application provides an infrared detector chip wafer, an infrared detector packaged at a wafer level, an infrared detector packaged at a pixel level, an infrared detector packaged by metal or ceramic and a preparation method of the infrared detector chip wafer, which are used for enhancing the interconnection reliability of the infrared detector and reducing the signal transmission delay and the packaging volume.

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

Referring to fig. 1, a schematic structural diagram of an infrared detector chip wafer according to an embodiment of the present application is shown. The wafer of the infrared detector chip provided by the embodiment of the application can comprise a substrate wafer 1, an epitaxial layer 2 arranged on the upper surface of the substrate wafer, an interlayer medium 3 arranged on the upper surface of the epitaxial layer 2, an integrated circuit 4 arranged in the interlayer medium 3, and a micro-bolometer 10 arranged on the upper surface of the interlayer medium 3 and connected with the integrated circuit 4;

a through hole 5 penetrating the interlayer dielectric 3, the epitaxial layer 2 and the substrate wafer 1 is arranged at the integrated circuit 4, an insulating layer 6 is arranged on the side wall of the through hole 5, and a conductive material 7 is filled in the through hole 5 so that the integrated circuit 4 is connected with the conductive material 7;

the lower surface of the substrate wafer 1 is provided with conductive structures connected to the conductive material 7 so that the integrated circuits 4 are connected to external circuits through the conductive structures.

The infrared detector chip wafer provided by the application can sequentially comprise a substrate wafer 1, an epitaxial layer 2, an interlayer medium 3 and an integrated circuit 4 (the integrated circuit 4 is arranged in the interlayer medium 3), and a micro-bolometer 10 from bottom to top. The substrate wafer 1 plays a role of supporting, and the substrate wafer 1 may be a Silicon substrate, specifically a doped N-type or P-type Silicon substrate, or may be an SOI (Silicon-On-Insulator) Silicon wafer or a Silicon germanium wafer. The epitaxial layer 2 is a layer of lightly doped epitaxial layer 2, and the arrangement of the epitaxial layer 2 can improve the performance of the infrared detector chip wafer. The interlayer dielectric 3 disposed on the upper surface of the epitaxial layer 2 is used for playing a role of spacing between layers in the integrated circuit 4, the interlayer dielectric 3 is insulating, and the number of layers of the interlayer dielectric 3 is related to the number of layers of the integrated circuit 4. The integrated circuit 4 is connected to the microbolometer 10 such that the microbolometer 10 converts incident infrared radiation signals into electrical signals and transmits the electrical signals to the integrated circuit 4. The microbolometer 10 is specifically a MEMS structure, and the microbolometer 10 is in a suspended form.

In the infrared detector chip wafer provided by the application, a through hole 5 penetrating through an interlayer medium 3, an epitaxial layer 2 and a substrate wafer 1 is arranged at an integrated circuit 4. In order to ensure the reliability of the etching of the through hole 5, the thickness of the substrate wafer 1 may be 120 μm-350 μm, and the aspect ratio of the through hole 5 may be between 2:1 and 10:1. Of course, the thickness of the substrate wafer 1 and the aspect ratio of the through holes 5 may be adjusted according to the etching process of the through holes 5.

An insulating layer 6 is deposited on the sidewalls of the via 5 (the insulating layer 6 is not deposited on top) to block the electrical conduction between the conductive material 7 filled in the via 5 and the substrate wafer 1. Wherein the material of the insulating layer 6 can be specifically SiO ₂ Or Si (Si) ₃ N ₄ And the thickness of the insulating layer 6 may range from 50nm to 1000nm. It should be noted that, after the through hole 5 is etched, the insulating layer 6 may be deposited in the through hole 5, and then the top of the through hole 5 (i.e. at the position where the through hole 5 contacts the integrated circuit 4) may be etched back to the insulating layer 6, so that the conductive material 7 filled in the through hole 5 may be connected to the integrated circuit 4, thereby ensuring stable interconnection of the electrical signals.

In addition, the through-hole 5 is filled with the conductive material 7, and the conductive material 7 may specifically fill the through-hole 5 so that the conductive material 7 may be connected to the integrated circuit 4. Since the side wall of the through hole 5 is provided with the insulating layer 6, the conductive material 7 filled in the through hole 5 is not electrically conducted with the substrate wafer 1, so that the reliability of the infrared detector chip wafer can be ensured. The conductive material 7 may be filled in the through hole 5 by PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), electroplating, or the like. And the conductive material 7 may be Cu, ag, W, etc., and Cu may be selected as the conductive material 7 in the through hole 5 in consideration of electromigration characteristics, cost and technical maturity.

The lower surface of the substrate wafer 1 is provided with a conductive structure connected to the conductive material 7 in the through hole 5 (the conductive structure is a pin of the infrared detector chip wafer), so that the integrated circuit 4 is connected to the conductive structure through the conductive material 7 filled in the through hole 5, and the integrated circuit 4 can be connected to an external circuit through the conductive structure, without the need of leading out an interconnection line of the integrated circuit 4 to connect to the external circuit. That is, the present application makes the infrared detector chip wafer connect with the external circuit through the conductive structure by providing the through hole 5 and filling the conductive material 7 in the through hole 5 and providing the conductive structure, so that the electric signal converted by the micro bolometer 10 can be transmitted to the external circuit through the integrated circuit 4, the conductive material 7 filled in the through hole 5 and the conductive structure.

Through the above, the vertical lamination interconnection of the infrared detector chip wafer is realized by the through hole technology without wire bonding, namely, the interconnection from the original two-dimensional horizontal lead interconnection to the three-dimensional vertical through hole 5 interconnection is realized. That is, the through holes 5 realize the arrangement of vertical channels, and the conductive material 7 is filled in the through holes 5 to realize vertical interconnection, so that wire bonding is not needed. Therefore, through the infrared detector chip wafer packaging method and device, the electrical interconnection length can be effectively shortened, the signal transmission delay is reduced, the signal transmission speed is improved, the interconnection reliability is enhanced, the power consumption and the overall size and weight of the infrared detector chip wafer in the interconnection packaging process are reduced, and the development requirements of the infrared detector chip wafer towards high-density interconnection, miniaturization, high performance and multiple functions can be met. Meanwhile, the infrared detector chip wafer can be integrated in a three-dimensional space.

According to the technical scheme, through holes penetrating through interlayer media, epitaxial layers and substrate wafers are formed in integrated circuit positions, conductive materials are filled in the through holes, so that integrated circuits in the infrared detector chip wafers can be connected with external circuits through the conductive materials in the through holes, and conductive structures arranged on the lower surfaces of the substrate wafers, namely, the integrated circuits can be interconnected with the external circuits through the through holes, namely, the infrared detector chip wafers can be interconnected with the external circuits through the conductive structures at the through holes, and the interconnection lines are not required to be led out from the integrated circuits to be connected with the external circuits, and therefore, the electric interconnection length can be effectively shortened, the interconnection reliability is improved, the signal transmission delay is reduced, the infrared detector packaging volume can be reduced, and the infrared detector can meet the development requirements of high-density interconnection, miniaturization, high performance and multiple functions. The insulating layer is arranged on the side wall of the through hole and can block the electric conduction between the conductive material and the substrate wafer so as to ensure the reliability of the infrared detector.

According to the infrared detector chip wafer provided by the embodiment of the application, the adhesion barrier layer 8 between the insulating layer 6 and the conductive material 7 is further arranged in the through hole 5.

In this application, an adhesion barrier layer 8 between the insulating layer 6 and the conductive material 7 may also be provided in the via 5, and the adhesion barrier layer 8 may serve as both an adhesion layer between the insulating layer 6 and the conductive material 7 and a barrier layer for preventing the conductive material 7 from diffusing into the insulating layer 6 during the temperature annealing. The adhesion barrier layer 8 may have a thickness of 10nm to 200nm.

The adhesion barrier layer 8 may be specifically disposed after the insulating layer 6 is disposed in the through hole 5 and before the conductive material 7 is filled, and the material of the adhesion barrier layer 8 may be specifically Ti-TiN, ti-TiW, or Ta-TaN, where Ti and Ta play an adhesion role, tiN, tiW, taN play a role in blocking, and the material that plays the role in blocking may be deposited first during the disposing, and then the material that plays the role in adhesion is deposited. That is, the adhesion barrier layer 8 may specifically include an adhesive layer functioning as an adhesion, a barrier layer functioning as a barrier, and a barrier layer located between the insulating layer 6 and the adhesive layer, the adhesive layer being in contact with the conductive material 7.

According to the infrared detector chip wafer provided by the embodiment of the application, the seed layer 9 positioned between the adhesion barrier layer 8 and the conductive material 7 is further arranged in the through hole 5.

In this application, in order to improve the conductivity and adhesion of the conductive material 7, a seed layer 9 may be disposed between the adhesion barrier layer 8 in the via 5 and the conductive material 7, that is, after the adhesion barrier layer 8 is deposited, the seed layer 9 is deposited first and the conductive material 7 is refilled. The material of the seed layer 9 may be the same as the conductive material 7. For example, when the conductive material 7 is copper, the seed layer 9 is also copper for lattice matching of the bulk plating.

Referring to fig. 1 and fig. 2, fig. 2 is a schematic structural diagram of another infrared detector chip wafer according to an embodiment of the present application. According to the infrared detector chip wafer provided by the embodiment of the application, the conductive structure can comprise the first conductive structure 11 positioned at the through hole 5;

alternatively, the conductive structure may comprise a second conductive structure 12 extending from the through hole 5 to outside the through hole 5; the second conductive structures 12 are not connected to each other.

In this application, the conductive structure disposed on the lower surface of the substrate wafer 1 may include the first conductive structure 11 located at the through hole 5, that is, the first conductive structure 11 is a conductive structure of a through hole, and there is no dislocation with the position of the through hole 5.

Alternatively, the conductive structures disposed on the lower surface of the substrate wafer 1 may include second conductive structures 12 extending from the through holes 5 to outside the through holes 5, and the respective second conductive structures 12 are not connected, i.e., the second conductive structures 12 may not be located at the positions of the through holes 5. The extension range of the second conductive structure 12 may be set according to practical situations. The second conductive structure 12 can adjust the I/O positions and arrangement of the infrared detector chip wafer, redefine the pin distribution of the infrared detector chip wafer, realize interconnection design of the packaging layer, and reduce thickness and cost of the infrared detector chip wafer as a whole without using an IC carrier plate.

In one embodiment of the present disclosure, the first conductive structure 11 may include a first metallization layer 111 and a first solder 112 disposed on a lower surface of the first metallization layer 111.

In this application, the first conductive structure 11 may include a first metallization layer 111, and a first solder 112 located on a lower surface of the first metallization layer 111. The first metallization layer 111 may be regarded as an adhesion-seed layer, and may serve to adhere and improve conductivity, so as to facilitate the arrangement of the first solder 112, and the first metallization layer 111 may be a Ti-Cu layer. The first solder 112 may be tin, tin-silver, or the like, and the first solder 112 may specifically be a semi-ellipsoidal structure or the like formed by plating solder through an electroplating process and then through a thermal reflow process, so as to facilitate solder connection or the like with an external circuit, for example, with a BGA (ball grid array) form. Alternatively, the first solder 112 may be disposed on the lower surface of the first metallization layer 111 by means of solder ball printing.

In the infrared detector chip wafer provided in the embodiment of the present application, the second conductive structure 12 may include a first PI layer 121 located at a position except for the position of the through hole 5 on the lower surface of the substrate wafer 1, a second metallization layer 122 extending from the position of the through hole 5 to the position of the outside of the through hole 5, a rewiring layer 125 located on the lower surface of the second metallization layer 122, a third metallization layer located at a preset area on the lower surface of the rewiring layer 125, a second solder 123 located on the lower surface of the third metallization layer, and a second PI layer 124 located at a position where the second metallization layer 122 is not disposed on the lower surface of the first PI layer 121 and where the second solder 123 is not disposed on the lower surface of the rewiring layer 125;

The second metallization layer 122 located at the through hole 5 is connected to the conductive material 7, and the second metallization layer 122 extending out of the through hole 5 is located on the lower surface of the first PI layer 121, and the preset area is an area out of the corresponding area of the through hole 5.

In the present application, the second conductive structure 12 may include a first PI (polyimide) layer 121, a second metallization layer 122, a rewiring layer 125, a third metallization layer, a second solder 123, and a second PI layer 124. Wherein the first PI layer 121 is located at a position other than the through hole 5 on the lower surface of the substrate wafer 1; the second metallization layer 122 is located on the lower surface of the first PI layer 121 when extending from the through hole 5 to the outside of the through hole 5 and extending to the outside of the through hole 5, wherein the second metallization layer 122 located at the through hole 5 is connected with the conductive material 7 in the through hole 5; the rewiring layer 125 is located on the lower surface of the second metallization layer 122, where the size of the rewiring layer 125 may be the same as or close to the size of the second metallization layer 122, and the rewiring layer 125 may be specifically copper; the third metallization layer is located at a preset area on the lower surface of the rewiring layer 125, and the preset area is an area outside the corresponding area of the through hole 5, namely, an area which is not the through hole 5; the second solder 123 is located on the lower surface of the third metallization layer; the second PI layer 124 is located at a position where the second metallization layer 122 is not provided on the lower surface of the first PI layer 121 and at a position where the second solder 123 is not provided on the lower surface of the rewiring layer 125.

The second metallization layer 122 and the second solder 123 may be specifically disposed by laying the first PI layer 121, the second PI layer 124 and the patterning manner, for example, the first PI layer 121 may be laid on the lower surface of the substrate wafer 1, the first PI layer 121 may be patterned, the position of the through hole 5 may be exposed, the second metallization layer 122 may be disposed at the position extending from the position of the through hole 5 to the position outside the through hole 5, the rewiring layer 125 may be formed on the lower surface of the second metallization layer 122 by an electroplating process or the like, the second PI layer 124 may be laid on the lower surface of the rewiring layer 125 and the lower surface of the first PI layer 121, the second PI layer 124 may be patterned to expose a preset area on the lower surface of the rewiring layer 125, the third metallization layer may be disposed at the preset area on the lower surface of the rewiring layer 125, and the second solder 123 may be disposed on the lower surface of the third metallization layer. In addition, the first PI layer 121 and the second PI layer 124 may function to protect the substrate wafer 1, the second metallization layer 122, the rewiring layer 125, the third metallization layer, and the second solder 123, and may function to improve conductivity, reliability of the infrared detector chip wafer, and the like.

The second metallization layer 122 and the third metallization layer may be referred to as adhesion-seed layers, which play roles in adhesion and conductivity improvement, the second metallization layer 122 facilitates the arrangement of the rewiring layer 125, the third metallization layer facilitates the arrangement of the second solder 123, and the second metallization layer 122 and the third metallization layer may be Ti-Cu layers. The second solder 123 may be tin, tin-silver, or the like, and the second solder 123 may specifically be a semi-ellipsoidal structure or the like formed by plating solder through an electroplating process and then through a thermal reflow process, or the second solder 123 may be disposed at a predetermined region of the lower surface of the rewiring layer 125 by means of solder ball printing.

The foregoing description uses one rewiring layer 125 as an example, however, two layers, three layers of rewiring layers 125 may be provided, and the lower surface of each rewiring layer 125 may be provided with a third metallization layer, which is not described in detail herein.

In the infrared detector chip wafer provided in the embodiment of the present application, the integrated circuit 4 may include a CMOS area 41 and a multi-layer conductive circuit interconnection area 42, where the CMOS area 41 may include a CMOS component, the multi-layer conductive circuit interconnection area 42 may include a multi-layer conductive circuit interconnection layer for connecting the CMOS component with the microbolometer 10, and each layer of conductive circuit interconnection layer may include a contact hole 421 and a conductive layer 422 located at the contact hole 421;

wherein, the contact hole 421 in the conductive circuit interconnection layer at the bottom layer is connected with the CMOS assembly, the contact hole 421 in the rest conductive circuit interconnection layers except the conductive circuit interconnection layer at the bottom layer is connected with the conductive layer 422 in the conductive circuit interconnection layer at the next layer, the conductive layer 422 in the conductive circuit interconnection layer at the top layer is also connected with the microbolometer 10, and the conductive circuit interconnection layer at the top layer also comprises a signal transmission conductive layer connected with a conductive material.

In this application, the integrated circuit 4 may specifically include a CMOS (complementary metal oxide semiconductor) region, i.e., an S (source)/D (drain) region, located on the upper surface of the epitaxial layer 2, and further include a multi-layered conductive circuit interconnection region. Wherein the CMOS region 41 includes CMOS devices; the multi-layer conductive circuit interconnect region is used to interconnect the CMOS device and connect the CMOS device to the microbolometer 10, and includes a plurality of conductive circuit interconnect layers, for example, any one of 3-8 layers, or may include other layers of conductive circuit interconnect layers, wherein 3 layers are illustrated in fig. 1 and 2. In addition, the conductive circuit interconnection layer may be a conductive metal circuit interconnection layer, and the conductive circuit interconnection region may be a conductive metal circuit interconnection region.

Each conductive circuit interconnect layer includes a contact hole 421, a conductive layer 422 (which may be a metal layer in particular) located at the contact hole 421, and a signal transmission conductive layer 423 (which may be a transmission metal layer in particular, and the signal transmission conductive layer 423 is not located at the contact hole 421) connected to the conductive material 7, that is, the via 5 may be disposed at the signal transmission conductive layer 423. The different conductive circuit interconnection layers are connected through the contact hole 421, and are separated by the interlayer dielectric 3, the interlayer dielectric 3 is at least two layers, and the specific number of layers is related to the number of conductive circuit interconnection layers. That is, when the preparation is performed, the CMOS region 41 may be prepared first, then, a layer of interlayer dielectric 3 is deposited, patterning is performed on the interlayer dielectric 3, a layer of conductive circuit interconnection layer is disposed in the patterned interlayer dielectric 3, and then, a layer of interlayer dielectric 3 … … is deposited until a conductive circuit interconnection layer including a predetermined number of layers is obtained.

For the multi-layer conductive circuit interconnect layer, the contact holes 421 in the conductive circuit interconnect layer at the bottom are connected to the CMOS assembly, and the contact holes 421 in the remaining conductive circuit interconnect layers except the conductive circuit interconnect layer at the bottom are connected to the conductive layer 422 in the conductive circuit interconnect layer at the next layer (i.e., the layer below), and the conductive layer 422 in the conductive circuit interconnect layer at the top is also connected to the microbolometer 10. As can be seen from the above, the conductive circuit interconnect layer on the top layer includes not only the conductive layer 422 on the contact hole 421, but also the signal transmission conductive layer 423 not on the contact hole 421. The conductive layer 422 in the conductive circuit interconnection layer on the top layer is connected not only to the contact hole 421 in the layer, but also to the microbolometer 10, so that the infrared detector chip wafer can be connected to the CMOS assembly through the multi-layer conductive circuit interconnection area 42, that is, the conductive layer 422 in the conductive circuit interconnection layer on the top layer realizes signal transmission between the infrared detector chip wafer and the internal circuit. The signal transmission conductive layer 423 realizes signal transmission between the infrared detector chip wafer and an external circuit. It should be noted that, in this application, the signal transmission conductive layer 423 is illustrated as being located on the top layer, and of course, the signal transmission conductive layer 423 may also be located in any conductive circuit interconnection layer. The preparation of the multi-layer conductive circuit interconnect layer may be achieved by FEOL (front end of line process) in particular, by preparing CMOS components (i.e. N-type and P-type field effect transistors etc.) on the substrate wafer 1, and then by BEOL (back end of line process) in CMOS components.

The application further provides an infrared detector of wafer level package, referring to fig. 3 to 5, wherein fig. 3 shows a schematic structural diagram of an infrared detector of wafer level package provided in an embodiment of the application, fig. 4 shows a schematic structural diagram of an infrared detector of another wafer level package provided in an embodiment of the application, and fig. 5 shows a schematic structural diagram of an infrared detector of yet another wafer level package provided in an embodiment of the application. The wafer-level packaged infrared detector provided by the embodiment of the application can comprise any one of the above infrared detector chip wafers and the window wafer 13 bonded above the infrared detector chip wafers, wherein the infrared detector chip wafers and the window wafer 13 form a first vacuum cavity 14, and the micro-bolometer 10 in the infrared detector chip wafers is positioned in the first vacuum cavity 14;

the upper surface of the window wafer 13 may include an incident surface area 15, and the lower surface may include an exit surface area 16, where the incident surface area 15 and the exit surface area 16 are used to provide anti-reflection and anti-reflection for light in the operating band of the microbolometer 10.

The infrared detector of the wafer level package (also can be a wafer level package) provided by the application is used for realizing wafer level vacuum package on any one of the infrared detector chip wafers. Specifically, the infrared detector of the wafer level package may include not only any of the above-mentioned infrared detector chip wafers, but also a window wafer 13 bonded above the infrared detector chip wafer.

The upper surface of the window wafer 13 is provided with an incident surface area 15, the lower surface is provided with an exit surface area 16, the incident surface area 15 and the exit surface area 16 can be specifically arranged in an area where the micro-bolometer 10 is located, and the incident surface area 15 and the exit surface area 16 can be specifically formed by plating an antireflection film or setting a microstructure for performing antireflection and reflection increase on a working band of the micro-bolometer 10, thereby improving the absorption of light of the micro-bolometer 10 on the working band. In particular, the entrance face region 15 and exit face region 16 may be selected from different materials and configurations depending on the operating characteristics of the microbolometer 10. The lower surface of the window wafer 13 and the upper surface of any one of the infrared detector chip wafers are bonded together in a bonder according to a manner such as medium bonding or metal bonding selected from the solder region 17, and the solder region 17 is provided at an edge portion of the lower surface of the window wafer 13.

The window wafer 13 bonded above the infrared detector chip wafer and the infrared detector chip wafer form a first vacuum cavity 14, and the microbolometers 10 in the infrared detector chip wafer are all located in the first vacuum cavity 14 so as to realize wafer-level vacuum packaging of the infrared detector chip wafer. The first vacuum cavity 14 may be stacked by the solder region 17, as shown in fig. 3 and 5, or may be formed by etching the window wafer 13 to form a groove, as shown in fig. 4. The case where the conductive structure in the infrared detector corresponding to fig. 3 and 5 is the first conductive structure 11, the case where the conductive structure in the infrared detector is the second conductive structure 12, and the case where the conductive structure is the second conductive structure 12, the first vacuum chamber 14 may be formed by etching the window wafer 13 to form a groove, as described above.

The infrared detector of the wafer level package can be subsequently divided into single finished chips, and the infrared detector of the wafer level package can meet the development directions of miniaturization, batch and low cost of the infrared detector. Because the infrared detector is provided with the vertical channel through the through hole 5, and the vertical wiring interconnection is realized by filling the conductive material 7 in the through hole 5, and wire bonding is not needed, the length of the interconnection wire can be effectively shortened, the electric interconnection length can be effectively shortened, the signal transmission delay is reduced, the signal transmission speed is improved, the interconnection reliability is enhanced, the overall size and weight of the infrared detector in the interconnection packaging process are reduced, the increasing development demands of the chip I/O of the wafer-level vacuum package of the infrared detector are met, the device performance can be obviously improved, the device power consumption is reduced by greatly optimizing the wire interconnection mode, and meanwhile, the chip of the wafer-level vacuum package of the infrared detector is integrated in a three-dimensional space to be possible.

In the wafer-level packaged infrared detector provided in the embodiments of the present application, the exit surface of the window wafer 13 may further include a getter region 18.

In the present application, the exit surface of the window wafer 13 is further provided with a getter area 18, and the getter area 18 contains a getter, where the getter area 18 may be disposed in an area where the microbolometer 10 is not distributed, so as to avoid affecting the operation of the microbolometer 10. The getter area 18 is arranged to enable the vacuum degree in the first vacuum cavity 14 to well meet the working requirement of the micro-bolometer 10, so that the vacuum packaging performance of the wafer-level packaged infrared detector is improved.

The detailed description of the corresponding parts in the infrared detector provided in the application can be referred to for the structure of the infrared detector in the wafer level package, and will not be repeated here.

The application further provides an infrared detector of a pixel level package, referring to fig. 6 and 7, wherein fig. 6 shows a schematic structural diagram of an infrared detector of a pixel level package provided in an embodiment of the application, and fig. 7 shows a schematic structural diagram of an infrared detector of another pixel level package provided in an embodiment of the application. The embodiment of the application provides a pixel-level packaged infrared detector, which can include any one of the above infrared detector chip wafers, and a pixel packaging layer 19 arranged on the upper surface of the infrared detector chip wafer; the pixel packaging layer 19 and the infrared detector chip wafer form second vacuum cavities 20 corresponding to the micro-bolometers 10 in the infrared detector chip wafer one by one, and the micro-bolometers 10 are respectively located in the corresponding second vacuum cavities 20.

The pixel-level packaged infrared detector is used for realizing pixel-level vacuum packaging on any one of the infrared detector chip wafers, and the pixel-level vacuum packaging can meet the development directions of miniaturization, batch and low cost of MEMS devices.

Specifically, the pixel-level packaged infrared detector not only includes any of the above-mentioned infrared detector chip wafers, but also includes a pixel packaging layer 19 disposed on the upper surface of the infrared detector chip wafer. The pixel packaging layer 19 and any one of the above infrared detector chip wafers form a second vacuum cavity 20 corresponding to each micro-bolometer 10 in the infrared detector chip wafer one by one, and each micro-bolometer 10 is located in the corresponding second vacuum cavity 20. That is, the pixel encapsulation layer 19 is not planarly disposed on the upper surface of the infrared detector chip wafer, but is respectively protruded at each micro bolometer 10 to form a corresponding second vacuum cavity 20 accommodating the micro bolometer 10 with the infrared detector chip wafer.

Because the vertical channel is arranged in the infrared detector chip wafer through the through holes 5, and the wiring interconnection of verticality is realized by filling the conductive material 7 in the through holes 5, wire bonding is not needed, the length of an interconnection wire can be effectively shortened for the infrared detector packaged at the pixel level, signal transmission delay is reduced, signal transmission speed is improved, interconnection reliability is enhanced, power consumption and overall size and weight of the infrared detector in the interconnection packaging process are reduced, the increasing development demands of the chip I/O of the pixel-level vacuum package of the infrared detector are met, the device performance can be obviously improved, the device power consumption is reduced, and meanwhile, the chip of the pixel-level vacuum package of the infrared detector is enabled to be integrated in a three-dimensional space.

The pixel packaging layer 19 of the pixel-level packaged infrared detector provided in the embodiment of the application may include a cover layer 191 provided with a release hole 192 in a region corresponding to the micro bolometer 10, and a sealing layer 193 located on the upper surface of the cover layer 191.

In this application, the pixel encapsulation layer 19 may specifically include a cover layer 191 and a sealing layer 193 located on the upper surface of the cover layer 191, where a release hole 192 is disposed on the cover layer 191 in a region corresponding to the microbolometer 10, so that a dielectric layer that assists in forming the second vacuum cavity 20 during the preparation process is released through the release hole 192. The sealing layer 193 seals the release holes 192 to form the second vacuum chambers 20 in one-to-one correspondence with the microbolometers 10 together with the cover layer 191.

The cap layer 191 may be specifically α -Si (amorphous silicon), and the material of the sealing layer 193 may be Ge, znS, a combination of both, or the like.

The detailed description of the corresponding parts in the infrared detector chip wafer provided in the application can be referred to for the structure of the infrared detector chip wafer in the pixel-level package, and will not be repeated here.

The application also provides a metal-encapsulated or ceramic-encapsulated infrared detector, which can comprise a tube shell and any one of the infrared detector chip wafers arranged in the tube shell, wherein the infrared detector chip wafer is connected with a circuit in the tube shell through a conductive structure.

The infrared detector with the metal package or the ceramic package is used for realizing metal-level package or ceramic-level package on any one of the infrared detector chip wafers. Specifically, the infrared detector with metal package or ceramic package may include a package, and any of the above infrared detector chip wafers disposed in the package, where any of the above infrared detector chip wafers may be connected to a circuit in the package through a conductive structure therein, and may, for example, be connected to the conductive structure in the package in a BGA (Ball Grid Array) form.

Wherein, the tube shell can be a metal tube shell or a ceramic tube shell. When the tube shell is a metal tube shell, the infrared detector is a metal-encapsulated infrared detector. When the tube shell is a ceramic tube shell, the infrared detector is in ceramic package.

The detailed description of the corresponding parts in the infrared detector chip wafer provided in the application can be referred to for the structure of the infrared detector chip wafer in the metal-encapsulated or ceramic-encapsulated infrared detector, and the detailed description is omitted herein.

The application further provides a method for manufacturing the wafer of the infrared detector chip, referring to fig. 8-13, wherein fig. 8 shows a schematic diagram for manufacturing an integrated circuit, fig. 9 shows a schematic diagram for bonding a first wafer of the carrier, fig. 10 shows a schematic diagram for etching a through hole, fig. 11 shows a schematic diagram for arranging an insulating layer, an adhesion barrier layer and a seed layer in the through hole, fig. 12 shows a schematic diagram for filling conductive materials in the through hole, and fig. 13 shows a schematic diagram for manufacturing a microbolometer. The method for preparing the infrared detector chip wafer provided by the embodiment of the application can comprise the following steps:

Growing an epitaxial layer 2 on a substrate wafer 1, arranging an interlayer medium 3 on the upper surface of the epitaxial layer 2, and preparing an integrated circuit 4 in the interlayer medium 3;

bonding the upper surface of the interlayer dielectric 3 with the first carrier wafer 21, and etching a through hole 5 penetrating the substrate wafer 1, the epitaxial layer 2 and the interlayer dielectric 3 from the lower surface of the substrate wafer 1 and connected with the integrated circuit 4;

depositing an insulating layer 6 on the side wall of the through hole 5, and carrying out reverse etching of the insulating layer 6 on the top of the through hole 5;

filling a conductive material 7 in the through hole 5, and annealing the substrate wafer 1; the conductive material 7 is in contact with the integrated circuit 4;

removing the first carrier wafer 21, and preparing a micro bolometer 10 connected with the integrated circuit 4 on the upper surface of the interlayer medium 3;

conductive structures are prepared on the lower surface of the substrate in connection with the conductive material 7 in the vias 5 so that the integrated circuit 4 is connected to external circuitry through the conductive structures.

Step 11: an integrated circuit 4 is fabricated. As shown in fig. 8, a lightly doped epitaxial layer 2 is grown on a substrate wafer 1, an interlayer dielectric 3 is provided on the upper surface of the epitaxial layer 2, the interlayer dielectric 3 is patterned by a photolithography process or the like, and then an integrated circuit 4 is prepared. Wherein the sum of the layers of the interlayer dielectric 3 is related to the number of layers of the integrated circuit 4.

For the preparation of the integrated circuit 4, the specific process is that after a lightly doped epitaxial layer 2 is grown on the substrate wafer 1, a CMOS region 41 with CMOS components is prepared on the epitaxial layer 2, then an interlayer dielectric 3 is deposited and patterned to form a multi-layer conductive circuit interconnection region 42 for interconnecting the CMOS components, wherein the multi-layer conductive circuit interconnection region 42 comprises a plurality of conductive circuit interconnection layers, each conductive circuit interconnection layer is composed of a contact hole 421 and a metal layer, the integrated circuit 4 process may be composed of a plurality of conductive circuit interconnection layers, the multi-layer conductive circuit interconnection region 42 comprises at least two conductive circuit interconnection layers, the conductive circuit interconnection layers are separated by an interlayer dielectric 3, and at least two layers of interlayer dielectrics 3 are connected by a contact hole 421. In this application, taking 3 conductive circuit interconnection layers as examples, the actual layers may be 3, 4, 5, 6, 7, 8 or more layers, where the uppermost layer (i.e. the top layer) conductive circuit interconnection layer of the substrate wafer 1 includes a top layer contact hole 421, a top layer conductive layer 422 and a signal transmission conductive layer 423, the top layer conductive layer 422 is used for a coarse signal function between the infrared detector chip wafer and an internal circuit, and the signal transmission conductive layer 423 is used for signal transmission between the infrared detector chip wafer and an external circuit. This step prepares N-type and P-type field effect transistors on substrate wafer 1 by an integrated circuit front-end process, and then proceeds through an integrated circuit back-end process to effect the preparation of multi-layer conductive circuit interconnect region 42 on the transistor.

Step 12: the first carrier wafer 21 is temporarily bonded. As shown in fig. 9, a temporary bonding adhesive is coated on a side of the substrate wafer 1 containing the integrated circuits 4 (i.e., an upper surface of the interlayer medium 3) and a side of the first carrier wafer 21, the substrate wafer 1 and the side of the first carrier wafer 21 coated with the adhesive are attached, baked to a certain extent, then the substrate wafer 1 and the first carrier wafer 21 are transferred into a temporary bonding device, raised to a certain temperature, and a certain pressure is applied, so that the temporary bonding of the substrate wafer 1 and the carrier wafer is completed under a vacuum condition, and the first carrier wafer 21 is used for protecting the integrated circuits 4, thereby avoiding the influence of the subsequent preparation process on the integrated circuits 4.

Step 13: the through holes 5 are etched. As shown in fig. 10, a via 5 (specifically, a signal transmission conductive layer 423 in the integrated circuit 4) penetrating the substrate wafer 1, the epitaxial layer 2, and the interlayer dielectric 3 and connected to the integrated circuit 4 is etched from the lower surface of the substrate wafer 1. The through hole 5 is etched by deep reactive ion etching, which has the advantages of high etching speed and larger etching depth-to-width ratio. In addition, the etching of the through hole 5 may be performed by using a technique such as laser ablation or light-guided wet etching. The through-hole 5 of the designed size is obtained by the above etching process. In order to improve the smoothness of the through hole 5 and reduce the risk of the subsequent hole filling process, the through hole 5 may be cleaned.

From the above, the etching of the through hole 5 is performed after the integrated circuit 4 is prepared, that is, the etching of the through hole 5 is performed by the post-through hole technology.

Step 14: an insulating layer 6 is deposited. After etching to obtain the via 5, a thin insulating layer 6 may be deposited on the sidewall of the via 5 to block the conductive material 7 filled in the via 5 from electrically conducting with the substrate wafer 1, as shown in fig. 11. Specifically, an insulating layer 6 can be deposited on the inner surface of the through hole 5 by thermal oxidation, chemical vapor deposition or atomic layer deposition. After the insulating layer 6 is deposited, the insulating layer 6 needs to be reversely etched on the top of the through hole 5, so that stable interconnection of electric signals is ensured.

Step 15: filling the through hole 5. As shown in fig. 12, after the insulating layer 6 is etched back, the via 5 may be filled with a conductive material 7, and the conductive material 7 is connected to the integrated circuit 4 to transfer an electrical signal from the integrated circuit 4 to the conductive material 7 and thus to the conductive structure through the conductive material 7. Among them, the conductive material 7 may be Cu, ag, W, and Cu may be specifically selected as the conductive material 7 in the through hole 5 in consideration of electromigration characteristics, cost and technical maturity. The copper filling technology of the through holes 5 includes PVD, CVD, ALD, electroplating and the like, and the electroplating cost is lower and the deposition rate is faster, so that the through holes 5 can be filled by adopting an electroplating copper process, and the electroplating filling effect of the copper of the through holes 5 can be adjusted by adjusting inhibitors, accelerators and leveling agents in the electroplating liquid. And after the through holes 5 are filled, annealing the substrate wafer 1, and selecting a proper annealing temperature to ensure the reliability of interconnection of the through holes 5 and release stress caused by filling the through holes 5. After the copper plating filling of the through holes 5 is completed, an uneven copper layer is deposited on the lower surface of the substrate wafer 1, and then the superfluous deposited copper on the surface is removed, which is usually performed by using CMP (chemical mechanical polishing). Of course, when filling the through holes 5 with other conductive materials 7 and/or processes, an uneven layer of conductive material 7 may be deposited on the lower surface of the substrate wafer 1, and thus, the lower surface of the substrate wafer 1 may be processed by CMP or other processes to remove the excessive layer of conductive material 7 deposited on the lower surface of the substrate wafer 1.

Step 16: a microbolometer 10 was prepared. As shown in fig. 13, after the conductive material 7 is filled in the through hole 5, the first carrier wafer 21 may be removed first, and a common method may be a thermal slip method, an ultraviolet light peeling method, a chemical dissolution method, a laser disassembly method, or the like, and specifically, the method used may be determined according to the temporary bonding glue used in step 12, and then, the first carrier wafer 21 may be disassembled by using the determined method.

After removal of the first carrier wafer 21, a microbolometer 10 connected to the integrated circuit 4 may be prepared on the upper surface of the interlayer dielectric 3. The microbolometer 10 may be fabricated using conventional semiconductor processes including at least one process step of photolithography, etching, CVD, PVD, and the like. Specifically, the first dielectric layer 25 may be disposed on the upper surface of the interlayer dielectric 3, and the microbolometer 10 may be prepared in the first dielectric layer 25, and then the first dielectric may be removed at a corresponding timing as the case may be.

Step 17: and preparing a conductive structure. After the micro bolometer 10 is prepared on the upper surface of the interlayer dielectric 3, a conductive structure connected to the conductive material 7 in the via 5 is prepared on the lower surface of the substrate, so that the integrated circuit 4 can be connected to an external circuit through the conductive structure, and thus, an electrical signal is transmitted through the integrated circuit 4, the conductive material 7 and the conductive structure. In order to avoid the influence of the process on the microbolometer 10 when the conductive structure connected to the conductive material 7 in the through hole 5 is prepared on the lower surface of the substrate, the microbolometer 10 may be protected by a protection structure. The protection structure may be the first dielectric layer 25 used for manufacturing the microbolometer 10, the window wafer 13 for the wafer level package, the pixel package layer 19 for the pixel level package, the first dielectric layer 25 used for manufacturing the microbolometer 10, and the third carrier wafer 27 bonded on the upper surface of the first dielectric layer 25 for the metal or ceramic package.

The microbolometer 10 is protected from the first dielectric layer 25 used in preparing the microbolometer 10, bonding a carrier wafer to the upper surface of the first dielectric layer 25, and the like

The infrared detector chip wafer is prepared through the steps 11-17, wherein the detailed description of the corresponding parts in the infrared detector chip wafer provided in the application can be referred to for the specific structure of the infrared detector chip wafer and the description of the related structure, and the detailed description is omitted here.

The method for manufacturing an infrared detector chip wafer provided in the embodiment of the present application may further include, after bonding the upper surface of the interlayer medium 3 with the first carrier wafer 21:

the substrate wafer 1 is thinned from the lower surface of the substrate wafer 1 so that the thickness of the substrate wafer 1 is within a predetermined range.

Considering that the thickness of the substrate wafer 1 may be too thick (exceeding the maximum value in the preset range) to enable the etching of the through-hole 5 to be performed smoothly, as shown in fig. 8 and 9, after bonding the upper surface of the interlayer dielectric 3 with the first carrier wafer 21, the substrate wafer 1 may be thinned from the lower surface of the substrate wafer 1 so that the thickness of the substrate wafer 1 is within the preset range (120 μm-350 μm), thereby ensuring the reliability of the etching of the through-hole 5.

The method for manufacturing the wafer of the infrared detector chip, provided by the embodiment of the application, includes that the substrate wafer 1 is thinned from the lower surface of the substrate wafer 1, and may include:

performing rough grinding on the lower surface of the substrate wafer 1;

after the rough polishing, the lower surface of the substrate wafer 1 is subjected to fine polishing;

the substrate wafer 1 is subjected to wet etching or CMP processing.

In the present application, when the substrate wafer 1 is thinned from the lower surface of the substrate wafer 1, specifically, the lower surface of the substrate wafer 1 may be subjected to rough polishing, and then the lower surface of the substrate wafer 1 may be subjected to fine polishing. The manner of dividing thinning into two processes of rough grinding and fine grinding can improve the grinding efficiency of the substrate wafer 1 and optimize the grinding quality.

After the substrate wafer 1 is polished, stress generated during the polishing process may be released by wet etching or CMP processing, eventually making the thickness of the substrate wafer 1 within a preset range.

In order to prevent the substrate wafer 1 from being damaged during the thinning process, the substrate wafer 1 may be subjected to a trimming process.

Referring to fig. 11, the method for manufacturing an infrared detector chip wafer provided in the embodiment of the present application may further include, before the conductive material 7 is filled in the through hole 5:

An adhesion barrier layer 8 is deposited on the surface of the insulating layer 6.

In this application, after depositing the insulating layer 6 on the sidewall of the via hole 5 and performing the back etching of the insulating layer 6 on top of the via hole 5, before filling the conductive material 7 in the via hole 5, an adhesion barrier layer 8 may be deposited on the surface of the insulating layer 6. The adhesion barrier layer 8 may be Ti-TiN, ti-TiW, ta-TaN, ti, ta may be deposited by PVD, tiN or TaN, or the like, and may be deposited by metal organic chemical vapor deposition or ALD.

Referring to fig. 11, the method for preparing an infrared detector chip wafer provided in the embodiment of the present application may further include, after depositing the adhesion barrier layer 8 on the surface of the insulating layer 6 and before filling the conductive material 7 in the through hole 5:

a seed layer 9 is deposited on the surface of the adhesion barrier 8.

In this application, after depositing the adhesion barrier layer 8 on the surface of the insulating layer 6, before filling the conductive material 7 in the via hole 5, for lattice matching, so that the conductive material 7 has good conductive performance, the seed layer 9 may be deposited on the surface of the adhesion barrier layer 8, where the deposition of the seed layer 9 may be performed by PVD or ALD process.

Referring to fig. 14, a schematic diagram of bonding a second carrier wafer to the lower surface of a substrate wafer is shown. The method for preparing the wafer of the infrared detector chip provided in the embodiment of the application may further include, before preparing the microbolometer 10 on the upper surface of the interlayer medium 3:

Bonding a second carrier wafer 22 on the lower surface of the substrate wafer 1;

before the preparation of the conductive structure connected to the conductive material 7 in the via 5 on the lower surface of the substrate, it may further comprise:

the second carrier wafer 22 is removed.

In the present application, after removing the first carrier wafer 21, the second carrier wafer 22 may be bonded to the lower surface of the substrate before the microbolometer 10 is prepared on the upper surface of the interlayer dielectric 3. Specifically, a layer of temporary bonding glue can be coated on the lower surface of the substrate wafer 1 and one side of the second carrier wafer 22 respectively, one side of the substrate wafer 1 and one side of the second carrier wafer 22, which are glued, are attached, baked to a certain extent, then the substrate wafer 1 and the second carrier wafer 22 are transferred into temporary bonding equipment, raised to a certain temperature, and a certain pressure is applied, so that the temporary bonding of the substrate wafer 1 and the second carrier wafer 22 is completed under a vacuum condition. Through the step, the through holes 5 can be protected, the influence of the subsequent process on related materials arranged in the through holes 5 is avoided, and meanwhile, the substrate wafer 1 can be protected from being broken in the subsequent process.

The second carrier wafer 22 is removed before the lower surface of the substrate is provided with conductive structures connected to the conductive material 7 in the vias 5. Specifically, similarly to the first carrier wafer 21 removal method, the removal method is determined according to the temporary bonding adhesive used, and the determined removal method is selected for removal. Thereafter, a conductive structure may be prepared on the lower surface of the substrate.

As shown in fig. 1 and fig. 2, a method for preparing an infrared detector chip wafer according to an embodiment of the present application, in which a conductive structure connected to a conductive material 7 in a through hole 5 is prepared on a lower surface of a substrate, may include:

a first conductive structure 11 is arranged at the through hole 5 on the lower surface of the substrate;

alternatively, the second conductive structure 12 is provided on the lower surface of the substrate extending from the through hole 5 to the outside of the through hole 5.

In this application, when the conductive structure connected to the conductive material 7 in the through hole 5 is prepared on the lower surface of the substrate, the first conductive structure 11 may be specifically disposed at the through hole 5 on the lower surface of the substrate, or the second conductive structure 12 may be disposed on the lower surface of the substrate extending from the through hole 5 to the outside of the through hole 5.

Referring to fig. 15 and 16, fig. 15 shows a schematic view of disposing a first photoresist and disposing a first metallization layer, fig. 16 shows a schematic view of disposing a first solder at a through hole, wherein fig. 16 illustrates a first solder 112 as a semi-ellipsoidal structure, and further, one of fig. 15 and 16 shows a schematic view of disposing a first conductive structure 11, and fig. 15 and 16 further provide a first dielectric layer 25 and a third carrier wafer 27 at a position of the microbolometer 10 to protect the microbolometer 10, and specific reference to the first dielectric layer 25 and the third carrier wafer 27 will be made later. The method for manufacturing the wafer of the infrared detector chip provided in the embodiment of the present application, where the first conductive structure 11 is disposed at the through hole 5 on the lower surface of the substrate, may include:

A first photoresist 23 is arranged on the lower surface of the substrate wafer 1;

patterning the first photoresist 23 to expose the through hole 5;

a first metallization layer 111 is provided at the via 5 and the first photoresist 23 is removed, and a first solder 112 is provided at the lower surface of the first metallization layer 111.

In this application, the process of disposing the first conductive structure 11 at the through hole 5 on the lower surface of the substrate may specifically be: 1) A layer of first photoresist 23 is arranged on the lower surface of the substrate wafer 1, and the thickness of the first photoresist 23 is determined according to the use requirement; 2) Patterning the first photoresist 23 to expose the through hole 5 on the substrate wafer 1; 3) A first metallization layer 111 is provided at the via hole 5 by PVD or the like, and the first photoresist 23 is removed, and a first solder 112 is provided on the lower surface of the first metallization layer 111. The first metallization layer 111 may be disposed at the through hole 5 by depositing photoresist, etching, or the like, or the first metallization layer 111 may be disposed directly at the through hole 5.

In addition, if the first solder 112 having a semi-ellipsoidal structure is formed by a thermal reflow process (as shown in fig. 15 and 16), after the first metallization layer 111 is provided at the through hole 5, an auxiliary solder 24 is formed on the lower surface of the first metallization layer 111 by an electroplating process, and then the first photoresist 23 is removed by wet etching, and then the auxiliary solder 24 is subjected to a thermal reflow process to form the first solder 112. If the first solder 112 is generated by a solder ball printing method, after the first metallization layer 111 is disposed at the through hole 5, the first photoresist 23 may be removed, and the first solder 112 may be generated by a solder ball printing method.

Referring to fig. 17 and 18, fig. 17 shows a schematic view of preparing the second metallization layer, fig. 18 shows a schematic view of preparing the second solder, wherein fig. 18 illustrates a semi-ellipsoidal structure as the first solder, and further, one of fig. 17 and 18 shows a schematic view of disposing the second conductive structure 12, and fig. 17 and 18 further include a first dielectric layer 25 and a third carrier wafer 27 at a position of the microbolometer 10 to protect the microbolometer 10, and specific reference will be made to the first dielectric layer 25 and the third carrier wafer 27. The method for manufacturing the wafer of the infrared detector chip provided in the embodiment of the application, in which the second conductive structure 12 is disposed on the lower surface of the substrate extending from the through hole 5 to the outside of the through hole 5, may include:

a first PI layer 121 is arranged on the lower surface of the substrate wafer 1;

patterning the first PI layer 121 to expose the through hole 5;

depositing a second metallization layer 122 on the lower surface of the first PI layer 121, and arranging a second photoresist on the surface of the second metallization layer 122;

patterning the second photoresist to expose the second metallization layer 122 extending from the via 5 to a location outside the via 5;

Forming a rewiring layer 125 on the lower surface of the exposed second metallization layer 122, and removing the remaining second photoresist and the second metallization layer 122 covered by the second photoresist;

a second PI layer 124 is arranged on the lower surface of the first PI layer 121 and the lower surface of the rewiring layer 125, and the second PI layer 124 is patterned to expose a preset area on the lower surface of the rewiring layer 125; the preset area is an area outside the corresponding area of the through hole 5;

a third metallization layer is provided at a predetermined region of the lower surface of the second metallization layer 122, and a second solder 123 is provided at the lower surface of the third metallization layer.

In this application, the specific process of preparing the second conductive structure 12 may be as follows:

1) A first PI layer 121 is coated on the lower surface of the substrate wafer 1, and the first PI layer 121 is patterned to expose the through hole 5.

2) A second metallization layer 122 is deposited on the lower surface of the first PI layer 121, and a second photoresist is disposed on the lower surface of the second metallization layer 122.

3) The second photoresist is exposed and patterned to expose the second metallization layer 122 extending from the via 5 to a location outside the via 5.

4) A re-wiring layer 125 is formed on the lower surface of the exposed second metallization layer 122 by an electroplating process or the like. Thereafter, the remaining second photoresist and the second metallization layer 122 covering the same are removed.

5) A second PI layer 124 is disposed on the lower surface of the first PI layer 121 and the lower surface of the rewiring layer 125, and the second PI layer 124 is patterned to expose a predetermined area on the lower surface of the rewiring layer 125.

6) A third metallization layer is provided at a predetermined region of the lower surface of the rewiring layer 125 by PVD or the like, and a second solder 123 is provided on the lower surface of the third metallization layer.

In the case of forming the second solder 123 with a semi-ellipsoidal structure by thermal reflow (as shown in fig. 18), the second solder 123 may be formed by generating the auxiliary solder 24 on the lower surface of the third metallization by an electroplating process, and then performing thermal reflow on the auxiliary solder 24. If the second solder 123 is produced by means of solder ball printing, the second solder 123 may be printed directly at the third metallized lower surface.

The present application further provides a method for manufacturing an infrared detector of wafer level package, see fig. 3, 4, 8-12, 14, and 19-23, wherein fig. 19 shows a schematic diagram of another method for manufacturing a microbolometer, fig. 20 shows a schematic diagram of one bonding window wafer, fig. 21 shows a schematic diagram of another bonding window wafer, fig. 22 shows a schematic diagram of manufacturing a first conductive structure 11 after bonding a window wafer, and fig. 23 shows a schematic diagram of manufacturing a second conductive structure after bonding a window wafer. The method for manufacturing the wafer-level packaged infrared detector provided by the embodiment of the application can comprise the following steps:

The infrared detector chip wafer is prepared by adopting any one of the preparation methods of the infrared detector chip wafer;

in the method for preparing the infrared detector chip wafer, the micro bolometer 10 is prepared on the upper surface of the interlayer medium 3, and may include:

a first dielectric layer 25 is arranged on the upper surface of the interlayer dielectric 3, the micro-bolometer 10 is prepared on the first dielectric layer 25, and the first dielectric layer 25 is removed;

after the micro bolometer 10 is prepared on the upper surface of the interlayer medium 3, it may further include:

an incident surface area 15 is arranged on the upper surface of the window wafer 13, an emergent surface area 16 is arranged on the lower surface of the window wafer 13, a solder area 17 is arranged on the lower surface of the window wafer 13, and the lower surface of the window wafer 13 and the upper surface of the infrared detector chip wafer are bonded together through the solder area 17 so that the window wafer 13 and the infrared detector chip wafer form a first vacuum cavity 14;

the incident surface area 15 and the exit surface area 16 are used for anti-reflecting and anti-reflecting the working band of the microbolometer 10 in the infrared detector chip wafer, and the microbolometer 10 in the infrared detector chip wafer is located in the first vacuum cavity 14.

The preparation method of the wafer-level packaged infrared detector is as follows:

Step 21: as shown in fig. 8, an integrated circuit 4 is fabricated.

Step 22: as shown in fig. 9, the first carrier wafer 21 is temporarily bonded.

Step 23: as shown in fig. 10, the through hole 5 is etched.

Step 24: as shown in fig. 11, an insulating layer 6 is deposited.

Step 25: as shown in fig. 12, the through-hole 5 is filled. The implementation process of step 21 to step 25 is the same as the implementation process of step 11 to step 15, and will not be described here again.

Step 26: as shown in fig. 19, a microbolometer 10 was prepared. Specifically, after the first carrier wafer 21 is removed, a first dielectric layer 25 is provided on the upper surface of the interlayer dielectric 3, and the microbolometer 10 is fabricated on the first dielectric layer 25. After the microbolometer 10 is fabricated on the first dielectric layer 25, the first dielectric layer 25 is removed to form the suspended microbolometer 10, as shown in fig. 14. The first dielectric layer 25 may be removed in a plasma of oxygen by a dry chemical etching method. Fig. 19 and 14 illustrate an example in which the second carrier wafer 22 is bonded to the lower surface of the substrate wafer 1, but the second carrier wafer 22 may not be bonded. Fig. 19 shows a schematic diagram of the microbolometer 10 prepared after removing the first carrier wafer 21 and bonding the second carrier wafer 22, specifically, after bonding the second carrier wafer 22, a first dielectric layer 25 may be disposed on the upper surface of the interlayer dielectric 3, and the microbolometer 10 may be prepared on the upper surface of the first dielectric layer 25, and then the first dielectric layer 25 may be removed to obtain the structure shown in fig. 14.

Step 27: as shown in fig. 20 and 21, the window wafer 13 and wafer level vacuum package bonding are prepared. While or before the first dielectric layer 25 is removed, an incident surface area 15 may be disposed on the upper surface of the window wafer 13 and an exit surface area 16 may be disposed on the lower surface of the window wafer 13, specifically, the incident surface area 15 and the exit surface area 16 of different materials and/or structures may be selected according to the operating characteristics of the microbolometer 10, and the incident surface area 15 and the exit surface area 16 may be formed by using a plating film or a microstructure. The solder region 17 is also formed on the exit surface region 16 side, and specifically, the solder region 17 may be prepared by PVD, plating, or the like. The lower surface of the window wafer 13 is then bonded to the upper surface of the microbolometer 10 by solder regions 17, such that the window wafer 13 and the infrared detector form a first vacuum chamber 14. Specifically, the prepared window wafer 13 may be aligned with the substrate wafer 1 with the suspended microbolometer 10 and bonded in a bonding machine in a manner selected from dielectric bonding, metal bonding, etc. according to the solder region 17.

Wherein the first vacuum chamber 14 may be stacked by the solder regions 17, as shown in fig. 20. Alternatively, the recess may be formed by etching the lower surface of the window wafer 13, and the first vacuum chamber 14 may be formed by the recess, as shown in fig. 21. In addition, fig. 20 to 21 illustrate an example in which the second carrier wafer 22 is bonded to the lower surface of the substrate wafer 1, and after the window wafer 13 and the infrared detector chip wafer are formed into the first vacuum chamber 14, the first carrier wafer 21 is removed so that the conductive structure can be prepared on the lower surface of the substrate wafer 1.

Step 28: and preparing a conductive structure. That is, after the window wafer 13 and the infrared detector chip wafer are formed into the first vacuum chamber 14, a conductive structure may be provided on the lower surface of the substrate wafer 1. The specific process of setting the conductive structure may refer to the detailed description of the corresponding portion in the preparation method of the infrared detector chip wafer, which is not described herein again. Except that here the upper surface of the infrared detector chip wafer has a window wafer 13 bonded thereto. For the preparation of the first conductive structures 11, reference may be made to fig. 22 and 3, which illustrate a process of providing the first conductive structures 11 on the lower surface of the substrate wafer 1. For the preparation of the second conductive structure 12, reference may be made to fig. 23 and 4, which illustrate the process of providing the second conductive structure 12 on the lower surface of the substrate wafer 1.

The detailed description of the corresponding parts in the wafer-level packaged infrared detector provided in the application can be referred to for the specific structure of the wafer-level packaged infrared detector and the description of the related structures, and will not be repeated here.

The method for manufacturing the wafer-level packaged infrared detector provided in the embodiment of the present application may further include, before bonding the lower surface of the window wafer 13 and the upper surface of the infrared detector chip wafer together:

A getter area 18 is arranged on the emergent surface of the window wafer 13;

in bonding the lower surface of the window wafer 13 and the upper surface of the infrared detector chip wafer together, it may further include:

the getter area 18 is activated.

In the present application, before bonding the lower surface of the window wafer 13 to the upper surface of the infrared detector chip wafer, the incident surface area 15 is disposed on the upper surface of the window wafer 13, and the exit surface area 16 is disposed on the lower surface of the window wafer 13, and simultaneously or before or after, the getter area 18 may be disposed on the exit surface of the window wafer 13, specifically, the thin film getter area 18 may be formed on the lower surface side of the window wafer 13 by PVD or the like.

On the basis of the above, in the process of bonding the lower surface of the window wafer 13 and the upper surface of the infrared detector chip wafer together, the getter area 18 may be activated, so that the vacuum degree of the first vacuum cavity 14 reaches the working requirement of the microbolometer 10 by using the getter area 18.

The application further provides a method for manufacturing the pixel-level packaged infrared detector, referring to fig. 6-7, 8-12, 19 and 24-25, wherein fig. 24 shows a schematic view of providing a second dielectric layer, fig. 25 shows a schematic view of manufacturing a pixel packaging layer, fig. 26 shows a schematic view of manufacturing a first conductive structure after bonding the pixel packaging layer, and fig. 27 shows a schematic view of manufacturing a second conductive structure after bonding the pixel packaging layer. The method for manufacturing the pixel-level packaged infrared detector provided by the embodiment of the application can comprise the following steps:

a first dielectric layer 25 is arranged on the upper surface of the interlayer dielectric 3, and a micro-bolometer 10 is prepared on the first dielectric layer 25;

after the microbolometer 10 is fabricated on the first dielectric layer 25, before the conductive structure connected to the conductive material 7 in the via 5 is fabricated on the lower surface of the substrate, it may further include:

a second dielectric layer 26 is arranged on the upper surface of the first dielectric layer 25;

patterning the second dielectric layer 26 and the first dielectric layer 25 to remove the second dielectric layer 26 and the first dielectric layer 25 at the non-distributed microbolometer 10;

depositing a pixel packaging layer 19 on the upper surface of the infrared detector chip wafer, and removing a second dielectric layer 26 and a first dielectric layer 25 between the pixel packaging layer 19 and the infrared detector chip wafer, so that the pixel packaging layer 19 and the infrared detector chip wafer form second vacuum cavities 20 which are in one-to-one correspondence with the micro-bolometers 10; each microbolometer 10 is located within a corresponding second vacuum chamber 20.

The preparation method of the pixel-level packaged infrared detector is as follows:

step 31: as shown in fig. 8, an integrated circuit 4 is fabricated.

Step 32: as shown in fig. 9, the first carrier wafer 21 is temporarily bonded.

Step 33: as shown in fig. 10, the through hole 5 is etched.

Step 34: as shown in fig. 11, an insulating layer 6 is deposited.

Step 35: as shown in fig. 12, the through-hole 5 is filled. The implementation process of step 31 to step 35 is the same as the implementation process of step 11 to step 15, and will not be described here again.

Step 36: as shown in fig. 19, a microbolometer 10 was prepared. Specifically, after the first carrier wafer 21 is removed, a first dielectric layer 25 is provided on the upper surface of the interlayer dielectric 3, and the microbolometer 10 is fabricated on the first dielectric layer 25. Fig. 19 shows a schematic view of the microbolometer 10 prepared after removing the first carrier wafer 21 and bonding the second carrier wafer 22, specifically, after bonding the second carrier wafer 22, a first dielectric layer 25 may be disposed on the upper surface of the interlayer dielectric 3, and the microbolometer 10 may be prepared on the upper surface of the first dielectric layer 25.

Step 37: as shown in fig. 24, a second dielectric layer 26 is provided to form a double-layered sacrificial layer with the first dielectric layer 25. After the micro-bolometer 10 is prepared on the first dielectric layer 25, a second dielectric layer 26 is disposed on the upper surface of the first dielectric layer 25 to form a double-layer sacrificial layer with the first dielectric layer 25, so that the suspended micro-bolometer 10 can be formed conveniently.

Step 38: as shown in fig. 25, the pixel level is vacuum-packed. After the second dielectric layer 26 is disposed to form a dual sacrificial layer with the first dielectric layer 25, the second dielectric layer 26 and the first dielectric layer 25 may be patterned, and the second dielectric layer 26 and the first dielectric layer 25 at the non-distributed microbolometer 10 (i.e., the non-pixel region) may be etched to remove, that is, the dual sacrificial layer may be patterned to remove the dual sacrificial layer in the non-pixel region. Wherein the non-pixel area refers to an area where the microbolometer 10 is not disposed. Then, a pixel encapsulation layer 19 is deposited on the upper surface of the infrared detector chip wafer, and the second dielectric layer 26 and the first dielectric layer 25 (that is, the second dielectric layer 26 and the first dielectric layer 25 in the pixel area are removed) between the pixel encapsulation layer 19 and the infrared detector chip wafer are removed, so that a second vacuum cavity 20 which corresponds to each micro-bolometer 10 one by one and accommodates the corresponding micro-bolometer 10 is formed between the pixel encapsulation layer 19 and the infrared detector chip wafer.

It should be noted that, fig. 24 to 25 illustrate an example in which the second carrier wafer 22 is bonded to the lower surface of the substrate wafer 1, after the second vacuum cavities 20 corresponding to the microbolometers 10 one by one and accommodating the corresponding microbolometers 10 are formed between the pixel packaging layer 19 and the infrared detector chip wafer, the second carrier wafer 22 needs to be removed, so that the conductive structure is set on the lower surface of the substrate wafer 1.

Step 39: and preparing a conductive structure. That is, after forming the second vacuum chambers 20, which are in one-to-one correspondence with the respective microbolometers 10 and accommodate the corresponding microbolometers 10, between the pixel encapsulation layer 19 and the infrared detector chip wafer, a conductive structure may be disposed on the lower surface of the substrate wafer 1. The specific process of disposing the conductive structure may be referred to the detailed description of the corresponding portion in the method for manufacturing the infrared detector chip wafer, which is not described herein again. Except that here the upper surface of the infrared detector chip wafer is provided with a pixel encapsulation layer 19. For the preparation of the first conductive structures 11, reference may be made to fig. 26 and 6, which illustrate the process of preparing the first conductive structures 11 on the lower surface of the substrate wafer 1. For the preparation of the second conductive structure 12, reference may be made to fig. 27 and 7, which illustrate the process of preparing the second conductive structure 12 on the lower surface of the substrate wafer 1.

The specific structure of the pixel-level packaged infrared detector and the description of the related structure can be referred to the detailed description of the corresponding parts in the pixel-level packaged infrared detector provided in the application, and will not be repeated here.

Referring to fig. 25, fig. 28 to fig. 29, in which fig. 28 shows a schematic view of disposing a cover layer, fig. 29 shows a schematic view of disposing a release hole on the cover layer and releasing a first dielectric layer and a second dielectric layer in a pixel region, a method for manufacturing a pixel-level packaged infrared detector provided in the embodiment of the present application, depositing a pixel encapsulation layer 19 on a top surface of an infrared detector chip wafer, and removing the second dielectric layer 26 and the first dielectric layer 25 between the pixel encapsulation layer 19 and the infrared detector chip wafer, may include:

A cover layer 191 is arranged on the upper surface of the infrared detector chip wafer, and release holes 192 are arranged in the areas corresponding to the micro-bolometers 10 on the cover layer 191;

removing the second dielectric layer 26 and the first dielectric layer 25 between the pixel encapsulation layer 19 and the infrared detector through the release hole 192;

a sealing layer 193 is provided on the upper surface of the cover layer 191.

In this application, a specific process of depositing the pixel encapsulation layer 19 on the top surface of the infrared detector chip wafer and removing the second dielectric layer 26 and the first dielectric layer 25 between the pixel encapsulation layer 19 and the infrared detector chip wafer may be: 1) As shown in fig. 28, after etching to remove the second dielectric layer 26 and the first dielectric layer 25 at the non-distributed microbolometer 10, a cover layer 191 is deposited on the upper surface of the infrared detector chip wafer by CVD or the like, where the material of the cover layer 191 may be α -si; 2) As shown in fig. 29, release holes 192 are etched into the cap layer 191 on each pixel region, that is, release holes 192 are provided in the regions of the cap layer 191 corresponding to the respective microbolometers 10 for removal of the double-layer sacrificial layer in the cap layer 191. After the release hole 192 is provided, the second dielectric layer 26 and the first dielectric layer 25 between the pixel encapsulation layer 19 and the infrared detector chip wafer, that is, the second dielectric layer 26 and the first dielectric layer 25 in the pixel region, can be removed through the release hole 192; 3) As shown in fig. 25, a sealing layer 193 is provided on the upper surface of the cap layer 191 to form the pixel encapsulation layer 19 together with the cap layer 191 having the release holes 192. The material of the sealing layer 193 may be Ge, znS, or a combination of both.

The application also provides a preparation method of the metal-encapsulated or ceramic-encapsulated infrared detector, referring to fig. 8-12, 15-18 and 30-31, wherein fig. 30 shows a schematic diagram of yet another preparation of a microbolometer, and fig. 31 shows a schematic diagram of bonding a third carrier wafer. The embodiment of the application also provides a preparation method of the infrared detector with metal encapsulation or ceramic encapsulation, which can comprise the following steps:

bonding a third carrier wafer 27 on the upper surface of the first dielectric layer 25;

after the preparation of the conductive structure connected to the conductive material 7 in the via 5 on the lower surface of the substrate, it may further comprise:

removing the third carrier wafer 27 and removing the first dielectric layer 25;

the infrared detector chip wafer is arranged in the tube shell, and the conductive structure in the infrared detector chip wafer is connected with the conductive structure in the tube shell.

The preparation method of the infrared detector with the metal package or the ceramic package comprises the following steps:

step 41: as shown in fig. 8, an integrated circuit 4 is fabricated;

step 42: as shown in fig. 9, the first carrier wafer 21 is temporarily bonded.

Step 43: as shown in fig. 10, the through hole 5 is etched.

Step 44: as shown in fig. 11, an insulating layer 6 is deposited.

Step 45: as shown in fig. 12, the through-hole 5 is filled. The implementation process of step 41 to step 45 is the same as the implementation process of step 11 to step 15, and will not be described here again.

Step 46: as shown in fig. 30, a microbolometer 10 is prepared. Specifically, after the first carrier wafer 21 is removed, a first dielectric layer 25 is provided on the upper surface of the interlayer dielectric 3, and the microbolometer 10 is fabricated on the first dielectric layer 25. Fig. 30 illustrates an example in which the second carrier wafer 22 is not bonded to the lower surface of the substrate wafer 1. Of course, the microbolometer 10 may be fabricated by bonding the second carrier wafer 22 to the lower surface of the substrate wafer 1, and then preparing the microbolometer on the upper surface of the substrate wafer 1, as shown in fig. 19.

Step 47: as shown in fig. 31, a third carrier wafer 27 is bonded to the upper surface of the first dielectric layer 25. That is, after the microbolometer 10 is fabricated on the first dielectric layer 25, a three-wafer is bonded on the upper surface of the first dielectric layer 25 to protect the microbolometer 10 by temporary bonding, thereby preventing the microbolometer 10 from being affected or damaged in subsequent process steps. The manner of bonding the third carrier wafer 27 is the same as that of bonding the first carrier wafer 21 and the second carrier wafer 22, and will not be described here again.

Step 48: a conductive structure is prepared on the lower surface of the substrate wafer 1. The specific process of setting the conductive structure may refer to the detailed description of the corresponding portion in the preparation method of the infrared detector chip wafer, which is not described herein again. Except that here the top surface of the infrared detector chip wafer is provided with a first dielectric layer 25 and a third carrier wafer 27. For the preparation of the first conductive structure 11, reference may be made to fig. 15 and 16. For the preparation of the second conductive structure 12, reference can then be made to fig. 17 and 18.

Step 49: the third carrier wafer 27 and the first dielectric layer 25 are removed and metal or ceramic encapsulated. Specifically, after the conductive structure is obtained, the third carrier wafer 27 may be removed first, where the removing manner of the third carrier wafer 27 is the same as that of the first carrier wafer 21 and the third carrier wafer 27, and will not be described herein. Then, the first dielectric layer 25 is removed, and the infrared detector chip wafer is obtained. Then, the infrared detector chip wafer can be arranged in the tube shell, and the conductive structure in the infrared detector chip wafer is connected with a circuit in the tube shell.

The specific structure of the metal-encapsulated or ceramic-encapsulated infrared detector and the description of the related structure can be referred to the detailed description of the corresponding parts in the metal-encapsulated or ceramic-encapsulated infrared detector provided in the application, and will not be repeated here.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is inherent to. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In addition, the parts of the above technical solutions provided in the embodiments of the present application, which are consistent with the implementation principles of the corresponding technical solutions in the prior art, are not described in detail, so that redundant descriptions are avoided.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. The infrared detector chip wafer is characterized by comprising a substrate wafer (1), an epitaxial layer (2) arranged on the upper surface of the substrate wafer (1), an interlayer medium (3) arranged on the upper surface of the epitaxial layer (2), an integrated circuit (4) arranged in the interlayer medium (3), and a micro-bolometer (10) arranged on the upper surface of the interlayer medium (3) and connected with the integrated circuit (4);

the integrated circuit (4) is provided with a through hole (5) penetrating through the interlayer medium (3), the epitaxial layer (2) and the substrate wafer (1), the side wall of the through hole (5) is provided with an insulating layer (6), and the through hole (5) is filled with a conductive material (7) so that the integrated circuit (4) is connected with the conductive material (7);

the lower surface of the substrate wafer (1) is provided with a conductive structure connected with the conductive material (7) so that the integrated circuit (4) is connected with an external circuit through the conductive structure.

2. The infrared detector chip wafer as claimed in claim 1, characterized in that an adhesion barrier (8) between the insulating layer (6) and the conductive material (7) is also provided in the through-hole (5).

3. The infrared detector chip wafer as claimed in claim 2, characterized in that a seed layer (9) is further provided in the through-hole (5) between the adhesion barrier layer (8) and the conductive material (7).

4. The infrared detector chip wafer as claimed in claim 1, characterized in that the conductive structure comprises a first conductive structure (11) at the through hole (5);

alternatively, the conductive structure comprises a second conductive structure (12) extending from the through hole (5) to outside the through hole (5); the second conductive structures (12) are not connected.

5. The infrared detector chip wafer as set forth in claim 4, wherein the first conductive structure (11) comprises a first metallization layer (111), a first solder (112) located on a lower surface of the first metallization layer (111).

6. The infrared detector chip wafer as set forth in claim 4, wherein the second conductive structure (12) includes a first PI layer (121) located at a position other than at the through hole (5) on the lower surface of the substrate wafer (1), a second metallization layer (122) extending from at the through hole (5) to outside the through hole (5), a rewiring layer (125) located at a lower surface of the second metallization layer (122), a third metallization layer located at a predetermined region of a lower surface of the rewiring layer (125), a second solder (123) located at a lower surface of the third metallization layer, a second PI layer (124) located at a position where the second metallization layer (122) is not provided at a lower surface of the first PI layer (121), and a position where the second solder (123) is not provided at a lower surface of the rewiring layer (125);

The second metallization layer (122) located at the through hole (5) is connected with the conductive material (7), the second metallization layer (122) extending to the outside of the through hole (5) is located on the lower surface of the first PI layer (121), and the preset area is an area outside the corresponding area of the through hole (5).

7. The infrared detector chip wafer of claim 1, wherein the integrated circuit (4) comprises a CMOS region (41), a multilayer conductive circuit interconnect region (42), the CMOS region (41) comprising CMOS components therein, the multilayer conductive circuit interconnect region (42) comprising a multilayer conductive circuit interconnect layer for connecting the CMOS components to the microbolometer (10), each layer of the conductive circuit interconnect layer comprising a contact hole (421), a conductive layer (422) located at the contact hole (421);

wherein contact holes (421) in the conductive circuit interconnection layer at the bottom layer are connected with the CMOS component, contact holes (421) in the rest of the conductive circuit interconnection layers except the conductive circuit interconnection layer at the bottom layer are connected with conductive layers (422) in the conductive circuit interconnection layers at the next layer, the conductive layers (422) in the conductive circuit interconnection layers at the top layer are also connected with the microbolometer (10), and the conductive circuit interconnection layers at the top layer further comprise signal transmission conductive layers (423) connected with the conductive material (7).

8. An infrared detector, characterized in that the infrared detector is a wafer-level packaged infrared detector, and comprises an infrared detector chip wafer and a window wafer (13) bonded above the infrared detector chip wafer, wherein the infrared detector chip wafer and the window wafer (13) form a first vacuum cavity (14), and a microbolometer (10) in the infrared detector chip wafer is positioned in the first vacuum cavity (14).

9. The infrared detector as set forth in claim 8, wherein the window wafer (13) exit face further comprises a getter region (18).

10. An infrared detector, characterized in that the infrared detector is a pixel-level packaged infrared detector, comprising an infrared detector chip wafer according to any one of claims 1 to 7, and a pixel packaging layer (19) arranged on the upper surface of the infrared detector chip wafer; the pixel packaging layer (19) and the infrared detector chip wafer form second vacuum cavities (20) which are in one-to-one correspondence with the micro-bolometers (10) in the infrared detector chip wafer, and the micro-bolometers (10) are respectively positioned in the corresponding second vacuum cavities (20).

11. The infrared detector according to claim 10, characterized in that the pixel encapsulation layer (19) includes a cover layer (191) provided with a release hole (192) in a region corresponding to the microbolometer (10), and a sealing layer (193) located on an upper surface of the cover layer (191).

12. An infrared detector, characterized in that the infrared detector is a metal-encapsulated or ceramic-encapsulated infrared detector, comprising a tube shell, and the infrared detector chip wafer as claimed in any one of claims 1 to 7 arranged in the tube shell, wherein the infrared detector chip wafer is connected with a circuit in the tube shell through a conductive structure therein.