CN220652014U - Semiconductor packaging structure - Google Patents

Abstract

The application provides a semiconductor packaging structure, including: a first gasket including a convex portion; at least two first nanowires formed on the convex portions of the first pad; a second liner including a recess facing the first liner, the recess defining an inner side surface of the second liner, the convex portion of the first liner being received in the recess of the second liner; at least two second nanowires extending from an inner side surface of the second pad and contacting the first nanowires. Namely, the bonding structure similar to a magic tape is formed by the first nanowire and the second nanowire, the first nanowire and the second nanowire are accommodated in the concave part of the second gasket to form a boundary, and further the first nanowire and the second nanowire can be directly and tightly contacted together, the bonding structure formed by good contact between the first nanowire and the second nanowire can provide good product performance, thinning of the product can be realized, various risks possibly occurring in a welding process are avoided, and the bonding structure has good electrical performance due to a short electrical path.

Description

Semiconductor packaging structure

Technical Field

The application relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure.

Background

In the process of bonding two sets of nanowires (nanowires) of copper to copper, the nanowires on the two pads are brought into contact with each other by pressing to make an electrical connection. After the two groups of nanowires are contacted, the positions of the two groups of nanowires are limited by the lack of tension between the two groups of nanowires, so that after the subsequent pressurization is released, the two groups of nanowires can spring away from each other and are not contacted, namely, the electrical property between the two groups of nanowires is reduced. In addition, after the pressurization is released, disconnection may occur at the edges of the two sets of pads due to positional displacement between the two pads, or warpage may occur in the two pads. This is because after releasing the pressure, no boundary is established at the edge of the pad and the two sets of nanowires are scattered.

As shown particularly in fig. 1, the pressurization shown in the left portion of fig. 1 brings the first set of nanowires 40 and the second set of nanowires 50 into contact with each other. The right part of fig. 1 shows that after releasing the pressure, the first set of nanowires 40 and the second set of nanowires 50 are separated due to lack of tension, which results in poor electrical properties of the product.

Disclosure of Invention

The application provides a semiconductor packaging structure.

In a first aspect, the present application proposes a semiconductor package structure, comprising:

a first gasket including a convex portion;

at least two first nanowires formed on the convex portions of the first pad;

a second liner including a recess facing the first liner, the recess defining an inside surface of the second liner, the convex portion of the first liner being received in the recess of the second liner;

at least two second nanowires extending from an inner side surface of the second pad and contacting the first nanowires.

In some alternative embodiments, the inner side surface of the second liner includes an inner side bottom surface furthest from the first liner, and at least one of the first nanowires includes a first portion proximate to the first liner protrusion, the first portion extending from the first liner protrusion in a first direction that is directed from the first liner protrusion outer surface toward the second liner inner side bottom surface.

In some alternative embodiments, at least one of the second nanowires includes a second portion proximate the second liner medial surface, the second portion extending from the second liner medial surface in a second direction different from the first direction, the second direction pointing from the second liner medial surface toward the second liner medial bottom surface.

In some alternative embodiments, the length of each of the first nanowires is different, and the length of each of the second nanowires is different.

In some alternative embodiments, the first pad includes a bottom surface distal to the second pad, and the length of a first nanowire of each of the first nanowires that is closer to the bottom surface of the first pad is shorter.

In some alternative embodiments, the first nanowire forms a connection with the second nanowire.

In some alternative embodiments, the portion of the link closer to the bottom surface of the first pad has a lower line density.

In some alternative embodiments, a portion of at least one of the second nanowires does not contact the first nanowire.

In some alternative embodiments, the recess of the second liner is smaller in diameter as it is closer to the bottom surface of the second liner.

In some alternative embodiments, the semiconductor package structure further includes:

and a first protective layer coating the first pad, the first nanowire, the second pad, and the second nanowire.

In order to solve two sets of nanowires from top to bottom and combine the contact back each other, restrict each other because of lack pulling force each other between two sets of nanowires, and then remove the problem that two sets of nanowires bullet open each other and do not contact after the pressurization in follow-up, this application provides a semiconductor packaging structure, includes: a first gasket including a convex portion; at least two first nanowires formed on the convex portions of the first pad; a second liner including a recess facing the first liner, the recess defining an inner side surface of the second liner, the convex portion of the first liner being received in the recess of the second liner; at least two second nanowires extending from an inner side surface of the second pad and contacting the first nanowires. The semiconductor packaging structure can achieve the following technical effects:

first, the first nanowire is formed at the convex portion of the first pad, and the second nanowire is formed at the inner side surface of the concave portion of the second pad having a recess (i.e., cavity), and the convex portion of the first pad is accommodated in the concave portion of the second pad, the bonding structure formed by the first nanowire and the second nanowire is contacted together like a group of 'magic tapes', the first nanowire and the second nanowire are accommodated in the concave portion of the second pad, a boundary is formed, and further the first nanowire and the second nanowire can be directly and tightly contacted together, and the bonding structure formed by good contact between the first nanowire and the second nanowire can provide good product performance.

Secondly, the whole semiconductor packaging structure does not need a welding process, namely a connecting piece (such as a solder ball) needed in the welding process is not needed, so that the thickness of a product is reduced, and the thinning of the product is realized.

Third, various risks that may occur during the welding process are also avoided due to the lack of a welding process, including, for example, but not limited to, the following welding risks: bridging (bridging), cracking (crack), cold joining (cold joint), high resistance (high resistance), and the like, require the same size of pad due to wetting problems.

Fourth, since the first nanowire and the second nanowire are in direct contact, the electrical path is shorter, and thus, the electrical performance is better.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings, in which:

FIG. 1 is a schematic view of a longitudinal cross-sectional structure of a product during and after pressurization and release of pressure during the process of bonding two groups of nanowires to each other in the prior art;

fig. 2 is a schematic longitudinal sectional structure of one embodiment 2a of a semiconductor package structure according to the present application;

fig. 3 is an enlarged partial schematic view of a rectangular dotted frame in the semiconductor package structure 2a shown in fig. 2;

fig. 4 is a partially enlarged schematic view of the semiconductor package 2a shown in fig. 2 after the first pad 11 is turned 180 °.

Fig. 5 shows an exploded view of the first pad 11 and the second pad 13 in the semiconductor package structure 2a shown in fig. 2;

fig. 6 shows three possible top views of the second liner 13 in the exploded view of fig. 5 after removal of the first liner 11;

fig. 7 is a schematic dimensional view of the semiconductor package 2a shown in fig. 2;

fig. 8, 9, 10, 11, 12 and 13 are schematic longitudinal sectional structures of one embodiment 8a, 9a, 10a, 11a, 12a and 13a of a semiconductor package structure according to the present application, respectively;

fig. 14 to 34 are schematic views showing a manufacturing step of an embodiment 2a of the semiconductor package structure of the present application, respectively.

Reference numerals/symbol description:

11-a first liner; 111-convex part; 11 b-a first bottom surface; 12-a first nanowire; 121-a first portion of a first nanowire; 13-a second liner; 131-a recess of a second liner; 13 a-an inner side surface of a second liner; 13 b-an inner bottom surface of the second liner; 14-a second nanowire; 141-the second nanowire 14 is adjacent to a second portion of the second liner 13; 15-a first protective layer; 16-a first substrate; 17-a first chip; 17 a-an active face of the first chip; 18-a first circuit layer; d1—a first direction; d2—a second direction; 19-a second substrate; 20-a second circuit layer; 21-a second protective layer; 22-a second chip; 23-a third pad; 24-a third substrate; 25-a third wiring layer; 26-a first seed layer; 27-a first metal layer; 28-photoresist; 29-a second metal layer; 30-a second seed layer; 40-a first set of nanowires; 50-a second set of nanowires.

Detailed Description

The technical problems to be solved by the present application and the technical effects to be produced will be readily apparent to those skilled in the art from the descriptions of the present application, which are described in the following detailed description of the present application with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the utility model and are not limiting of the utility model. In addition, for convenience of description, only a portion related to the related utility model is shown in the drawings.

It should be readily understood that the meanings of "on," "above," and "above" in this application should be interpreted in the broadest sense so that "on" means not only "directly on" but also "on" including intermediate components or layers that exist therebetween.

Further, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "layer" as used herein refers to a portion of material that includes regions having a certain thickness. The layers may extend over the entire underlying or overlying structure, or may have a degree less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes therebetween. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate (substrate) may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, and/or thereon. One layer may comprise multiple layers. For example, the semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

The term "substrate" as used herein refers to a material to which subsequent layers of material are added. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire chips, or the like. Further alternatively, the substrate may have a semiconductor device or a circuit formed therein.

It should be noted that, the structures, proportions, sizes, etc. shown in the drawings are merely used in conjunction with the descriptions of the embodiments and should not be construed as limiting the applicable limitations of the present application, so that any modification, variation of proportions, or adjustment of sizes of structures, proportions, etc. which are not intended to affect the efficacy of the present application or the objects achieved, are still within the scope of what is disclosed herein. Also, the terms "upper", "first", "second", and "a" and "an" as used in the present specification are merely for descriptive purposes and are not intended to limit the scope of the utility model in which the utility model may be practiced or their relative relationships may be altered or modified without materially altering the technical context.

It should be further noted that, in the embodiment of the present application, the corresponding longitudinal section may be a section corresponding to a front view direction, the corresponding transverse section may be a section corresponding to a right view direction, and the corresponding horizontal section may be a section corresponding to an upper view direction.

In addition, embodiments and features of embodiments in this application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

The present application proposes a semiconductor package structure, referring to fig. 2, fig. 2 is a schematic longitudinal sectional view of an embodiment 2a of the semiconductor package structure according to the present application.

As shown in fig. 2, the semiconductor package structure 2a may include a first pad 11, at least two first nanowires 12, a second pad 13, and at least two second nanowires 14. Wherein:

the first gasket 11 includes a convex portion 111.

The first nanowire 12 is formed on the convex portion 111 of the first pad 11.

The second gasket 13 comprises a recess 131 facing the first gasket 11, the recess 131 defining an inner side surface 13a of the second gasket 13. The convex portion 111 of the first gasket 11 is partially accommodated in the concave portion 131 of the second gasket 13.

The second nanowire 14 extends from the inner side surface 13a of the second pad 13 and is in contact with the first nanowire 12.

As shown in fig. 2, the inner side surface 13a of the second liner 13 includes an inner side bottom surface 13b furthest from the first liner 11.

In some alternative embodiments, referring to fig. 3, fig. 3 is an enlarged partial schematic view of a rectangular dashed box in the semiconductor package structure 2a shown in fig. 2, and as shown in fig. 3, the inner side surface of the second pad 13 includes an inner side bottom surface 13b farthest from the first pad 11, and at least one first nanowire 12 includes a first portion 121 near the convex portion 111 of the first pad 11, the first portion 121 extending from the convex portion 111 of the first pad 11 along a first direction D1, and the first direction D1 pointing from the outer surface of the convex portion 111 of the first pad 11 toward the inner side bottom surface 13b of the second pad 13.

In some alternative embodiments, as shown in fig. 3, the at least one second nanowire 14 comprises a second portion 141 near the inner side surface of the second liner 13, the second portion 141 extending from the inner side surface of the second liner 13 in a second direction D2 different from the first direction D1, the second direction D2 pointing from the inner side surface of the second liner 13 towards the inner bottom surface 13b of the second liner 13.

In some alternative embodiments, as shown in fig. 2, the lengths of the first nanowires 12 may all be different, as may the lengths of the second nanowires 14.

In some alternative embodiments, referring to fig. 4, fig. 4 is an enlarged partial schematic view of the semiconductor package 2a shown in fig. 2 after the first pad 11 is turned 180 °. As shown in fig. 4, the first pad 11 may include a first bottom surface 11b distant from the second pad 13, and the length of the first nanowire 12, which is closer to the first bottom surface 11b, among the first nanowires 12 is shorter. Specifically, the longer the length of the first nanowire 12 is, the shorter the length of the first nanowire 12 is, which is, the closer to the upper portion in fig. 4 (i.e., relatively, the lower portion in fig. 4 is the first bottom surface 11 b). This is because the first nanowire 12 farther from the first bottom surface 11b contacts the second nanowire 14 earlier in the manufacturing process, the length of the first nanowire 12 farther from the first bottom surface 11b is longer, and thus the cross strength after sintering of the first nanowire 12 farther from the first bottom surface 11b is greater. However, since the length of the first nanowire 12 near the first bottom surface 11b is short, a reaction force from the edge of the recess 131 of the second pad 13 can be avoided.

In some alternative embodiments, as shown in fig. 2, the first nanowire 12 and the second nanowire 14 may form a connection.

Alternatively, the portion of the line density formed by the first nanowire 12 and the second nanowire 14 is lower the closer the connection is to the first bottom surface 11 b.

In some alternative embodiments, as shown by the oval dashed box in fig. 2, a portion of the at least one second nanowire 14 does not contact the first nanowire 12.

In some alternative embodiments, the closer the recess 131 of the second liner 13 is to the inside bottom surface 13b of the second liner 13, the smaller the aperture.

In some alternative embodiments, as shown in fig. 2, the semiconductor package 2a may further include a first protective layer 15. Wherein the first protection layer 15 encapsulates the first pad 11, the first nanowire 12, the second pad 13, and the second nanowire 14.

In an alternative embodiment, as shown in fig. 2, the semiconductor package 2a may further include a first wiring layer 18. The second pad 13 may be partially embedded in the first circuit layer 18, and the first protective layer 15 covers the first circuit layer 18.

In an alternative embodiment, as shown in fig. 2, the semiconductor package 2a may further include a first substrate 16, and the first circuit layer 18 may be disposed on the first substrate 16.

In some alternative embodiments, as shown in fig. 2, the semiconductor package 2a may further include a first chip 17, and the first pad 11 is disposed on an active surface 17a of the first chip 17.

In some alternative embodiments, referring to fig. 5, fig. 5 shows an exploded view of the first pad 11 and the second pad 13 in the semiconductor package 2a shown in fig. 2. As shown in fig. 5, the second gasket 13 may include a shoulder 133, a ramp portion 134, and a bottom 135 disposed horizontally.

In some alternative embodiments, referring to fig. 6, fig. 6 shows three possible top views of the second liner 13 in the exploded view shown in fig. 5 after removal of the first liner 11. As shown in fig. 6, the top view of the shoulder 133, ramp portion 134, and bottom 135 of the second liner 13 may form a rectangular ring, a circular ring, or a multi-layered rectangular ring.

Referring now to fig. 7, fig. 7 is a schematic dimensional view of the semiconductor package 2a shown in fig. 2.

As shown in fig. 7, wherein:

the PBW is the maximum outer diameter of the first bottom surface 11b, and the PBW has a value ranging from 2 micrometers to 1000 micrometers.

CBW is the maximum outer diameter of the second pad 13 contacting the outer surface of the first wiring layer 18. CBW ranges from 2 microns to 1000 microns.

The ratio of PBW divided by CBW ranges from 1 to 2, which facilitates the bonding of the first pad 11 to the second pad 13, i.e. the recess space of the second pad 13 is sufficient to accommodate the protrusion 111 of the first pad 11.

θp is an angle between the outer side surface of the convex portion 11 of the first liner 11 and the side plane, and the value of θp ranges from 10 ° to 80 °.

θc is an angle between the outer surface of the second liner 13 and the horizontal plane, and the value of θp ranges from 10 ° to 80 °.

IG is the distance between the first bottom surface 11b and the upper surface of the recess 131 of the second gasket. IG is 50 microns or less.

PLT is the thickness of the second metal layer 29 on the surface of the first liner 11, and the PLT has a value ranging from 1 micron to 20 microns.

CLT is the thickness of the second liner 13, and the CLT has a value ranging from 1 micron to 20 microns.

The semiconductor packaging structure provided by the application has the advantages that the first nanowire 12 is formed on the convex part 111 of the first liner 11, the second nanowire 14 is formed on the inner side surface 13a of the concave part 131 of the second liner 13, the convex part 111 of the first liner 11 is partially accommodated in the concave part 131 of the second liner 13, the bonding structure formed by the contact of the first nanowire 12 with the second nanowire 14 can provide good product performance, the electric path is shorter, the product thickness is thinner, and the risk possibly generated in the welding process is avoided.

Referring to fig. 8, fig. 8 is a schematic longitudinal sectional structure of another embodiment 8a of a semiconductor package structure according to the present application. 8a is a semiconductor package structure similar to that of 2a, except that: the first circuit layer 18 in the semiconductor package 2a is disposed over the first substrate 16, and as shown in fig. 8, the first circuit layer 18 in the semiconductor package 8a is embedded in the first substrate 16.

Referring to fig. 9, fig. 9 is a schematic longitudinal sectional structure of another embodiment 9a of a semiconductor package structure according to the present application. 9a is a semiconductor package structure similar to that of fig. 2a, except that: the active surface 17a of the first chip 17 in the semiconductor package 2a is provided with a third pad 23, and the first pad 11 is disposed on the third pad 23. As shown in fig. 9, the first pad 11 in the semiconductor package 9a is disposed on the second circuit layer 20 on the second substrate 19, and is electrically connected to the second substrate 19 through the second circuit layer 20.

In addition, in the semiconductor package 2a, the second pad 13 is partially embedded in the first wiring layer 18, and the first wiring layer 18 is disposed on the first substrate 16. In the semiconductor package 9a, as shown in fig. 9, the second pad 13 is partially embedded in the second protective layer 21, and the second pad 13 contacts the third pad 23 disposed on the second chip 22 and electrically connects the second chip 22 through the third pad 23.

Referring to fig. 10, fig. 10 is a schematic longitudinal sectional structure view of another embodiment 10a of a semiconductor package structure according to the present application. 10a is a semiconductor package structure similar to 9a except that: the second pad 13 in the semiconductor package 10a contacts the third wiring layer 25 disposed on the third substrate 24.

Referring to fig. 11, fig. 11 is a schematic longitudinal sectional structure of another embodiment 11a of a semiconductor package structure according to the present application. 11a is a semiconductor package structure similar to 9a, except that: the second circuit layer 20 in the semiconductor package 11a is disposed on the active surface of the first chip 17, so that signal connection between the first chip 17 and the second chip 22 can be achieved through the second circuit layer 20, the first pad 11, the first nanowire 12, the second nanowire 14, the second pad 13, and the third pad 23 in sequence.

Referring to fig. 12, fig. 12 is a schematic longitudinal sectional structure of another embodiment 12a of a semiconductor package structure according to the present application. 12a is a semiconductor package structure similar to that of fig. 2a, except that: the semiconductor package 12a includes two sets of first pads 11, first nanowires 12, second pads 13, and second nanowires 14, and the two second pads 13 are partially embedded in the same first circuit layer 18, but the two first pads 11 are electrically connected to separate third pads 23, respectively.

Referring to fig. 13, fig. 13 is a schematic longitudinal sectional structure of another embodiment 13a of a semiconductor package structure according to the present application. 13a is a semiconductor package structure similar to 12a, and the semiconductor package structure 13a also includes two groups of first pads 11, first nanowires 12, second pads 13 and second nanowires 14, where the two second pads 13 are respectively partially embedded in different first circuit layers 18, and the two first pads 11 are electrically connected to the same third pad 23.

Referring to fig. 14-34, fig. 14-34 are schematic views of the manufacturing steps of one embodiment 2a of a semiconductor package structure according to the present application, respectively.

Referring to fig. 14, a chip first chip 17 is provided.

The active surface 17a of the first chip 17 is provided with a third pad 23, and the outer surface of the third pad 23 is provided with a first seed layer 26.

Referring to fig. 15, a first metal layer 27 is electroplated on the upper and outer sides of the first seed layer 26 to encapsulate the first seed layer 26 and the active surface 17a of the first chip 17.

Referring to fig. 16, after laminating a photoresist 28 on the surface of the first metal layer 27, photolithography is performed to expose a portion of the first metal layer 27.

Referring to fig. 17, the first metal layer 27 is etched to form the first pad 11 as shown in fig. 18, and the photoresist 28 is removed.

Referring to fig. 19, the photoresist 28 is laminated again such that the laminated photoresist 28 encapsulates the first seed layer 26, the active surface 17a of the first chip 17, and the first pad 11, and then photolithography exposes the top of the first pad 11.

Referring to fig. 20, a second metal layer 29 is formed on top of the exposed first pad 11.

Referring to fig. 21, the second metal layer 29 is etched to form at least two first nanowires 12 in the second metal layer 29.

Referring to fig. 22, photoresist 28 is removed.

Referring to fig. 23, the first seed layer 26 of the surface is etched away.

To this end, the first pad 11 and the first nanowire 12 have been formed.

Referring to fig. 24, a first substrate 16 is provided, and a first circuit layer 18 is disposed on a surface of the first substrate 16.

Referring to fig. 25, a photoresist 28 is laminated on the surfaces of the first wiring layer 18 and the first substrate 16.

Referring to fig. 26, the photoresist 28 is post-developed and then lithographically exposed to expose portions of the first circuit layer 18.

Referring to fig. 27, the exposed first circuit layer 18 is etched to form recesses in the first circuit layer 18, then the photoresist 28 is removed, and finally a second seed layer 30 is formed on the surface of the first circuit layer 18.

Referring to fig. 28, a photoresist 28 is laminated on the surface of the second seed layer 30.

Referring to fig. 29, the photoresist 28 is subjected to post-development photolithography to expose a portion of the second seed layer 30, and then a second liner 13 is formed on the exposed surface of the second seed layer 30.

Referring to fig. 30, the second pad 13 is etched to form the second nanowire 14.

Referring to fig. 31, the surface second seed layer 30 is removed.

Referring to fig. 32, the structure obtained after fig. 21 is inverted and then bonded to the structure obtained after fig. 30.

Referring to fig. 33, heating is performed such that the first nanowire 12 and the second nanowire 14 are sintered to form a connection.

Referring to fig. 34, the underfill is filled to form the first protection layer 15.

While the present application has been described and illustrated with reference to particular embodiments thereof, the description and illustration is not intended to be limiting. It will be apparent to those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments thereof without departing from the true spirit and scope of the application as defined by the appended claims. The illustrations may not be drawn to scale. There may be a distinction between technical reproduction and actual implementation in this application due to variables in the manufacturing process, etc. Other embodiments of the present application not specifically described may exist. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present application. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present application. Thus, unless specifically indicated herein, the order and grouping of operations is not a limitation of the present application.

Claims (10)

1. A semiconductor package structure, comprising:

a first gasket including a convex portion;

at least two first nanowires formed on the convex portions of the first pad;

a second liner including a recess facing the first liner, the recess defining an inside surface of the second liner, the convex portion of the first liner being received in the recess of the second liner;

at least two second nanowires extending from an inner side surface of the second pad and contacting the first nanowires.

2. The semiconductor package according to claim 1, wherein the inner side surface of the second liner includes an inner side bottom surface furthest from the first liner, at least one of the first nanowires includes a first portion proximate to the first liner protrusion, the first portion extending from the first liner protrusion in a first direction that is directed from the first liner protrusion outer surface toward the second liner inner side bottom surface.

3. The semiconductor package according to claim 2, wherein at least one of the second nanowires includes a second portion proximate the second liner inner side surface, the second portion extending from the second liner inner side surface in a second direction different from the first direction, the second direction pointing from the second liner inner side surface toward the second liner inner side bottom surface.

4. The semiconductor package according to claim 1, wherein the length of each of the first nanowires is different and the length of each of the second nanowires is different.

5. The semiconductor package according to claim 1, wherein the first pad includes a bottom surface remote from the second pad, and wherein a length of a first nanowire of each of the first nanowires that is closer to the bottom surface of the first pad is shorter.

6. The semiconductor package according to claim 1, wherein the first nanowire and the second nanowire form a connection.

7. The semiconductor package according to claim 6, wherein a portion of the connection member closer to the bottom surface of the first pad has a lower line density.

8. The semiconductor package according to claim 1, wherein at least one of the first

Portions of the two nanowires do not contact the first nanowire.

9. The semiconductor package according to claim 1, wherein the recess of the second pad has a smaller aperture closer to a bottom surface of the second pad.

10. The semiconductor package according to claim 1, further comprising:

and a first protective layer coating the first pad, the first nanowire, the second pad, and the second nanowire.