CN220342210U - National standard fast and slow charging connection signal CC2/CC wake-up and dormancy unit - Google Patents

Abstract

The embodiment of the utility model provides a national standard fast and slow charging connection signal CC2/CC wake-up and sleep unit, and belongs to the technical field of new energy automobile electronics. The unit comprises: the power supply LDO circuit, the main power supply wake-up buffer circuit, the control circuit, the analog switch circuit, the conversion circuit, the reference source, the reference reset circuit and the voltage division acquisition circuit. The power supply LDO circuit is used for providing +5V direct current voltage; the first end of the main power supply wake-up buffer circuit is connected with the main power supply circuit; one end of the control circuit is connected with the second end of the main power supply wake-up buffer circuit; one end of the analog switch circuit is connected with the other end of the control circuit; the first end of the conversion circuit is connected with the other end of the analog switch circuit, and the second end of the conversion circuit is connected with the third end of the main power wake-up buffer circuit; the reference source and the reference reset circuit are connected with the third end of the conversion circuit; the voltage division acquisition circuit is connected with the fourth end of the conversion circuit.

Description

National standard fast and slow charging connection signal CC2/CC wake-up and dormancy unit

Technical Field

The utility model relates to the technical field of new energy automobile electronics, in particular to a national standard fast and slow charging connection signal CC2/CC wake-up and sleep unit.

Background

With the increasing strictness of global environmental protection policies of various countries and the increasing awareness of energy resources, new energy automobiles are rapidly popularized, and become one of the most potential vehicles in new times. In terms of charging speed selection, the charging of the new energy automobile is divided into quick charging and slow charging, but no matter the quick charging or the slow charging is carried out, a pull-down resistor is required to be arranged in the charging gun, so that whether the charging gun is connected with a charging socket of the power battery or not is confirmed by detecting a resistance signal of the pull-down resistor in the charging process of the new energy automobile.

The traditional resistor voltage division network is used for collecting the wake-up of the national standard fast and slow charge CC2/CC signals, the voltage division network is converted into switching value to supply the MCU interrupt signal in dormancy, the circuit is simple, but the MCU needs to supply power for a long time and is in a low-power-consumption dormancy state, and the system power consumption is difficult to be further reduced below an ideal value. Especially, when the MCU works with low power consumption, hardware dog feeding work is required to be continuously carried out, and the sleep power consumption of the system is further increased.

Disclosure of Invention

The embodiment of the utility model aims to provide a national standard fast and slow charging connection signal CC2/CC wake-up and sleep unit. The BMS dormancy power consumption when this unit can reduce the vehicle by a wide margin and stew, can effectively prolong vehicle time of stewing, improve customer and use experience satisfaction, reduce cost is convenient for promote on a large scale.

In order to achieve the above objective, an embodiment of the present utility model provides a national standard fast and slow charging connection signal CC2/CC wake-up and sleep unit, the unit comprising:

the power supply LDO circuit is used for providing +5V direct current voltage;

a main power supply circuit;

the main power supply wake-up buffer circuit is connected with the first end of the main power supply wake-up buffer circuit;

one end of the control circuit is connected with the second end of the main power supply wake-up buffer circuit;

the analog switch circuit is connected with one end of the control circuit;

the first end of the conversion circuit is connected with the other end of the analog switch circuit, and the second end of the conversion circuit is connected with the third end of the main power wake-up buffer circuit;

a reference source and a reference reset circuit, the reference source and the reference reset circuit being connected to a third terminal of the conversion circuit;

and the partial pressure acquisition circuit is connected with the fourth end of the conversion circuit.

Optionally, the power LDO circuit includes:

a first anti-reflection diode, the anode of which is used for being connected to a normal fire KL30 line;

one end of the LDO chip is connected with the cathode of the anti-reflection diode, and the second end of the LDO chip is used for outputting +5V direct current voltage;

one end of the first capacitor is connected with the cathode of the anti-reflection diode, and the other end of the first capacitor is grounded;

and one end of the second capacitor is connected with the other end of the LDO chip, and the other end of the second capacitor is grounded.

Optionally, the reference source and reference reset circuit includes:

one end of the first resistor is connected with +5V direct current voltage;

one end of the second resistor is connected with the other end of the first resistor, and the other end of the second resistor is grounded;

the D electrode of the MOS tube is connected with the other end of the second resistor, and the S electrode of the MOS tube is grounded;

one end of the fourth resistor is connected with the G pole of the MOS tube, and the other end of the fourth resistor is grounded;

one end of the fourth capacitor is connected with the G pole of the MOS tube, and the other end of the fourth capacitor is grounded;

one end of the fifth resistor is connected with the G pole of the MOS tube, and the other end of the fifth resistor is connected with the MCU control port;

one end of the sixth resistor is connected with the D pole of the MOS tube, and the other end of the sixth resistor is connected with the conversion circuit;

and one end of the sixth capacitor is connected with the other end of the sixth resistor, and the other end of the sixth capacitor is grounded.

Optionally, the voltage division acquisition circuit includes:

a twelfth resistor, wherein one end of the twelfth resistor is used for being externally connected to +5V direct current voltage;

one end of the signal resistor is connected with the other end of the twelfth resistor, and the other end of the signal resistor is grounded;

one end of the seventh resistor is connected with one end of the signal resistor, and the other end of the seventh resistor is connected with the conversion circuit;

and one end of the seventh capacitor is connected with the other end of the seventh resistor, and the other end of the seventh capacitor is grounded.

Optionally, the conversion circuit includes:

the non-inverting input end of the comparator is connected with the reference source and the reference reset circuit, and the inverting input end of the comparator is connected with the voltage division acquisition circuit;

one end of the eighth resistor is connected with the output end of the comparator, and the other end of the eighth resistor is connected with the main power supply wake-up buffer circuit;

and one end of the eighth capacitor is connected with the other end of the eighth resistor, and the other end of the eighth capacitor is grounded.

Optionally, the analog switching circuit includes:

the input end of the single-channel SPST analog switch is connected with the voltage division acquisition circuit;

one end of the ninth resistor is connected with the output end of the single-channel SPST analog switch, and the other end of the ninth resistor is connected with one end of the control circuit;

and one end of the ninth capacitor is connected with the other end of the ninth resistor, and the other end of the ninth capacitor is grounded.

Optionally, the main power wake-up buffer circuit includes:

the first end of the D-type trigger is connected with the conversion circuit;

a first output or gate diode, the anode of the first output or gate diode being connected to the second end of the D-type flip-flop, the cathode of the first output or gate diode being connected to the main power circuit;

a second output or gate diode, the anode of the second output or gate diode being connected to the control circuit, the cathode of the first output or gate diode being connected to the cathode of the second output or gate diode;

a third output or gate diode, the cathode of the third output or gate diode being connected to the cathode of the second output or gate diode, the anode of the third output or gate diode being connected to the normally-on KL15 line;

one end of the tenth resistor is connected with the control circuit, and the other end of the tenth resistor is connected with the third end of the D-type trigger;

a tenth capacitor, one end of which is connected with the other end of the tenth resistor, and the other end of which is grounded;

and one end of the eleventh resistor is connected with one end of the tenth resistor, and the other end of the eleventh resistor is grounded.

Optionally, the main power circuit includes:

the DCDC power supply is output as a VCC power supply network;

and the cathode of the second anti-reflection diode is connected with a normal fire KL30 circuit, and the anode of the second anti-reflection diode is connected with the input end of the DCDC power supply.

Through the technical scheme, the national standard fast and slow charging connection signal CC2/CC wake-up and sleep unit provided by the utility model is composed of a power supply LDO circuit, a main power supply wake-up buffer circuit, a control circuit, an analog switch circuit, a conversion circuit, a reference source, a reference reset circuit and a voltage division acquisition circuit. In this unit, the control circuit is powered by the main power wake-up buffer circuit, and whether the main power wake-up buffer circuit is powered or not depends on whether the CC2/CC signal is input or not, so that the control circuit does not need to continuously detect the CC2/CC signal. Compared with the mode of directly detecting the CC2/CC signal by the controller in the prior art, the national standard fast and slow charging connection signal CC2/CC wake-up and sleep unit provided by the utility model can sleep under the condition of no wake-up, thereby achieving the purpose of energy conservation.

Drawings

FIG. 1 is a block diagram of a national standard fast and slow charge connection signal CC2/CC wake-up and sleep unit according to one embodiment of the present utility model;

FIG. 2 is a schematic diagram of a power LDO circuit in a national standard fast and slow charge connection signal CC2/CC wake-up and sleep cell according to one embodiment of the present utility model;

FIG. 3 is a schematic diagram of a reference source and reference reset circuit in a national standard fast and slow charge connection signal CC2/CC wake-up and sleep unit according to one embodiment of the present utility model;

FIG. 4 is a schematic diagram of a switching circuit in a national standard fast and slow charge connection signal CC2/CC wake-up and sleep cell according to one embodiment of the present utility model;

FIG. 5 is a schematic diagram of a primary power wake-up buffer circuit in a national standard fast and slow charge connection signal CC2/CC wake-up and sleep unit according to one embodiment of the present utility model;

FIG. 6 is a schematic diagram of an analog switch circuit in a national standard fast and slow charge connection signal CC2/CC wake-up and sleep cell according to one embodiment of the present utility model;

FIG. 7 is a schematic diagram of a partial pressure acquisition circuit in a national standard fast and slow charge connection signal CC2/CC wake-up and sleep unit according to one embodiment of the present utility model;

FIG. 8 is a schematic diagram of a main power circuit in a national standard fast and slow charge connection signal CC2/CC wake-up and sleep cell according to one embodiment of the present utility model;

FIG. 9 is a schematic diagram of a control circuit in a national standard fast and slow charge connection signal CC2/CC wake-up and sleep unit according to one embodiment of the present utility model;

fig. 10 is a schematic diagram of an overall circuit of a national standard fast and slow charge connection signal CC2/CC wake-up and sleep unit according to an embodiment of the present utility model.

Description of the reference numerals

1. Power LDO circuit 2 and main power supply circuit

3. Main power supply awakening buffer circuit 4 and control circuit

5. Analog switch circuit 6 and conversion circuit

7. Reference source and reference reset circuit 8 and partial pressure acquisition circuit

R1, a first resistor R2 and a second resistor

R3/RC, signal resistor R4 and fourth resistor

R5, fifth resistor R6 and sixth resistor

R7, seventh resistor R8, eighth resistor

R9, a ninth resistor R10 and a tenth resistor

R11, eleventh resistor R12, twelfth resistor

C1, first capacitor C2 and second capacitor

C4, fourth capacitor C6, sixth capacitor

C7, seventh capacitor C8, eighth capacitor

C9, ninth capacitance C10, tenth capacitance

U1, LDO chip U2, comparator

U3, single-channel SPST analog switch U4 and MCU

U5, D type trigger U6, DCDC power

D1, first anti-reflection diode D2, second anti-reflection diode

D3, first output or gate diode D4, second output or gate diode

D5, third output OR gate diode Q1, MOS tube

Detailed Description

The following describes specific embodiments of the present utility model in detail with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the utility model, are not intended to limit the utility model.

In the embodiments of the present application, unless otherwise indicated, terms of orientation such as "upper, lower, top, bottom" are used generally with respect to the directions shown in the drawings or with respect to the positional relationship of the components with respect to each other in the vertical, vertical or gravitational directions.

In addition, if there is a description of "first", "second", etc. in the embodiments of the present application, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the protection scope of the present application.

Fig. 1 is a schematic diagram of a national standard fast and slow charging connection signal CC2/CC wake-up and sleep unit according to the present utility model. In this fig. 1, the unit includes: the power supply LDO circuit 1, the main power supply circuit 2, the main power supply wake-up buffer circuit 3, the control circuit 4, the analog switch circuit 5, the conversion circuit 6, the reference source and reference reset circuit 7 and the voltage division acquisition circuit 8. The power supply LDO circuit 1 is used for providing +5V direct current voltage; the first end of the main power supply wake-up buffer circuit 3 is connected with the main power supply circuit 2; one end of the control circuit 4 is connected with the second end of the main power supply wake-up buffer circuit 3; one end of the analog switch circuit 5 is connected with the other end of the control circuit 4; a first end of the conversion circuit 6 is connected with the other end of the analog switch circuit 5, and a second end of the conversion circuit 6 is connected with a third end of the main power wake-up buffer circuit 3; the reference source and reference reset circuit 7 is connected with the third end of the conversion circuit 6; the voltage dividing and collecting circuit 8 is connected with the fourth end of the conversion circuit 6. The power supply LDO circuit 1 is used as a power supply for monitoring and controlling the unit to work, the conversion circuit 6 is used for converting an analog signal into a switching signal, the main power supply wake-up buffer circuit 3 is used for buffering the output of the conversion circuit and enabling the main power supply circuit 2, and the analog switching circuit 5 is used for cutting off the connection between a normal electric analog signal and the power-down detection circuit after the control circuit is powered down.

In the wake-up and sleep unit of a national standard fast and slow charge connection signal CC2/CC as shown in FIG. 1, the power LDO circuit 1 can be used to provide a pull-up voltage; the main power supply circuit 2 is used for supplying power to the control circuit 4; the main power supply wake-up buffer circuit 3 is used for determining an instruction of the output power supply wake-up based on whether the CC2/CC signal is input or not; the analog switch circuit 5 is used for sending different instructions to the control circuit 4 based on the state of the input CC2/CC signal; the conversion circuit 6 is used for converting the input CC2/CC signals, so that the state of the CC2/CC signals which the main power wake-up buffer circuit 3 needs to receive is obtained; the voltage division acquisition circuit 8 is used for carrying out level adjustment on the input CC2/CC signals. With this unit as shown in fig. 1, the control circuit 4 can be powered by the main power wake-up buffer circuit 3, and whether the main power wake-up buffer circuit 3 is powered or not depends on whether there is an input of the CC2/CC signal, so that the control circuit 4 does not need to continuously detect the CC2/CC signal. Compared with the mode of directly detecting the CC2/CC signal by the controller in the prior art, the national standard fast and slow charging connection signal CC2/CC wake-up and sleep unit provided by the utility model can sleep under the condition of no wake-up, thereby achieving the purpose of energy conservation. In addition, since the input CC2/CC signal itself has a low level, it is difficult to trigger the main power wake-up buffer circuit 3 directly, and therefore, the CC2/CC signal is adjusted by providing the combination of the voltage dividing acquisition circuit 8, the conversion circuit 6, the reference source, and the reference reset circuit 7, so that an instruction capable of triggering the main power wake-up buffer circuit 3 is obtained. The analog switch circuit 5 determines whether to send the CC2/CC signal or the default full signal to the control circuit 4 based on the state of the input CC2/CC signal, so that the control circuit 4 can automatically power off after the charging is completed.

In this embodiment, the combination of the power LDO circuit 1 may be various combinations known to those skilled in the art. Considering the case where the power LDO circuit 1 is used to provide a pull-up voltage for the whole cell, in one embodiment of the present utility model, a schematic diagram of a power LDO circuit in a national standard fast/slow charge connection signal CC2/CC wake-up and sleep cell according to the present utility model is shown in fig. 2, in which fig. 2, the power LDO circuit 1 includes: the first anti-reflection diode D1, the LDO chip U1, the first capacitor C1 and the second capacitor C2. Wherein the anode of the first anti-reflection diode D1 is used for being connected to a normal fire KL30 line; one end of the LDO chip U1 is connected with the cathode of the first anti-reflection diode D1, and the second end of the LDO chip U1 is used for outputting +5V direct current voltage; one end of the first capacitor C1 is connected with the cathode of the first anti-reflection diode D1, and the other end of the first capacitor C1 is grounded; one end of the second capacitor C2 is connected with the other end of the LDO chip U1, and the other end of the second capacitor C2 is grounded. The power LDO circuit 1 with auxiliary normal fire operation is used for providing the pull-up voltage of the reference source and the reference reset circuit 7, and also providing the pull-up voltage of the voltage division acquisition circuit 8, and simultaneously supplying power to the conversion circuit 6, the main power wake-up buffer circuit 3 and the analog switch circuit 5.

In this embodiment, the combination of the reference source and the reference reset circuit 7 may be any of various combinations known to those skilled in the art. Considering the case that the input CC2/CC signal itself is low in level, in a specific embodiment of the present utility model, as shown in fig. 3, a schematic diagram of a reference source and reference reset circuit 7 in a national standard fast and slow charging connection signal CC2/CC wake-up and sleep unit according to the present utility model is shown, in fig. 3, the reference source and reference reset circuit 7 includes: the MOS transistor comprises a first resistor R1, a second resistor R2, a MOS transistor Q1, a fourth resistor R4, a fourth capacitor C4, a fifth resistor R5, a sixth resistor R6 and a sixth capacitor C6. One end of the first resistor R1 is connected with +5V direct current voltage; one end of the second resistor R2 is connected with the other end of the first resistor R1, and the other end of the second resistor R2 is grounded; the D electrode of the MOS tube Q1 is connected with the other end of the second resistor R2, and the S electrode of the MOS tube Q1 is grounded; one end of the fourth resistor R4 is connected with the G pole of the MOS tube Q1, and the other end of the fourth resistor R4 is grounded; one end of the fourth capacitor C4 is connected with the G pole of the MOS tube Q1, and the other end of the fourth capacitor C4 is grounded; one end of a fifth resistor R5 is connected with the G pole of the MOS tube Q1, and the other end of the fifth resistor R5 is connected with the MCU control port; one end of a sixth resistor R6 is connected with the D pole of the MOS tube Q1, and the other end of the sixth resistor R6 is connected with the conversion circuit; one end of the sixth capacitor C6 is connected to the other end of the sixth resistor R6, and the other end of the sixth capacitor C6 is grounded. The reference source and reference reset circuit 7 is a circuit formed by a resistor voltage division reference source and a MOS tube Q1, and can turn over the reference voltage for the level of the post-stage conversion circuit 6 when the charging gun is inserted into a charging socket, namely when the CC2/CC signal connection is confirmed, meanwhile, the MOS tube Q1 is controlled by the MCU U4, so that the reset of the reference voltage can be realized, and a rising edge is provided for realizing the output turning of the D-type trigger U5.

In this embodiment, as shown in fig. 7, a schematic diagram of a voltage division collecting circuit 8 in a national standard fast/slow charging connection signal CC2/CC wake-up and sleep unit according to the present utility model is shown, in fig. 7, the voltage division collecting circuit 8 includes: twelfth resistor R12, signal resistor R3/RC, seventh resistor R7, and seventh capacitor C7. One end of the twelfth resistor R12 is used for being externally connected to +5V direct current voltage; one end of the signal resistor R3/RC is connected with the other end of the twelfth resistor R12, and the other end of the signal resistor R3/RC is grounded; one end of a seventh resistor R7 is connected with one end of the signal resistor R3/RC, and the other end of the seventh resistor R7 is connected with the conversion circuit; one end of the seventh capacitor C7 is connected to the other end of the seventh resistor R7, and the other end of the seventh capacitor C7 is grounded. One end of the twelfth resistor R12 is pulled up to +5V direct current voltage, the other end of the twelfth resistor R12 is connected to the interface CC2/CC signal, and the outside of the CC2/CC signal is the signal resistor R3/RC needing to be detected. The power supply is higher than the rated voltage of the electric appliance, so that the electric appliance cannot be directly connected to the power supply. That is, a seventh resistor R7 is connected to the voltage dividing and collecting circuit to share a part of voltage for the circuit. The voltage division acquisition circuit 8 is for providing a resistive voltage division to the conversion circuit 6.

In this embodiment, as shown in fig. 4, a schematic diagram of a switching circuit 6 in a national standard fast/slow charge connection signal CC2/CC wake-up and sleep unit according to the present utility model is shown, and in fig. 4, the switching circuit 6 includes: comparator U2, eighth resistor R8 and eighth capacitor C8. The same-direction input end of the comparator U2 is connected with the reference source and the reference reset circuit 7, and the reverse input end of the comparator U2 is connected with the voltage division acquisition circuit 8; one end of an eighth resistor R8 is connected with the output end of the comparator U2, and the other end of the eighth resistor R8 is connected with the main power wake-up buffer circuit 3; one end of the eighth capacitor C8 is connected to the other end of the eighth resistor R8, and the other end of the eighth capacitor C8 is grounded. The conversion circuit 6 can compare the reference source voltage with the voltage of the connection confirmation signal resistor R3/RC, and flip-flop of the output terminal of the comparator U2 can be realized when the connection confirmation of the signal resistor R3/RC is confirmed, thereby waking up the main power supply circuit 2.

In this embodiment, as shown in fig. 6, a schematic diagram of an analog switch circuit 5 in a national standard fast/slow charge connection signal CC2/CC wake-up and sleep unit according to the present utility model is shown, and various combinations of the analog switch circuits 5 are possible as known to those skilled in the art. In a specific embodiment of the utility model, the analog switching circuit 5 comprises: a single channel SPST analog switch U3, a ninth resistor R9, and a ninth capacitor C9. The input end of the single-channel SPST analog switch U3 is connected with the voltage division acquisition circuit; one end of a ninth resistor R9 is connected with the output end of the single-channel SPST analog switch U3, and the other end of the ninth resistor R9 is connected with one end of the control circuit; one end of the ninth capacitor C9 is connected to the other end of the ninth resistor R9, and the other end of the ninth capacitor C9 is grounded. Considering the situation that the MCU U4 needs to be powered for a long period of time and is in a low power consumption sleep state in the prior art, it is difficult to further reduce the system power consumption below an ideal value, the present utility model is provided with an analog switch circuit 5. The enabling end of the analog switch circuit 5 is directly controlled by the VCC power supply, and when the analog switch circuit 5 realizes the power-down of the system, the connection between the analog signal 5 and the control circuit 4 is disconnected, so that the leakage current of the power LDO circuit 1 to the power-down circuit is eliminated. The analog switch circuit 5 determines whether to transmit the CC2/CC signal or a default full electrical signal to the control circuit 4 based on the state of the input CC2/CC signal so that the control circuit 4 can automatically power off after the completion of the charging. After the system is powered off, the control circuit does not need to work in a live dormancy mode, so that the workload of software is reduced, and the reliability of the system is provided.

In this embodiment, as shown in fig. 5, a schematic diagram of a main power wake-up buffer circuit 3 in a national standard fast/slow charge connection signal CC2/CC wake-up and sleep unit according to the present utility model is shown, and various combinations known to those skilled in the art may be used for the combination of the analog main power wake-up buffer circuit 3. In one embodiment of the present utility model, the main power wake-up buffer circuit 3 includes: a D-type flip-flop U5, a first output or gate diode D3, a second output or gate diode D4, a third output or gate diode D5, a tenth resistor R10, a tenth capacitor C10, and an eleventh resistor R11. The first end of the D-type trigger U5 is connected with the conversion circuit 6; the anode of the first output or gate diode D3 is connected with the second end of the D-type trigger U5, and the cathode of the first output or gate diode D3 is connected with a main power supply circuit; the anode of the second output or gate diode D4 is connected with the control circuit, and the cathode of the second output or gate diode D4 is connected with the cathode of the first output or gate diode D3; the cathode of the third output or gate diode D5 is connected with the cathode of the second output or gate diode D4, and the anode of the third output or gate diode D5 is connected with a normal fire KL15 circuit; one end of a tenth resistor R10 is connected with the control circuit, and the other end of the tenth resistor R10 is connected with the third end of the D-type trigger U5; one end of the tenth capacitor C10 is connected with the other end of the tenth resistor R10, and the other end of the tenth capacitor C10 is grounded; one end of the eleventh resistor R11 is connected to one end of the tenth resistor R10, and the other end of the eleventh resistor R11 is grounded. The main power supply awakening buffer circuit 3 is provided with the D-type trigger U5, the D-type trigger U5 has two stable states, namely '0' and '1', and can be turned over from one stable state to the other stable state under the action of an input CC2/CC signal, and the signal interruption can be carried out on the MCU U4 in the dormant state, so that the aim of saving energy is fulfilled.

In this embodiment, as shown in fig. 8, a schematic diagram of a main power circuit 2 in a national standard fast and slow charge connection signal CC2/CC wake-up and sleep unit according to the present utility model is shown, and in fig. 8, the main power circuit 2 includes: a DCDC power supply U6 and a second anti-reflection diode D2. The output of the DCDC power supply U6 is a VCC power supply network; the cathode of the second anti-reflection diode D2 is connected with a normal fire KL30 circuit, and the anode of the second anti-reflection diode D2 is connected with the input end of the DCDC power supply U6. The DCDC power supply U6 supplies power for the MCU U4 with larger power consumption and other external equipment, and is separately supplied with power from the power supply LDO circuit 1, and each module is independently supplied with power to prevent one module from being damaged due to high-voltage discharge or other reasons and then being damaged. The purpose of this is to ensure that each module works independently and is not disturbed.

In this embodiment, as shown in table 1 below, table 1 is a truth table for a D-type flip-flop U5, where the input clock signal of the D-type flip-flop U5 is CLK, the input data signal is DI, and the output signal is Q; as shown in the following table 2, table 2 is a truth table of the comparator U2, wherein the voltage at the non-inverting input terminal of the comparator U2 is V1, and the voltage at the inverting input terminal is V2; the MCU U4 outputs the control signal of the data input DI of the D-type trigger U5 as OUT-D, the control signal of the enabling input EN of the main power circuit as OUT-DC, and the G-pole control signal of the MOS transistor Q1 as REF-RST.

Table 1D trigger truth table

Table 2 comparison circuit truth table

In-phase input	Inverting input	Output of
			V1	V2	CLK
High height	Low and low	1
			Low and low	High height	0

When the unit shown in the figures 1 to 10 works, the KL30 circuit is connected with normal fire for the first time, the LDO power supply U1 works, and a +5V voltage circuit is added for power-on work; v1 is the voltage of +5v divided by the series connection of R1 and R2, V2 is the voltage of +5v pulled up, the voltage in the same direction of the comparator U2 is smaller than the voltage in the opposite direction, i.e. V1< V2, at this time the output of the comparator U2 is low, i.e. clk=0, the clock input clk=0 of the d-type flip-flop U5, the data input di=0, and the output q=0; when the output Q=0 of the D-type trigger U5, the enabling end of the DCDC power supply U6 is invalid, the VCC circuit is unpowered, the single-channel SPST analog switch U3 is invalid, the switch is closed, and the V2 does not leak electricity to the VCC circuit; when a fast and slow charging gun is inserted, namely the signal resistor R3/RC is connected, V1 is still a reference voltage, V2 is the serial voltage division +5V of the signal resistor R3/RC and the fifth resistor R5, namely the in-phase voltage of the comparator U2 is greater than the reverse voltage, namely V1 is greater than V2, at the moment, the output of the comparator U2 is high, namely the rising edge jump from 0 to 1 occurs in CLK=1, the clock input CLK of the D-type trigger U5 is also changed from 0 to 1, the data input DI=0 and the output Q=1, at the moment, the output Q=1 of the D-type trigger U5, the enabling end of the DCDC power supply U6 is effective, the VCC circuit is electrified, the single-channel SPST analog switch U3 is enabled to be effective, the switch is opened, the MCU U4 collects the V2 voltage, the MCU U4 controls OUT-DC=1, namely the MCU U4 simultaneously takes over the DCDC power supply U6 to enable control, and charges according to an estimated charging strategy; after the system charging is finished, the MCU U4 controls OUT-D=1, namely, the D-type trigger U5 data input DI=1, the MCU U4 controls REF-RST=1, the MOS tube Q1 is opened, R2 is short-circuited, namely, V1=0V, V2 is the series voltage +5V of the resistor R3/RC and R5, namely, the in-phase voltage < reverse voltage of the comparator U2, namely, V1< V2, the output of the comparator U2 is low, namely, CLK=0, the MCU U4 controls REF-RST=0, the MOS tube Q1 is closed, at the moment, the in-phase voltage of the comparator U2 > reverse voltage, namely, V1> V2, the clock input CLK of the D-type trigger U5 is changed from 0 to 1, the data input DI=1, when the D-type trigger U5 outputs Q=0, the DCDC power supply U6 enabling end is completely taken over by the MCU U4, the MCU U4 controls OUT-D=0, and the OUT-DC=0 is finished; and pulling out the charging gun, waking up the starting system by a key to discharge, and waiting for the charging gun to be inserted after the discharge is finished, so as to complete the cycle.

Through the technical scheme, the utility model provides a national standard fast and slow charging connection signal CC2/CC wake-up and sleep unit, which comprises a power supply LDO circuit 1, a main power supply circuit 2, a main power supply wake-up buffer circuit 3, a control circuit 4, an analog switch circuit 5, a conversion circuit 6, a reference source and reference reset circuit 7 and a voltage division acquisition circuit 8. In this unit, the control circuit 4 is powered by the main power wake-up buffer circuit 3, and whether the main power wake-up buffer circuit 3 is powered or not depends on whether there is an input of the CC2/CC signal, so that the control circuit does not need to continuously detect the CC2/CC signal. Compared with the mode of directly detecting the CC2/CC signal by the controller in the prior art, the national standard fast and slow charging connection signal CC2/CC wake-up and sleep unit provided by the utility model can sleep under the condition of no wake-up, thereby achieving the purpose of energy conservation.

The optional embodiments of the present utility model have been described in detail above with reference to the accompanying drawings, but the embodiments of the present utility model are not limited to the specific details of the foregoing embodiments, and various simple modifications may be made to the technical solutions of the embodiments of the present utility model within the scope of the technical concept of the embodiments of the present utility model, and all the simple modifications belong to the protection scope of the embodiments of the present utility model.

In addition, the specific features described in the above embodiments may be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the various possible combinations of embodiments of the utility model are not described in detail.

Those skilled in the art will appreciate that all or part of the steps in implementing the methods of the embodiments described above may be implemented by a program stored in a storage medium, including instructions for causing a (which may be a single-chip microcomputer, a chip or the like) or processor (processor) to perform all or part of the steps of the methods of the embodiments described herein. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

In addition, any combination of the various embodiments of the present utility model may be made between the various embodiments, and should also be regarded as disclosed in the embodiments of the present utility model as long as it does not deviate from the idea of the embodiments of the present utility model.

Claims (8)

1. A national standard fast and slow charging connection signal CC2/CC wake-up and sleep unit, the unit comprising:

the power supply LDO circuit is used for providing +5V direct current voltage;

a main power supply circuit;

the main power supply wake-up buffer circuit is connected with the first end of the main power supply wake-up buffer circuit;

one end of the control circuit is connected with the second end of the main power supply wake-up buffer circuit;

the analog switch circuit is connected with one end of the control circuit;

the first end of the conversion circuit is connected with the other end of the analog switch circuit, and the second end of the conversion circuit is connected with the third end of the main power wake-up buffer circuit;

a reference source and a reference reset circuit, the reference source and the reference reset circuit being connected to a third terminal of the conversion circuit;

and the partial pressure acquisition circuit is connected with the fourth end of the conversion circuit.

2. The circuit of claim 1, wherein the power LDO circuit comprises:

a first anti-reflection diode, the anode of which is used for being connected to a normal fire KL30 line;

one end of the LDO chip is connected with the cathode of the first anti-reflection diode, and the second end of the LDO chip is used for outputting +5V direct current voltage;

one end of the first capacitor is connected with the cathode of the first anti-reflection diode, and the other end of the first capacitor is grounded;

and one end of the second capacitor is connected with the other end of the LDO chip, and the other end of the second capacitor is grounded.

3. The circuit of claim 1, wherein the reference source and reference reset circuit comprises:

one end of the first resistor is connected with +5V direct current voltage;

one end of the second resistor is connected with the other end of the first resistor, and the other end of the second resistor is grounded;

the D electrode of the MOS tube is connected with the other end of the second resistor, and the S electrode of the MOS tube is grounded;

one end of the fourth resistor is connected with the G pole of the MOS tube, and the other end of the fourth resistor is grounded;

one end of the fourth capacitor is connected with the G pole of the MOS tube, and the other end of the fourth capacitor is grounded;

one end of the fifth resistor is connected with the G pole of the MOS tube, and the other end of the fifth resistor is connected with the MCU control port;

one end of the sixth resistor is connected with the D pole of the MOS tube, and the other end of the sixth resistor is connected with the conversion circuit;

and one end of the sixth capacitor is connected with the other end of the sixth resistor, and the other end of the sixth capacitor is grounded.

4. The circuit of claim 1, wherein the voltage division acquisition circuit comprises:

a twelfth resistor, wherein one end of the twelfth resistor is used for being externally connected to +5V direct current voltage;

one end of the signal resistor is connected with the other end of the twelfth resistor, and the other end of the signal resistor is grounded;

one end of the seventh resistor is connected with one end of the signal resistor, and the other end of the seventh resistor is connected with the conversion circuit;

and one end of the seventh capacitor is connected with the other end of the seventh resistor, and the other end of the seventh capacitor is grounded.

5. The circuit of claim 1, wherein the conversion circuit comprises:

the non-inverting input end of the comparator is connected with the reference source and the reference reset circuit, and the inverting input end of the comparator is connected with the voltage division acquisition circuit;

one end of the eighth resistor is connected with the output end of the comparator, and the other end of the eighth resistor is connected with the main power supply wake-up buffer circuit;

and one end of the eighth capacitor is connected with the other end of the eighth resistor, and the other end of the eighth capacitor is grounded.

6. The circuit of claim 1, wherein the analog switching circuit comprises:

the input end of the single-channel SPST analog switch is connected with the voltage division acquisition circuit;

one end of the ninth resistor is connected with the output end of the single-channel SPST analog switch, and the other end of the ninth resistor is connected with one end of the control circuit;

and one end of the ninth capacitor is connected with the other end of the ninth resistor, and the other end of the ninth capacitor is grounded.

7. The circuit of claim 1, wherein the main power wake-up buffer circuit comprises:

the first end of the D-type trigger is connected with the conversion circuit;

a first output or gate diode, the anode of the first output or gate diode being connected to the second end of the D-type flip-flop, the cathode of the first output or gate diode being connected to the main power circuit;

a second output or gate diode, the anode of the second output or gate diode being connected to the control circuit, the cathode of the first output or gate diode being connected to the cathode of the second output or gate diode;

a third output or gate diode, the cathode of the third output or gate diode being connected to the cathode of the second output or gate diode, the anode of the third output or gate diode being connected to the normally-on KL15 line;

one end of the tenth resistor is connected with the control circuit, and the other end of the tenth resistor is connected with the third end of the D-type trigger;

a tenth capacitor, one end of which is connected with the other end of the tenth resistor, and the other end of which is grounded;

and one end of the eleventh resistor is connected with one end of the tenth resistor, and the other end of the eleventh resistor is grounded.

8. The circuit of claim 1, wherein the main power circuit comprises:

the DCDC power supply is output as a VCC power supply network;

and the cathode of the second anti-reflection diode is connected with a normal fire KL30 circuit, and the anode of the second anti-reflection diode is connected with the input end of the DCDC power supply.