CN211236170U

CN211236170U - Circuit board

Info

Publication number: CN211236170U
Application number: CN201921723754.4U
Authority: CN
Inventors: 梁建; 罗雄科
Original assignee: Shanghai Zenfocus Semi Tech Co ltd
Current assignee: Shanghai Zenfocus Semi Tech Co ltd
Priority date: 2019-10-12
Filing date: 2019-10-12
Publication date: 2020-08-11
Anticipated expiration: 2029-10-12

Abstract

The utility model discloses a circuit board, it is regional at the BGA of this circuit board, the pin end electricity each other of the power that awaits measuring connects and forms impedance test region, just impedance test region's edge disposes the matching interface who is connected with the regional electricity of impedance test. When the circuit board is used for measuring the power supply impedance, the test point is close to the chip, and the difference on the test position is small; the capacitor of the power supply to be tested does not need to be removed during testing, and the performance of the power supply is reserved; the test data has high precision and good feedback power supply performance.

Description

Circuit board

Technical Field

The utility model relates to a power test technical field indicates a circuit board especially.

Background

With the rapid development of the communication industry, the requirement on the large data computing capacity is higher and higher, and the requirement on the measurement precision of the power performance on the board is also higher and higher. The measurement of the performance of the power supply is mainly divided into two types: one is measurement based on ripple noise, which is to capture power supply ripple through an oscilloscope, and belongs to time domain measurement; the other is measurement based on power supply impedance, which captures AC (alternating current) impedance of the power supply through a network analyzer, and belongs to frequency domain measurement.

Currently, a two-port test method is generally used for measuring the AC impedance of a power supply, and includes the following steps: 1) removing a capacitor which is closer to the power utilization chip; 2) welding the copper core and the grounding wire of the coaxial cable to the two bonding pads of the capacitor; 3) and connecting the coaxial cable to a network branch tester to measure data. However, this test method has a number of drawbacks: 1) the test point is far away from the power utilization chip, and inconsistency exists in the test position; 2) the coaxial cable is introduced to influence the reliability of test data; 3) the coaxial cable needs to be welded, and artificial uncontrollable factors are introduced in welding; 4) the capacitor of the power source to be tested needs to be removed, destroying the performance of the power source itself.

Fig. 1 shows a comparison graph of the test values and the theoretical derivative values under the method, wherein the abscissa represents frequency and the ordinate represents impedance. Fig. 1(a) is a graph comparing an experimental test value and a theoretical derivative value, where at a point m2 (frequency freq 19.8889MHz), the test value mag (N _ AVSVDD) is 0.44657, the theoretical derivative inverse value mag (powersi.. N _ AVSVDD) is 0.01169, and the theoretical derivative inverse value mag (slwave.. N _ AVSVDD) is 0.01076; fig. 1(b) is a graph comparing the test value and the theoretically derived value of another experiment, where the point m3 (frequency freq 19.8889MHz) in the graph is 0.50998 for the test value mag (LVCC), 0.01346 for the theoretically derived inverse mag (powersi.. LVCC), and 0.011796 for the theoretically derived inverse mag (slwave.. LVCC); wherein, the abscissa is frequency, and the ordinate is amplitude; mag denotes amplitude, i.e., amplitude data is shown in fig. 1(a) and 1 (b); PowerSI/Slwave represents a different theoretical derivation tool; n _ AVSVDD/LVCC represents a custom power source name. It can be seen that the test values deviate far from the theoretical derivation values, and the test accuracy is poor.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a circuit board solves the limited technical problem of current-carrying capacity of current PCB.

The utility model provides a technical scheme as follows:

a power supply impedance testing method, comprising:

connecting a connector for impedance test to a preset matching interface on a circuit board; in a BGA (ball grid Array) area of a circuit board, pin (pin) ends of a power supply to be tested are electrically connected with each other to form an impedance test area, and the matching interface is arranged at the edge of the impedance test area and is electrically connected with the impedance test area;

setting test conditions, and testing the impedance of the power supply to be tested by using an alternating current impedance test method.

Further preferably, the circuit board includes a plurality of power supplies to be tested, in the BGA area, pin terminals of each power supply to be tested are connected to form an impedance test area for the corresponding power supply to be tested, and a matching interface is configured at an edge of each impedance test area.

Further preferably, the pin terminals of the power supply to be tested are connected with each other by using a copper sheet on the surface layer of the BGA area to form an impedance test area.

Further preferably, 2 matching interfaces are configured for the impedance test area of each power supply to be tested;

in connecting a connector for impedance testing to a matching interface provided in advance on a circuit board: 2 connectors for impedance test are respectively connected to 2 matching interfaces which are arranged in an impedance test area on the circuit board in advance.

Further preferably, the connector is an SMA connector, and the matching interface is an SMA interface;

and arranging an installation through hole matched with the fixing hole on the SMA interface in the impedance test area, and installing the SMA interface in a mode that a connecting piece penetrates through the fixing hole and the installation through hole.

The utility model also provides a circuit board is applied to the impedance that uses the AC impedance test method test power that awaits measuring, the BGA of circuit board is regional, and the pin end electricity interconnection of the power that awaits measuring forms the impedance test region, just the edge in impedance test region disposes the matching interface who is connected with the regional electricity of impedance test.

Further preferably, the circuit board includes a plurality of power supplies to be tested, in the BGA area, pin terminals of each power supply to be tested are connected to form an impedance testing area for the corresponding power supply to be tested, and a matching interface is configured at an edge of each impedance testing area.

Further preferably, 2 matching interfaces are configured for each impedance test area of the power supply under test.

Further preferably, the matching interface is an SMA interface, and an installation through hole matched with the fixing hole on the SMA interface is configured in the impedance testing area.

Further preferably, in the BGA area, a layer of copper sheet is disposed on a surface layer of a pin end of the power supply to be tested, and the pin ends of the power supply to be tested are connected to form an impedance testing area.

The utility model provides an among power impedance test method and the circuit board, the power pin end that will await measuring the power in top layer BGA area holds all shorts and forms the impedance test region together to dispose the interface at the impedance test region, with this, when the impedance test, use the interface connection who connects and set up to test. The test method comprises the following steps: 1) the test point is closer to the chip, and the difference on the test position is very small; 2) the capacitor of the power supply to be tested does not need to be removed, and the performance of the power supply is kept; 3) the test data has high precision and good feedback power supply performance.

In addition, the interface configured on the circuit board is an SMA interface, and the joint is an SMA joint, so that during testing, a coaxial cable is not required to be introduced, the influence on the test data is greatly reduced due to the use of the high-speed SMA, and the test data is more reliable; and the SMA interface adopts a mechanical assembly structure, welding is not needed, and the influence of human factors such as the quantity of soldering tin and temperature does not exist, so that the test precision is further improved.

Drawings

The above features, technical features, advantages and modes of realisation of the circuit board will be further described in the following, in a clearly understandable manner, with reference to the accompanying drawings, which illustrate preferred embodiments.

FIG. 1 is a comparison graph of a test value and a theoretical derivation value of an existing AC impedance measurement method for a power supply;

FIG. 2 is a schematic flow chart of the power impedance testing method of the present invention;

fig. 3 is a schematic structural diagram of an example of the present invention, in which pin terminals of 5 power supplies to be tested in a circuit board are respectively connected to form 5 impedance testing regions;

fig. 4 is a schematic diagram illustrating a structure of two interfaces configured in each impedance testing area according to an embodiment of the present invention;

fig. 5 is a schematic diagram of the SMA interface and SMA connector of the present invention;

fig. 6 is a schematic view of the SMA interface installation of the present invention;

fig. 7 is a comparison graph of the test value and the theoretical derivation value of the AC impedance measurement method of the utility model.

The reference numbers illustrate:

1-impedance test area, 2-interface, 21-fixing hole and 3-mounting through hole.

Detailed Description

In order to more clearly illustrate embodiments of the present invention or technical solutions in the prior art, specific embodiments of the present invention will be described below with reference to the accompanying drawings. It is obvious that the drawings in the following description are only examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be obtained from these drawings without inventive effort.

For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure of the product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".

In this context, it is to be understood that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

As shown in fig. 2, the flow diagram of the power impedance testing method provided by the present invention is shown, and it can be seen from the diagram that the power impedance testing method includes:

s10, connecting the connector for impedance test to the matching interface preset on the circuit board; in the BGA area of the circuit board, pin ends of a power supply to be tested are electrically connected with each other to form an impedance test area, and a matching interface is arranged at the edge of the impedance test area and is electrically connected with the impedance test area;

and S20, setting test conditions, and testing the impedance of the power supply to be tested by using an alternating current impedance test method.

Before the test, the chip is processed according to the scene that the chip normally works (when the chip is welded, the pin ends of the power supply to be tested are all in short circuit connection through packaging), and specifically, in the design, the pin ends of the power supply to be tested are connected together in a surface layer BGA area. Further, when the circuit board (PCB) comprises a plurality of power supplies to be tested, pin ends of the power supplies to be tested are respectively connected together to form respective impedance testing areas. In one example, as shown in fig. 3, a circuit board includes 5 power supplies, and 5 impedance test areas 1 are formed.

After the impedance test area is formed, the interface position is designed at the edge of the impedance test area (without influencing the normal work of the chip), so that the interface is convenient to mount. In the testing process, a testing instrument with a corresponding joint is connected with an interface in a chip, and after corresponding testing conditions are set according to the chip, the performance of the power supply to be tested is directly tested by using an alternating current impedance testing method. Further, when the circuit board comprises a plurality of power supplies to be tested, interfaces matched with the connectors are respectively configured in the impedance test area formed by each power supply to be tested. The test method has the advantages that the test point is closer to the chip, and the difference on the test position is very small; and the capacitor of the power supply to be tested does not need to be removed, the performance of the power supply is kept, the performance of the power supply can be well fed back, and the precision of test data is greatly improved.

For the BGA area surface layer, the method of connecting the pins of the power source to be tested together is not limited in detail, and the method of connecting the pins of the power source to be tested together is included in the disclosure of the present invention. In one example, the pin ends of the power source to be tested are connected with each other by using a copper sheet to form an impedance testing area, and in other examples, the pin ends of the power source to be tested can be connected by using any other conductive material.

In addition, in practical application, the test method for the power supply impedance is provided with a corresponding number of interfaces in an impedance test area. In one example, a two-port test method with higher test accuracy is adopted, and 2 matching interfaces 2 are configured for each impedance test area of the power supply to be tested, as shown in fig. 4. During testing, 2 connectors of the testing instrument are respectively connected to 2 matching interfaces of the impedance testing area to perform impedance testing. In other testing methods, a corresponding number of interfaces may be set according to requirements, such as installing 1 interface, 3 interfaces, and the like.

The specific form of the joint and interface is likewise not limited here. In one example, the connector is an SMA connector, and the matching interface is an SMA interface, as shown in fig. 5, where fig. 5(a) is a schematic diagram of the SMA interface, and fig. 5(b) is a schematic diagram of the SMA connector. An installation through hole 3 matched with the fixing hole 21 on the SMA interface 2 is configured in the impedance test area, the SMA interface is installed on the circuit board in a mode that a connecting piece (screw) penetrates through the fixing hole and the installation through hole, and the SMA interface is installed on the circuit board as shown in figure 6.

In one example, pin terminals of a power supply to be tested are connected together using a copper sheet to form an impedance test area, and 2 SMA interfaces are installed in one impedance test area as shown in fig. 4. During testing, the SMA joints on two test wires (adopting a dual-port test method) of the net-dividing tester are directly connected with the 2 SMA interfaces on the impedance test area for testing. The test results are shown in fig. 7, where the abscissa is frequency and the ordinate is impedance. Fig. 7(a) is a graph comparing a test value and a theoretically derived value under a one-time experimental condition, where at a point m2 (frequency freq 20.0013MHz), the test value mag (N _ AVSVDD) is 0.01413, the theoretically derived inverse value mag (powersi.. N _ AVSVDD) is 0.01200, and the theoretically derived inverse value mag (slwave.. N _ AVSVDD) is 0.01101; fig. 7(b) is a graph comparing the test value and the theoretically derived value under the secondary experimental condition, where at a point m3 (frequency freq is 20.0013MHz), the test value mag (LVCC) is 0.01725, the theoretically derived inverse mag (powersi.. LVCC) is 0.01377, and the theoretically derived inverse mag (slwave.. LVCC) is 0.01206, where the abscissa is frequency and the ordinate is amplitude; mag denotes amplitude, i.e., amplitude data is shown in fig. 7(a) and 7 (b); PowerSI/Slwave represents a different theoretical derivation tool; n _ AVSVDD/LVCC represents a custom power source name. It can be seen that, by using the test method, the trend of the test value is basically consistent with that of the theoretical derivation value, and compared with the test result of the existing test method shown in fig. 1, the test value has smaller deviation, the test precision and the test efficiency are greatly improved, and the predictability of the project risk is greatly reduced; and the testing method is used, the coaxial cable does not need to be welded in the capacitor area, and the testing difficulty is greatly reduced.

The utility model also provides a circuit board is applied to the impedance that uses the AC impedance test method test power that awaits measuring, and the BGA of circuit board is regional, and the pin end electricity interconnection of the power that awaits measuring forms the impedance test region, and the edge in impedance test region disposes the matching interface who is connected with the regional electricity of impedance test.

Specifically, before carrying out impedance test to the power that awaits measuring, handle the chip according to the scene that the chip normally worked (the chip is when the welding, and the encapsulation will await measuring the whole short circuits of pin end of power together), specifically, in the design, link together the power pin end of the power that awaits measuring in top layer BGA region. Further, when the circuit board (PCB) comprises a plurality of power supplies to be tested, pin ends of the power supplies to be tested are respectively connected together to form respective impedance testing areas. In one example, as shown in fig. 3, a circuit board includes 5 power supplies, and 5 impedance test areas 1 are formed.

In addition, in practical application, the test method for the power supply impedance is provided with a corresponding number of interfaces in an impedance test area. In one example, a two-port test method with higher test accuracy is adopted, and 2 matching interfaces 2 are configured for each impedance test area of the power supply to be tested, as shown in fig. 4. During testing, 2 connectors of the testing instrument are respectively connected to 2 matching interfaces of the impedance testing area to perform impedance testing.

It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. The circuit board is characterized in that in a BGA area of the circuit board, pin ends of a power supply to be tested are electrically connected with each other to form an impedance test area, and a matching interface electrically connected with the impedance test area is arranged at the edge of the impedance test area.

2. The circuit board of claim 1, wherein the circuit board comprises a plurality of power supplies to be tested, in the BGA area, the pin terminals of each power supply to be tested are connected to form an impedance testing area for the corresponding power supply to be tested, and the matching interfaces are respectively configured at the edges of the impedance testing areas.

3. A circuit board as claimed in claim 1 or 2, characterized in that 2 matching interfaces are configured for each impedance test area of the power supply to be tested.

4. The circuit board of claim 1 or 2, wherein the matching interface is an SMA interface, and wherein the impedance testing area is configured with mounting through holes that match with fixing holes on the SMA interface.

5. The circuit board of claim 1 or 2, wherein in the BGA area, the surface layer of the pin terminals of the power supply to be tested is provided with a copper layer, and the pin terminals of the power supply to be tested are connected with each other to form an impedance test area.