CN210897259U

CN210897259U - Semiconductor package

Info

Publication number: CN210897259U
Application number: CN201921679525.7U
Authority: CN
Inventors: 高荣范
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2019-10-09
Filing date: 2019-10-09
Publication date: 2020-06-30
Anticipated expiration: 2029-10-09

Abstract

The present application relates to semiconductor packages. A semiconductor package according to an embodiment includes: a semiconductor die having a first surface, a second surface opposite the first surface, and a side surface connecting the first surface and the second surface; a conductive pad adjacent to the first surface; a first passivation layer having a first modulus on a side surface of the semiconductor die; and an encapsulation encapsulating the semiconductor die, the conductive pad, and the first passivation layer. The semiconductor packaging body provided by the embodiment of the application can prevent the low-k interlayer dielectric from being layered at the edge of the semiconductor bare chip, so that the packaging reliability is improved.

Description

Semiconductor package

Technical Field

The embodiment of the application relates to the field of semiconductors, in particular to a semiconductor package.

Background

In existing semiconductor packages, the low-k dielectric portion surrounding the top metallization of the semiconductor die has low modulus properties and is therefore susceptible to damage, cracking, or delamination during semiconductor packaging operations. One failure scheme includes delamination of the low-k interlayer dielectric at the edge of the semiconductor die due to Coefficient of Thermal Expansion (CTE) mismatch between the semiconductor die and the epoxy mold compound. The difference in material shrinkage and expansion at the heterointerface (e.g., semiconductor material and epoxy-based molding material) stresses the low-k interlayer dielectric at the edge of the semiconductor die, causing the low-modulus low-k interlayer dielectric to delaminate from its original layer. Delamination of the low-k interlayer dielectric at the edge of the semiconductor die can lead to failure of the semiconductor device by damaging the metal interconnects in the top metallization and/or exposing the metal interconnects or active regions to the molding compound, thereby reducing the reliability of the semiconductor package.

Therefore, there are many technical problems to be solved in the industry regarding how to improve the reliability of the semiconductor package.

SUMMERY OF THE UTILITY MODEL

It is an object of embodiments of the present application to provide a semiconductor package that can prevent delamination of a low-k dielectric portion, thereby improving reliability of the semiconductor package.

According to an embodiment of the present application, there is provided a semiconductor package including: a semiconductor die having a first surface, a second surface opposite the first surface, and a side surface connecting the first surface and the second surface; a conductive pad adjacent to the first surface; a first passivation layer on the side surface of the semiconductor die and having a first modulus; and an encapsulation encapsulating the semiconductor die, the conductive pad, and the first passivation layer.

In some embodiments of the present application, the semiconductor die comprises a metallization adjacent to the first surface, the metallization comprising a conductive line and a dielectric portion surrounding the conductive line, wherein the dielectric portion comprises a second modulus lower than the first modulus.

In some embodiments of the present application, the encapsulation comprises a plurality of fillers.

In some embodiments of the present application, the first passivation layer does not include a filler.

In some embodiments of the present application, further comprising a second passivation layer on the first surface of the semiconductor die, the second passivation layer connected to the first passivation layer.

In some embodiments of the present application, the first passivation layer is in contact with the dielectric portion of the metallization portion.

In some embodiments of the present application, the semiconductor die further comprises a semiconductor layer stacked with the metallization, the first passivation layer further being in contact with the semiconductor layer.

In some embodiments of the present application, the second passivation layer is substantially coplanar with the conductive pad.

In some embodiments of the present application, the semiconductor layer includes a narrower portion near the first surface and a wider portion near the second surface, and the first passivation layer is in contact with the narrower portion.

In some embodiments of the present application, the narrower portion is in contact with the metalized portion.

According to an embodiment of the present application, there is provided a semiconductor package including: a substrate having a top surface and a bottom surface opposite the top surface; a semiconductor die electrically connected to the top surface, wherein semiconductor die comprises a side surface substantially perpendicular to the top surface; a first passivation layer on the side surface and having a first modulus; and an encapsulation encapsulating the semiconductor die and the first passivation layer.

The semiconductor package provided by the embodiment of the application can prevent the low-k dielectric part from being layered, so that the reliability of the semiconductor package is improved.

Drawings

The drawings necessary for describing the embodiments of the present application or the prior art will be briefly described below in order to describe the embodiments of the present application. It is to be understood that the drawings in the following description are only some of the embodiments of the present application. It will be apparent to those skilled in the art that other embodiments of the drawings can be obtained from the structures illustrated in these drawings without the need for inventive work.

FIG. 1 is a schematic diagram of a top view of a semiconductor die according to an embodiment of the present application

FIG. 2 is a schematic longitudinal cross-sectional view of a semiconductor package including the semiconductor die of FIG. 1 taken along line A-A of FIG. 1 according to an embodiment of the present application

FIG. 3 is an enlarged schematic longitudinal cross-sectional view of a portion B-B of the semiconductor package shown in FIG. 2

FIG. 4 is a schematic longitudinal cross-sectional view of a semiconductor package according to another embodiment of the present application taken along line A-A of FIG. 1

FIG. 5 is a schematic longitudinal cross-sectional view of a semiconductor package according to still another embodiment of the present application taken along line A-A of FIG. 1

FIG. 6 is a schematic longitudinal cross-sectional view of a semiconductor package according to another embodiment of the present application taken along line A-A of FIG. 1

FIGS. 7a-7g are schematic flow diagrams illustrating the fabrication of a semiconductor package according to an embodiment of the present application, which can fabricate the semiconductor package of FIG. 2

FIGS. 8a-8g are schematic flow diagrams illustrating the fabrication of a semiconductor package according to another embodiment of the present application, which can fabricate the semiconductor package of FIG. 4

Detailed Description

Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The examples of the present application should not be construed as limiting the present application.

As used herein, the terms "about", "substantially", "essentially" are used to describe and describe small variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation that is less than or equal to ± 10% of the numerical value, such as less than or equal to ± 5%, less than or equal to ± 0.5%, or less than or equal to ± 0.05%. For example, two numerical values may be considered "substantially" the same if the difference between the two values is less than or equal to ± 10% of the mean of the values.

Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.

In this application, unless specified or limited otherwise, "disposed," "connected," "coupled," "secured," and words of similar import are used broadly and those skilled in the art will understand that the words used above apply to situations in which, for example, a fixed connection, a removable connection, or an integrated connection; it may also be a mechanical or electrical connection; it may also be directly connected or indirectly connected through intervening structures; or may be internal to both components.

Fig. 1 is a schematic top view of a semiconductor die 100 according to an embodiment of the present application.

As shown in fig. 1, a semiconductor die 100 according to an embodiment of the present application may include: a pad region 101 and a central region 103.

The pad region 101 includes a plurality of pads 101 a. The pad area 101 may be located at the periphery of the semiconductor die 100. In other embodiments of the present application, the pad region 101 may be located in other regions of the semiconductor die 100, such as, but not limited to, the central region 103. The pad region 101 may include any number of pads 101a, and the position, arrangement, and shape of the pads 101a in the semiconductor die 100 are not limited to the position, arrangement, and shape shown in fig. 1.

Fig. 2 is a longitudinal cross-sectional view of a semiconductor package 200 including the semiconductor die of fig. 1 according to an embodiment of the present application, taken along line a-a of fig. 1. Fig. 3 is an enlarged schematic longitudinal cross-sectional view of a portion B-B of the semiconductor package 200 shown in fig. 2.

As shown in fig. 2 and 3, a semiconductor package 200 according to an embodiment of the present application includes: substrate 201, semiconductor die 203, conductive pad 205, first passivation layer 207, second passivation layer 209, and encapsulation 211.

The substrate 201 has a top surface 201a and a bottom surface 201b opposite to the top surface 201 a. Substrate 201 is configured to carry semiconductor die 203. The bottom surface 201b of the substrate 201 may be provided with a plurality of conductive terminals 201 c. In some embodiments, the substrate 201 may comprise a plurality of layers including dielectric layers, metal layers, and electrical connections (via) connecting the layers, as is conventional in the art.

Semiconductor die 203 has a first surface 203a, a second surface 203b opposite first surface 203a, and a side surface 203c connecting first surface 203a and second surface 203 b. Semiconductor die 203 may be configured to be adhesively disposed to top surface 201a of substrate 201 via second surface 203 b. In other embodiments of the present application, the semiconductor die 203 may be configured to be disposed on the top surface 201a of the substrate 201 by any other suitable manner. Semiconductor die 203 may be configured to be electrically connected to substrate 201 through wires 213 by a wire bonding process. In other embodiments of the present application, the semiconductor die 203 may be configured to be electrically connected to the substrate 201 by a flip chip bonding process. Side surfaces 203c of semiconductor die 203 are substantially perpendicular to top surface 201a of substrate 201. Semiconductor die 203 may be any type of die or chip.

Referring to fig. 3, semiconductor die 203 may include metalized portion 2031. Metallization 2031 is disposed adjacent to first surface 203a of semiconductor die 203. Metallization 2031 may include a conductive line 2031a, a dielectric portion 2031b surrounding conductive line 2031a, and a dielectric portion 2031 c. Conductive lines 2031a provide electrical connections between the interior of semiconductor die 203 and may connect to conductive pads 205 located on first surface 203 a. In certain embodiments, dielectric portion 2031b and dielectric portion 2031c each have a second modulus that is lower than the first modulus of the first passivation layer 207. In some embodiments, dielectric portion 2031b has a second modulus lower than the first modulus of the first passivation layer 207 and dielectric portion 2031c has a first modulus that is similar to the first modulus of the first passivation layer 207. Typically, dielectric portion 2031b is composed of one or more materials with a low dielectric constant (low dielectric constant).

Dielectric portions

2031b and 2031c of metallization 2031 are in contact with first passivation layer 207 such that the side surfaces of

dielectric portions

2031b and 2031c are covered by first passivation layer 207.

Semiconductor die 203 may also include a semiconductor layer 2033 stacked with metallization 2031. In some embodiments, the semiconductor layer 2033 can be an equal-width object, as shown in fig. 2 and 5. In some embodiments, the semiconductor layer 2033 can include a narrower portion 2033a near the first surface 203a and a wider portion 2033b near the second surface 203b, as shown in fig. 4 and 6. The narrower portion 2033a is in contact with the metalized portion 2031. The narrow portion 2033a and the wide portion 2033b may be in contact with the first passivation layer 207 such that all of the side surfaces of the narrow portion 2033a and all of the side surfaces of the wide portion 2033b are covered by the first passivation layer 207.

In other embodiments of the present application, only the side surface of the narrow portion 2033a of the semiconductor layer 2033 is in contact with the first passivation layer 207, so that all or a portion of the side surface of the narrow portion 2033a is covered by the first passivation layer 207. In other embodiments of the present application, the narrow portion 2033a and a portion of the wide portion 2033b of the semiconductor layer 2033 are in contact with the first passivation layer 207 such that all of the side surface of the narrow portion 2033a and a portion of the side surface of the wide portion 2033b are covered by the first passivation layer 207. In other embodiments of the present application, the semiconductor layer 2033 may not be in contact with the first passivation layer 207.

The conductive pad 205 may be adjacent to the first surface 203a of the semiconductor die 203. The conductive pad 205 may be disposed on the first surface 203a of the semiconductor die 203. The conductive pad 205 is substantially coplanar with the second passivation layer 209. In other embodiments of the present application, the conductive pads 205 may be further connected to connecting components such as conductive pillars, solder balls, or leads to electrically connect the semiconductor die 203 with other components.

The first passivation layer 207 may be disposed on the side surface 203c of the semiconductor die 203 and have a first modulus. In some embodiments, the first modulus of the first passivation layer 207 is greater than the second modulus of the

dielectric portions

2031b and 2031c of the metalized portions 2031 of the semiconductor die 203, and in some embodiments, the first modulus of the first passivation layer 207 is greater than or equal to the third modulus of the dielectric portions 2031c of the metalized portions 2031 of the semiconductor die 203, so that when the semiconductor package 200 is thermally expanded, since the side surfaces of the

dielectric portions

2031b and 2031c are covered by the first passivation layer 207, the

dielectric portions

2031b and 2031c are not easily deformed, peeled or delaminated, and the structure of the metalized portion 2031 in the semiconductor die 203 is further stabilized, thereby improving the reliability of the semiconductor package 200. In some embodiments, the first passivation layer 207 may encapsulate all of the side surface 203c of the semiconductor die 203. In some embodiments of the present application, the first passivation layer may wrap around all of the side surfaces of the metalized portion 2031 of the semiconductor die 203. In some embodiments of the present application, the first passivation layer may encapsulate all of the side surfaces of metallization 2031 of semiconductor die 203 and a portion or all of the side surfaces of narrower portion 2033a of semiconductor layer 2033. In some embodiments of the present application, the first passivation layer may encapsulate all of the side surfaces of metalized portion 2031 of semiconductor die 203 and all of the side surfaces of narrower portion 2033a and a portion of wider portion 2033b of semiconductor layer 2033. The first passivation layer 207 may not include a filler. The material of the first passivation layer 207 may be different from the material of the encapsulation 211.

A second passivation layer 209 may be adjacent the conductive pad 205 on the first surface 203 a. A second passivation layer 209 may be disposed on the first surface 203a of the semiconductor die 203 such that the first surface 203a of the semiconductor die 203 is covered by the second passivation layer 209. The second passivation layer 209 is connected to the first passivation layer 207. In some embodiments, the second passivation layer 209 and the first passivation layer 207 are comprised of substantially the same material, in some embodiments, second passivation layer 209 and first passivation layer 207 are comprised of different materials, the modulus of second passivation layer 209 is greater than the modulus of

dielectric portions

2031b and 2031c of metallization 2031 of semiconductor die 203, when semiconductor package 200 thermally expands, therefore, first surface 203a of semiconductor die 203 is also covered by second passivation layer 209, in addition to the side surfaces of

dielectric portions

2031b and 2031c being covered by first passivation layer 207, so that dielectric portion 2031b and dielectric portion 2031c are less susceptible to deformation, peeling or delamination with a better effect, to enhance the structural stability of the metallization in semiconductor die 203 and to better improve the reliability of semiconductor package 200. In some embodiments, the first passivation layer 207 and the second passivation layer 209 are different in thickness. In other embodiments of the present application, the first passivation layer 207 and the second passivation layer 209 may have the same thickness. The thicknesses of the first passivation layer 207 and the second passivation layer 209 may be set to any suitable values according to actual needs.

In other embodiments of the present application, the semiconductor package 200 may include only the first passivation layer 207 on the side surface 203c of the semiconductor die 203 and not the second passivation layer 209 on the first surface 203a of the semiconductor die 203.

The encapsulation 211 encapsulates the substrate 201, the semiconductor die 203, the conductive pad 205, the first passivation layer 207, and the second passivation layer 209. The encapsulation body may include a plurality of fillers 211 a. The material of the encapsulation may be an encapsulation material commonly used in the art. The plurality of fillers 211a of the encapsulation body 211 of fig. 2 are only illustrated in a part of the encapsulation body 211, and actually the plurality of fillers 211a are uniformly distributed in the whole encapsulation body 211.

The embodiment of the application provides a passivation layer made of a material with a modulus greater than that of a low-k interlayer dielectric at the edge of a semiconductor die where interlayer dielectric delamination is easy to occur, so as to cover the side surface of the semiconductor die, so as to ensure that the dielectric portion 2031b and the dielectric portion 2031c inside the semiconductor die are not easy to deform, peel or delaminate, thereby improving the reliability of the semiconductor package 200.

Fig. 4 is a longitudinal cross-sectional view of a semiconductor package 300 according to another embodiment of the present application, taken along line a-a shown in fig. 1. Referring to fig. 2, 3 and 4, the semiconductor package 300 shown in fig. 4 is different from the semiconductor package 200 shown in fig. 2 in that: the first passivation layer 307 of the semiconductor package 300 covers only a portion 303c' of the side surface 303c of the semiconductor die 303. A portion 303c' of the side surface 303c may include the metallization 2031 and the narrower portion 2033a of the semiconductor layer 2033 of fig. 3, such that the side surface of the metallization 2031 and the side surface of the narrower portion 2033a of the semiconductor layer 2033 are encapsulated by the first passivation layer 307. Another portion 303c "of the side surface 303c, i.e., the wider portion 2033b of the semiconductor layer 2033, is not covered by the first passivation layer 307.

The embodiment of the application provides a passivation layer made of a material with a modulus greater than that of the low-k interlayer dielectric at the edge of the metalized portion 2031 of the semiconductor die and the narrower portion 2033a of the semiconductor layer 2033 where interlayer dielectric delamination easily occurs, so as to cover the side surface of the semiconductor die, thereby ensuring that the metalized portion 2031 inside the semiconductor die and the narrower portion 2033a of the semiconductor layer 2033 are not easily deformed, peeled off or delaminated, and thus improving the reliability of the semiconductor package 200.

Fig. 5 is a schematic longitudinal cross-sectional view of a semiconductor package 400 according to still another embodiment of the present application, taken along line a-a shown in fig. 1. Referring to fig. 2, 3 and 5, the semiconductor package 400 shown in fig. 5 differs from the semiconductor package 200 shown in fig. 2 in that: the semiconductor die 403 of the semiconductor package 400 is electrically connected to the top surface 401a of the substrate 401 using a flip-chip bonding process by electrically connecting conductive pads 405 and metal balls 405a on the first surface 403a of the semiconductor die 403.

Fig. 6 is a schematic longitudinal cross-sectional view of a semiconductor package 500 according to another embodiment of the present application, taken along line a-a shown in fig. 1. Referring to fig. 3, 5 and 6, the semiconductor package 500 shown in fig. 6 is different from the semiconductor package 400 shown in fig. 5 in that: the first passivation layer 507 of the semiconductor package 500 encapsulates only a portion 503c' of the side surface 503c of the semiconductor die 503. A portion 503c' of the side surface 503c may include the metallization 2031 and the narrower portion 2033a of the semiconductor layer 2033 of fig. 3, such that the side surface of the metallization 2031 and the side surface of the narrower portion 2033a of the semiconductor layer 2033 are encapsulated by the first passivation layer 507. Another portion 503c "of the side surface 503c, i.e., the wider portion 2033b of the semiconductor layer 2033, is not covered by the first passivation layer 507.

Fig. 7a-7g are schematic flow diagrams of a process for fabricating a semiconductor package according to an embodiment of the present application, which can fabricate the semiconductor package 200 shown in fig. 2.

As shown in fig. 7a, a wafer 701 is provided without a passivation layer applied. The upper surface 701a of the wafer 701 may be provided with one or more conductive pads 703. The wafer 701 is cut by a half cut process (half cut) or any other suitable process so that the upper surface 701a of the wafer 701 has a groove 701 c. The groove 701c has a depth D1. The value of the depth D1 may be set according to actual needs. In some embodiments, the recess 701c divides and defines adjacent die regions.

As shown in fig. 7b, a first passivation 705 is disposed on the upper surface 701a of the wafer 701 and in the grooves 701c by a process commonly used in the art to cover the entire surfaces of the upper surface 701a and the grooves 701c of the wafer 701. The foregoing process includes, but is not limited to, spin-on (spin-on) of a polymer material, such as pi (polyimide), on the upper surface 701a and the recess 701c of the wafer 701 to form a flat surface of the first passivation 705.

As shown in fig. 7c, the thickness of the first passivation material 705 is reduced by processes commonly used in the art, including, but not limited to, plasma etching processes, chemical mechanical polishing processes, and combinations thereof. In some embodiments, the thickness of the first passivation 705 is reduced until the first passivation 705 is substantially planar with the top surface 703a of the conductive pad 703. This step may determine the thickness of the second passivation layer 209 of fig. 2. The thickness of the second passivation layer 209 may be set according to actual needs. In some embodiments, a second passivation material (not shown) that is the same as or different from the first passivation material 705 may be disposed on the top surface 701a and covers or partially exposes the plurality of conductive pads 703 before the formation of the recess 701c, and then, in fig. 7b, the first passivation material 705 is disposed on the second passivation material and in the recess 701c, and the thickness of the first passivation material 705 is reduced as in fig. 7c until the second passivation material is exposed and substantially coplanar with the top surface 703a of the conductive pads 703. In the manner described above, the second passivation material forms the second passivation layer 209 of fig. 2, which may be the same or different material composition as the first passivation layer 207.

As shown in fig. 7d, a protective tape 707 is provided on the upper surface 701a of the wafer 701 for subsequent processing to polish the lower surface 701b of the wafer 701.

As shown in fig. 7e, the lower surface 701b of the wafer 701 is ground until the first passivation material 705 in the recess 701c is exposed to obtain a semiconductor die of a desired height.

As shown in fig. 7f, the polished wafer 701 is placed on a mounting tape 709.

As shown in fig. 7g, the wafer 701 is diced to separate the wafer 701 into individual semiconductor dies 203. A second passivation layer 209 is adjacent the conductive pad 205 on the first surface 203 a. A second passivation layer 209 is disposed on the first surface 203a of the semiconductor die 203 such that the first surface 203a of the semiconductor die 203 is covered by the second passivation layer 209. The first passivation layer 207 is disposed on the side surface 203c of the semiconductor die 203 such that the side surface 203c of the semiconductor die 203 is covered by the first passivation layer 207. The cutting facet width used in the step of fig. 7g may determine the thickness of the first passivation layer 207 on the individual semiconductor die 203. The thickness of the first passivation layer 207 may be set according to actual needs.

Next, a semiconductor die 203 provided with a first passivation layer 207 and a second passivation layer 209 may be disposed on the top surface 201a of the substrate 201. Semiconductor die 203 may then be electrically connected to substrate 201 by a wire bonding process. Next, an encapsulation 211 is injection molded to encapsulate the substrate 201, the semiconductor die 203, the conductive pad 205, the first passivation layer 207, and the second passivation layer 209.

Fig. 8a-8g are schematic flow diagrams of manufacturing a semiconductor package according to another embodiment of the present application, which can manufacture the semiconductor package 300 shown in fig. 4.

As shown in fig. 8a, a wafer 801 is provided without a passivation layer applied. The upper surface 801a of the wafer 801 may be provided with one or more conductive pads 803. The wafer 801 is cut by a half cut process (half cut) or any other suitable process so that the upper surface 801a of the wafer 801 has grooves 801 c. Groove 801c has a depth D2. The value of the depth D2 may be set according to actual needs. In fig. 7a and 8a, if the thickness of the final semiconductor die is equal, the depth D2 of the groove 801c is shorter than the depth D1 of the groove 701 c. In some embodiments, the depth D2 of groove 801c corresponds to the height of the narrower portion of the final semiconductor die. In some embodiments, the recess 801c divides and defines adjacent die regions.

As shown in fig. 8b, a first passivation 805 is disposed on the upper surface 801a and the groove 801c of the wafer 801 by a process commonly used in the art to cover the entire surfaces of the upper surface 801a and the groove 801c of the wafer 801. The foregoing process includes, but is not limited to, spin-on (spin-on) polymer material, such as pi (polyimide), on the upper surface 801a and the recess 801c of the wafer 801 to form a planar surface of the first passivation 805.

As shown in fig. 8c, the thickness of the first passivation material 805 is reduced by processes commonly used in the art, including, but not limited to, plasma etching processes, chemical mechanical polishing processes, and combinations thereof. In some embodiments, the thickness of the first passivation material 705 is reduced until the first passivation material 805 is substantially planar with the upper surface 803a of the conductive pad 803. This step may determine the thickness of the second passivation layer 309 as in fig. 4. The thickness of the second passivation layer 309 may be set as desired. In some embodiments, a second passivation material (not shown) that is the same as or different from the first passivation material 805 may be disposed on the top surface 801a and covers or partially exposes the plurality of conductive pads 803 before the formation of the groove 801c, and in fig. 8b, the first passivation material 805 is disposed on the second passivation material and in the groove 801c, and the thickness of the first passivation material 805 is reduced as in fig. 8c until the second passivation material is exposed and substantially coplanar with the top surface 803a of the conductive pads 803. In the manner described above, the second passivation material forms a second passivation layer 309 as in fig. 4, which may be of the same or different material composition as the first passivation layer 307.

As shown in fig. 8d, a protective tape 807 is disposed on the upper surface 801a of the wafer 801 for subsequent processing to polish the lower surface 801b of the wafer 801.

As shown in fig. 8e, the lower surface 801b of the wafer 801 is polished until the distance from the bottom of the groove 801c to the lower surface 801b of the wafer conforms to the predetermined thickness D3. In some embodiments, thickness D3 corresponds to the height of the wider portion of the final semiconductor die.

As shown in fig. 8f, the polished wafer 801 is placed on a mounting tape 809.

As shown in fig. 8g, the wafer 801 is diced to separate the wafer 801 into individual semiconductor dies 303. A second passivation layer 309 is adjacent the conductive pad 305 on the first surface 303 a. A second passivation layer 309 is disposed on the first surface 303a of the semiconductor die 303 such that the first surface 303a of the semiconductor die 303 is covered by the second passivation layer 309. A first passivation layer 307 is disposed on a portion 303c' of the side surface 303c of the semiconductor die 303. A portion 303c' of the side surface 303c may include the metallization 2031 and the narrower portion 2033a of the semiconductor layer 2033 such that the side surface of the metallization 2031 and the side surface of the narrower portion 2033a of the semiconductor layer 2033 are encapsulated by the first passivation layer 307. Another portion 303c "of the side surface 303c, i.e., the wider portion 2033b of the semiconductor layer 2033, is not covered by the first passivation layer 307. The cutting facet width used by the fig. 8g step may determine the thickness of the first passivation layer 307 on the individual semiconductor die 303. The thickness of the first passivation layer 307 can be set according to actual needs.

Next, a semiconductor die 303 provided with a first passivation layer 307 and a second passivation layer 309 may be disposed on the top surface 301a of the substrate 301. Semiconductor die 303 may then be electrically connected to substrate 301 by a wire bonding process. Next, an encapsulation 311 is formed by injection molding to encapsulate the substrate 301, the semiconductor die 303, the conductive pad 305, the first passivation layer 307, and the second passivation layer 309.

The technical content and technical features of the present application have been disclosed as above, however, those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present application without departing from the spirit of the present application. Therefore, the protection scope of the present application should not be limited to the disclosure of the embodiments, but should include various alternatives and modifications without departing from the scope of the present application, which is encompassed by the claims of the present application.

Claims

1. A semiconductor package, comprising:

a semiconductor die having a first surface, a second surface opposite the first surface, and a side surface connecting the first surface and the second surface;

a conductive pad adjacent to the first surface;

a first passivation layer on the side surface of the semiconductor die and having a first modulus; and

an encapsulation encapsulating the semiconductor die, the conductive pad, and the first passivation layer.

2. The semiconductor package of claim 1, wherein the semiconductor die comprises a metalized portion adjacent to the first surface, the metalized portion comprising a conductive line and a dielectric portion surrounding the conductive line, wherein the dielectric portion comprises a second modulus lower than the first modulus.

3. The semiconductor package of claim 1, wherein the encapsulation comprises a plurality of fillers.

4. The semiconductor package of claim 1, wherein the first passivation layer does not include a filler.

5. The semiconductor package of claim 1, further comprising a second passivation layer on the first surface of the semiconductor die, the second passivation layer connected to the first passivation layer.

6. The semiconductor package of claim 2, wherein the first passivation layer is in contact with the dielectric portion of the metallization.

7. The semiconductor package of claim 6, wherein the semiconductor die further comprises a semiconductor layer stacked with the metallization, the first passivation layer further being in contact with the semiconductor layer.

8. The semiconductor package of claim 5, wherein the second passivation layer is substantially coplanar with the conductive pad.

9. The semiconductor package of claim 7, wherein the semiconductor layer comprises a narrower portion proximate the first surface and a wider portion proximate the second surface, the first passivation layer being in contact with the narrower portion.

10. The semiconductor package of claim 9, wherein the narrower portion is in contact with the metallization.

11. A semiconductor package, comprising:

a substrate having a top surface and a bottom surface opposite the top surface;

a semiconductor die electrically connected to the top surface, wherein semiconductor die comprises a side surface substantially perpendicular to the top surface;

a first passivation layer on the side surface and having a first modulus; and

an encapsulation encapsulating the semiconductor die and the first passivation layer.

12. The semiconductor package of claim 11, wherein the side surface connects a first surface of the semiconductor die and a second surface of the semiconductor die opposite the first surface.

13. The semiconductor package of claim 12, wherein the semiconductor die comprises a metalized portion adjacent to the first surface, the metalized portion comprising a conductive line and a dielectric portion surrounding the conductive line, wherein the dielectric portion comprises a second modulus lower than the first modulus.

14. The semiconductor package of claim 12, further comprising a conductive pad adjacent to the first surface and a second passivation layer on the first surface, the second passivation layer being substantially coplanar with the conductive pad.

15. The semiconductor package of claim 14, wherein the semiconductor die is electrically connected to the substrate through the conductive pad via wire bonding or flip chip bonding.

16. The semiconductor package of claim 14, wherein the first passivation layer and the second passivation layer are comprised of substantially the same material.

17. The semiconductor package of claim 14, wherein a thickness of the first passivation layer and a thickness of the second passivation layer are different.

18. The semiconductor package of claim 13, wherein the first passivation layer is in contact with a dielectric portion of the metallization.

19. The semiconductor package of claim 11, wherein the first passivation layer covers all of the side surface of the semiconductor die.

20. The semiconductor package of claim 11, wherein the bottom surface of the substrate comprises a plurality of conductive terminals.