CN210112175U

CN210112175U - SPDIF (shortest Path first) receiving controller, FPGA (field programmable Gate array) chip and electronic equipment

Info

Publication number: CN210112175U
Application number: CN201921117902.8U
Authority: CN
Inventors: 葛庆国
Original assignee: Shanghai First Semiconductor Technology Co Ltd
Current assignee: Shanghai First Semiconductor Technology Co Ltd
Priority date: 2019-07-17
Filing date: 2019-07-17
Publication date: 2020-02-21
Anticipated expiration: 2029-07-17

Abstract

The utility model belongs to the technical field of the audio transmission, a SPDIF receives controller, FPGA chip and electronic equipment is provided. The utility model discloses in, SPDIF receiving control ware includes: the device comprises a serial-parallel conversion circuit, a frame header detection circuit, a BMC decoding module, a data analysis circuit and a check detection circuit; the serial-parallel conversion circuit is used for receiving the SPDIF input data and performing serial-parallel conversion on the received SPDIF input data; the frame header detection circuit is used for receiving the bus data, performing frame header search and detection on the bus data and generating a frame timing signal; the BMC decoding module is used for decoding the bus data according to the frame timing signal; the data analysis circuit is used for analyzing the decoded data according to the frame timing signal; the verification detection circuit is used for receiving the analysis data and performing data verification on the analysis data to obtain a verification result. The SPDIF receiving controller realizes the transmission and the receiving of audio data, has low power consumption, reduces logic resources and simultaneously reduces the difficulty of product development.

Description

SPDIF (shortest Path first) receiving controller, FPGA (field programmable Gate array) chip and electronic equipment

Technical Field

The utility model belongs to the technical field of an audio transmission technique and specifically relates to a SPDIF receives controller, FPGA chip and electronic equipment.

Background

SPDIF (Sony/Philips Digital Interface Format) is a Digital audio transmission Interface, generally uses optical fiber and coaxial line for output, outputs audio signals to a decoder, can keep high fidelity output results, and is widely applied to DTS (Digital cinema System).

The existing audio receiving controller adopts single-sideband modulation to realize frequency shift, and is realized in a hardware mode in many ways, so that the software portability is poor, the hardware and the software are not convenient to upgrade, the power consumption is high in the whole data transmission process, the required resource consumption is large, and the data transmission is not facilitated.

SUMMERY OF THE UTILITY MODEL

Based on this, the embodiment of the utility model provides an SPDIF receives controller, FPGA chip and electronic equipment for audio data receiver has low power dissipation and stronger portability and maintainability, improves the development speed of product.

An SPDIF reception controller comprising:

the SPDIF reception controller includes: the device comprises a serial-parallel conversion circuit, a frame header detection circuit, a BMC decoding module, a data analysis circuit and a check detection circuit;

the serial-parallel conversion circuit is used for receiving SPDIF input data and performing serial-parallel conversion on the received SPDIF input data to obtain bus data;

the frame header detection circuit is used for receiving the bus data, performing frame header search and detection on the bus data and generating a frame timing signal;

the BMC decoding module is used for receiving the bus data and the frame timing signal and decoding the bus data according to the frame timing signal to obtain decoded data;

the data analysis circuit is used for receiving the frame timing signal and the decoded data and analyzing the decoded data according to the frame timing signal to obtain analysis data;

the verification detection circuit is used for receiving the analysis data and performing data verification on the analysis data to obtain a verification result.

Further, the parsing data includes audio data, a valid flag, a user bit, and a channel status bit.

Further, the frame header detection circuit is configured to perform frame header detection on the input bus data according to a configuration of the frame header and a correlation of a frame header code type.

Further, the BMC decoding module is configured to decode the bus data with the frame timing signal provided by the frame header detection circuit to obtain the decoded data when it is determined that the level of the head of each bit of the input SPDIF data is different from the level of the end of the previous bit.

Further, the frame header detection circuit is further configured to determine, if a starting subframe signal is detected, a starting subframe corresponding to the starting subframe signal as the starting position of the searched bus data, so as to implement data synchronization.

Further, the input working clock rate of the SPDIF receiving controller is greater than or equal to 256Fs, the audio sampling rate supports the range of 8Khz to 192Khz, and the audio data bit width supports the range of 16 bits to 24 bits.

Further, the frame timing signal includes a block timing signal, a left channel timing signal, and a right channel timing signal.

Further, the serial-parallel conversion circuit includes a shift register.

An FPGA chip comprises the SPDIF receiving controller.

An electronic device comprises the FPGA chip.

Compared with the prior art, the embodiment of the utility model beneficial effect who exists is: the utility model discloses an SPDIF receiving controller including serial-parallel conversion circuit, frame head detection circuitry, BMC decoding module, data analysis circuit and check-up detection circuitry for audio data obtains high-efficient transmission and receipt, and the low power dissipation, and logical resource is less. Meanwhile, the SPDIF controller has transportability, so that the development difficulty of a user can be reduced, and the product development speed is increased.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor.

Fig. 1 is a schematic diagram of an SPDIF receiving controller provided by an embodiment of the present invention;

fig. 2 is a schematic diagram of an FPGA chip according to another embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.

The following description will be made in detail with reference to fig. 1 to 2 to implement the present invention:

fig. 1 shows a schematic circuit structure diagram of an SPDIF receiving controller according to an embodiment of the present invention, and for convenience of description, only the portions related to the embodiment are shown, which are detailed as follows:

as shown in fig. 1, an embodiment of the present invention provides an SPDIF receiving controller 100, which includes a serial-parallel conversion circuit 10, a frame header detection circuit 20, a BMC decoding module 30, a data parsing circuit 40, and a verification detection circuit 50.

The serial-parallel conversion circuit 10 is connected to the frame header detection circuit 20, the BMC decoding module 30, the data analysis circuit 40, and the check detection circuit 50. The frame header detection circuit 20 is connected to the BMC decoding module 30. The data analysis circuit 40 is connected to both the frame header detection circuit 20 and the BMC decoding module 30.

The serial-to-parallel conversion circuit 10 is configured to receive SPDIF input data, and perform serial-to-parallel conversion on the received SPDIF input data to obtain bus data.

A frame header detection circuit 20, configured to receive the bus data, perform frame header search and detection on the bus data, and generate a frame timing signal;

the BMC decoding module 30 is configured to receive the bus data and the frame timing signal, and decode the bus data according to the frame timing signal to obtain decoded data;

a data analysis circuit 40, configured to receive the frame timing signal and the decoded data, and analyze the decoded data according to the frame timing signal to obtain analysis data;

and the verification detection circuit 50 is configured to receive the analysis data and perform data verification on the analysis data to obtain a verification result.

Specifically, the serial-parallel conversion circuit 10 completes serial-parallel conversion of SPDIF input data, and converts high-speed data into parallel bus data, and since the total data throughput is not changed, the working clock is reduced by 2 times, and the circuit can reduce the internal working clock by one time. After the serial input SPDIF input data is input into the serial-parallel conversion circuit 10, that is, after n branches in the circuit are passed through, finally, parallel bus data with n bit widths, that is, bus data in this embodiment, is output in parallel. The SPDIF input Data refers to Audio Data of a SONY digital Audio interface and a PHILIPS digital Audio interface, the bus Data refers to Data obtained by parallel processing the SPDIF input Data, the SPDIF input Data is composed of 192 frames, each Frame is composed of 2 subframes, and is divided into Channel a and Channel B channels, the Channel a and the Channel B channels correspond to a left Channel and a right Channel respectively, the length of the subframe Data is 32bits, the subframe Data comprises a header (Preamble), auxiliary Data (aux.data), Audio Data (Audio Data), and four bits of information and a check code, that is, one subframe is 32bits and 4Bytes, one Frame is 8Bytes, one Block is 192x 8-1536 Bytes, and each Block can transmit 192 double-Channel samples in total. It can be understood that the serial-parallel conversion circuit in this embodiment reduces the internal operating clock by one time, thereby reducing the power consumption.

In one embodiment, the serial-parallel conversion circuit may be implemented by using a register, a dual port ram (dual ram), an SRAM, an SDRAM, or a FIFO. Preferably, the serial-parallel conversion circuit includes a shift register.

Specifically, the frame header detection circuit 20 is configured to receive bus data, perform frame header search and detection on the bus data, and generate a frame timing signal, where if there are 3 consecutive 0 s or 3 consecutive 1 s in the bus data in the SPDIF frame format, the bus data also conforms to the X, Y, Z coding characteristic, and the X, Y, Z three configurations respectively represent starting subframes Channel Z of the subframe Channel a, the subframe Channel B, and the Block. X encoding is characterized by encoding 11101000 or 00010111; y-coding is characterized by 11100010 or 00011101; z-coding is characterized by 11100100 or 00011011. The frame header detection circuit carries out frame header search on the bus data according to different characteristics and code type relevance of the three frame headers, detects a data string in a subframe format in the bus data stream, and sends a corresponding indication signal when the data string is effective.

Optionally, the frame timing signal comprises a block timing signal, a left channel timing signal and a right channel timing signal. The block timing signal is used for indicating data insertion or identification of a starting subframe, the left Channel timing signal is used for indicating data insertion or identification of a subframe Channel A, and the right Channel timing signal is used for indicating data insertion or identification of a subframe Channel B.

Specifically, in the BMC decoding module 30, BMC refers to a Binary Mark Code (BMC), belongs to a phase modulation (phase modulation) encoding method, and is an encoding method for mixing a clock signal and a data signal together and transmitting the mixture. The bus data is BMC decoded according to the searched frame header timing, and the reason is that when the data is 1, the potential is changed once (such as 0- >1 or 1- >0) in the clock period to change the data into the data with two different potentials to 10 or 01, and when the data is 0, the potential is not changed to 11 or 00. The BMC decoding circuit module decodes the data part according to the frame timing signal provided by the SPDIF frame header detection circuit, namely, when the income is detected to be 10 or 01, the judgment is 1, and when the income is detected to be 11 or 00, the judgment is 0, so that the SPDIF protocol of the bus data can be decoded quickly and accurately, and the decoded data can be obtained.

Specifically, the data parsing circuit 40 is configured to complete protocol parsing on a parsed SPDIF protocol included in the decoded data according to a frame timing signal provided by the SPDIF frame header detection circuit, parse audio data, a User bit, a Validity bit, and Channel status bit data from the parsed SPDIF protocol, and send the audio data, the User bit, the Validity bit, and the Channel status bit data to the User port.

Specifically, the check detecting circuit 50 is configured to check data including audio data, a User bit, a Validity bit, and a Channel status bit according to a frame timing signal provided by the SPDIF frame header detecting circuit, that is, in the SPDIF protocol, a last bit of a subframe is a check bit, and is used to determine whether an error abnormality occurs in data transmission of the current subframe. The check detection circuit performs exclusive or operation on all sub-frame bits (except X, Y, Z) according to protocol requirements, compares the current calculation result with a check bit sent by an opposite terminal, judges whether the calculation result is consistent with the check bit, compares the result with the check bit, and outputs an error or correct indication to a user port through a check error identifier (O _ parity _ check _ error) signal to form an SPDIF receiving controller implementation circuit. The controller can be laid out and wired to various series of FPGA products, and the universality and portability of codes are improved.

It is to be understood that each circuit in the SPDIF receiving controller described above may be implemented by using internal logic resources of the FPGA.

In this embodiment, the SPDIF receiving controller reduces the internal working clock by one time by using the serial-parallel conversion circuit, so as to implement SPDIF data analysis and BMC decoding, and has the characteristics of low power consumption, less resources, portability, and the like. Furthermore, after the controller is called by cloud software, the controller can be used for synthesis, layout and wiring and is suitable for series FPGA products such as GW1N, GW1NS, GW1NZ, GW2A, GW2AR and the like, and the controller has good code transplantation and universality.

Further, as a preferred embodiment of the present invention, the analysis data includes audio data, valid flag, user bit and channel status bit.

Specifically, the parsed data is a standard audio data packet including audio data, a valid flag, a user bit and a channel status bit, which can provide a flexible data communication channel.

Further, as a preferred embodiment of the present invention, the frame header detection circuit is used for performing frame header detection on the input bus data according to the configuration of the frame header and the correlation of the frame header code pattern.

Specifically, the configuration of the header refers to the configuration of the beginning of the sub-frame in the bus data, and there are X, Y, Z configurations. The frame header type refers to the form of the combination of bit sequences in the bus data. Specifically, whether the bus data is the frame header or the data is judged according to the configuration of the frame header and the correlation of the frame header code type. The frame header detection in the embodiment can provide a basic time reference structure for decoding, thereby being beneficial to realizing the frame synchronization process.

Further, as a preferred embodiment of the present invention, the BMC decoding module is configured to decode the bus data by using the frame timing signal provided by the frame header detecting circuit when the level of the beginning of each bit of the input SPDIF data is determined to be different from the level of the end of the previous bit, so as to obtain decoded data.

Further, as the utility model discloses a preferred embodiment, frame head detection circuitry carries out the frame head according to the configuration of frame head and the relevance of frame head code pattern to the bus data of input and detects the back, and frame head detection circuitry still is used for: and if the initial subframe signal is detected, determining the initial subframe corresponding to the initial subframe signal as the initial position of the searched bus data so as to realize data synchronization.

Further, as a preferred embodiment of the present invention, the input operation clock rate of the SPDIF receiving controller is greater than or equal to 256Fs, the audio sampling rate supports the range of 8Khz to 192Khz, and the bit width of the audio data supports the range of 16 bits to 24 bits.

Further, the present invention also provides an FPGA chip 300, as shown in fig. 2, where the FPGA chip 300 includes the SPDIF receiving controller 100 and the memory controller 200. It should be noted that, since the SPDIF receiving controller 100 in the FPGA chip 300 provided by the embodiment of the present invention is the same as the SPDIF receiving controller shown in fig. 1, the specific working principle of the SPDIF receiving controller 1 in the FPGA chip 300 provided by the embodiment of the present invention can refer to the foregoing detailed description about fig. 1, and is not repeated here.

Further, the utility model also provides an electronic equipment, this electronic equipment includes the FPGA chip. It should be noted that, because the SPDIF receiving controller 100 included in the FPGA chip 300 of the electronic device provided by the embodiment of the present invention is the same as the SPDIF receiving controller 100 shown in fig. 1, the specific working principle of the FPGA chip 300 of the electronic device provided by the embodiment of the present invention can refer to the foregoing detailed description about fig. 1, and is not repeated here.

The above-mentioned embodiments are only used for illustrating the technical solution of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.

Claims

1. An SPDIF reception controller, comprising: the device comprises a serial-parallel conversion circuit, a frame header detection circuit, a BMC decoding module, a data analysis circuit and a check detection circuit;

2. The SPDIF receiving controller according to claim 1, wherein said parsed data includes audio data, valid identification, user bits, and channel status bits.

3. The SPDIF receiving controller according to claim 1, wherein the frame header detection circuit is configured to perform frame header detection on the input bus data according to the configuration of the frame header and the correlation of frame header patterns.

4. The SPDIF receiving controller according to claim 1, wherein said BMC decoding module is configured to decode the bus data by using the frame timing signal provided by the frame header detecting circuit to obtain the decoded data, when it is determined that the level of the head of each bit of the input SPDIF data is different from the level of the end of the previous bit.

5. The SPDIF receiving controller according to claim 1 or 3, wherein said frame header detection circuit is further configured to:

and if the starting subframe signal is detected, determining the starting subframe corresponding to the starting subframe signal as the searched starting position of the bus data so as to realize data synchronization.

6. The SPDIF receiving controller according to claim 1, wherein said SPDIF receiving controller has an input operating clock rate greater than or equal to 256Fs, an audio sampling rate supporting the range of 8Khz to 192Khz, and an audio data bit width supporting the range of 16 bits to 24 bits.

7. The SPDIF receiving controller of claim 1, wherein the frame timing signal comprises a block timing signal, a left channel timing signal and a right channel timing signal.

8. The SPDIF receiving controller according to claim 1, wherein said serial-parallel conversion circuit includes a shift register.

9. An FPGA chip comprising the SPDIF receiving controller of any one of claims 1 to 6.

10. An electronic device, characterized in that it comprises an FPGA chip according to claim 9.