CN219554947U - Low-cost MOS tube driving circuit - Google Patents
Low-cost MOS tube driving circuit Download PDFInfo
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- CN219554947U CN219554947U CN202320218774.6U CN202320218774U CN219554947U CN 219554947 U CN219554947 U CN 219554947U CN 202320218774 U CN202320218774 U CN 202320218774U CN 219554947 U CN219554947 U CN 219554947U
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Abstract
The utility model relates to the technical field of driving circuits, in particular to a low-cost MOS tube driving circuit which comprises a reverse totem pole circuit, a driving current circuit, a post-stage circuit, PWM (pulse width modulation), a Gate-MOS tube, a VI (voltage-dependent semiconductor) low-end power supply and a Vh high-end power supply, wherein the driving current circuit is respectively connected with the reverse totem pole circuit, the post-stage circuit and the Vh high-end power supply, the PWM is connected with the reverse totem pole circuit, the VI low-end power supply is connected with the reverse totem pole circuit, and the Gate-MOS tube is connected with the post-stage circuit.
Description
Technical Field
The utility model relates to the technical field of driving circuits, in particular to a low-cost MOS tube driving circuit.
Background
The most remarkable characteristic of the MOS tube (metal oxide semiconductor field effect tube) is good in switching characteristic, so that the MOS tube is widely applied to circuits requiring electronic switching, such as a switching power supply and motor driving, illumination dimming and the like, and the driving of the MOS tube plays a decisive role in the working effect of the MOS tube.
The direct driving of the power supply IC is the most common driving mode and the simplest driving mode, and in the power supply design, engineers often face the problem of insufficient driving current of the control IC or the problem of excessive power consumption of the control IC due to gate driving loss. To alleviate this problem, engineers typically use external drivers, semiconductor manufacturers have ready MOSFET integrated circuit driver solutions, but this is usually not the least costly solution, driving the OS tube, in effect charging and discharging the gate capacitance. If the parasitic capacitance of the selected MOS tube is relatively large, and the driving capability in the power IC is insufficient, the driving capability of the power IC needs to be enhanced on the driving circuit, a totem pole circuit is often used for enhancing the driving capability of the power IC, the totem pole is respectively a transistor, an upper transistor is NPN, a c pole is connected with a positive power supply, a lower transistor is PNP, and the c pole is connected with the negative power supply. Two poles b are connected together, the input is connected, the e of the upper tube and the e of the lower tube are connected together, the output is connected, the totem pole can be used for matching voltage or improving the driving capability of an IO port, but under the conditions of low-voltage application, wide-voltage application and double-voltage application, the totem pole structure can not meet the output requirement, and a plurality of existing MOS driving ICs comprise very few gate voltage limiting structures.
Disclosure of Invention
The utility model provides a low-cost MOS tube driving circuit, which aims to enable MOS driving to be used under the conditions of low-voltage application, wide-voltage application and dual-voltage application and enable MOS driving IC to have a gate voltage limiting structure.
To achieve the purpose, the utility model adopts the following technical scheme:
the MOS tube driving circuit comprises a reverse totem pole circuit, a driving current circuit, a rear-stage circuit, a PWM, a Gate-MOS tube, a VI low-end power supply and a Vh high-end power supply, wherein the driving current circuit is respectively connected with the reverse totem pole circuit, the rear-stage circuit and the Vh high-end power supply, the PWM is connected with the reverse totem pole circuit, the VI low-end power supply is connected with the reverse totem pole circuit, and the Gate-MOS tube is connected with the rear-stage circuit.
Further, the reverse totem pole circuit comprises a resistor R1, a triode Q2, a resistor R2 and a resistor R3, wherein one end of the resistor R1 is connected with PWM, the emitter of the triode Q1 and the emitter of the triode Q2 are both connected with the other end of the resistor R1, one end of the resistor R2 is connected with a VI low-end power supply, the other end of the resistor R2 is respectively connected with a base electrode of the triode Q1 and a base electrode of the triode Q2, one end of the resistor R3 is connected with the other end of the resistor R2, and the other end of the resistor R3 is grounded;
the driving current circuit comprises a triode Q3 and a triode Q4, wherein the base electrode of the triode Q3 is connected with the collector electrode of the triode Q1, the base electrode of the triode Q4 is connected with the collector electrode of the triode Q2, the emitter electrode of the triode Q3 is connected with a Vh high-end power supply, the emitter electrode of the triode Q4 is grounded, and the collector electrode of the triode Q3 is connected with the collector electrode of the triode Q4;
the rear-stage circuit comprises a triode Q5, a resistor R4, a resistor R5 and a resistor R6, wherein the base electrode of the triode Q5 is respectively connected with one end of the resistor R5 and one end of the resistor R6, the other end of the resistor R5 and the emitting electrode of the triode Q5 are both connected to a Vh high-end power supply, one end of the resistor R4 is connected with the collecting electrode of the triode Q3, the other end of the resistor R4 is connected with the other end of the resistor R6, the other end of the resistor R6 is connected with the other end of the resistor R2, and the other end of the resistor R6 is connected with a Gate-MOS tube.
Further, the reverse totem pole circuit comprises an inverter, a resistor R1, a triode Q2, a resistor R2 and a resistor R3, wherein one end of the inverter is connected with PWM, the other end of the inverter is connected with one end of the resistor R1, the emitter of the triode Q1 and the emitter of the triode Q2 are both connected with the other end of the resistor R1, one end of the resistor R2 is connected with a VI low-end power supply, the other end of the resistor R2 is respectively connected with a base electrode of the triode Q1 and a base electrode of the triode Q2, one end of the resistor R3 is connected with the other end of the resistor R2, and the other end of the resistor R3 is grounded;
the driving current circuit comprises a triode Q3 and a triode Q4, wherein the base electrode of the triode Q3 is connected with the collector electrode of the triode Q1, the base electrode of the triode Q4 is connected with the collector electrode of the triode Q2, the emitter electrode of the triode Q3 is connected with a Vh high-end power supply, the emitter electrode of the triode Q4 is grounded, and the collector electrode of the triode Q3 is connected with the collector electrode of the triode Q4;
the rear-stage circuit comprises a triode Q5, a resistor R4, a resistor R5 and a resistor R6, wherein the base electrode of the triode Q5 is respectively connected with one end of the resistor R5 and one end of the resistor R6, the other end of the resistor R5 and the emitting electrode of the triode Q5 are both grounded, one end of the resistor R4 is connected with the collecting electrode of the triode Q5, the other end of the resistor R4 is connected with the other end of the resistor R6, and the other end of the resistor R6 is connected with a Gate-MOS tube.
Further, a signal level transformer is arranged between the reverse totem pole circuit and the PWM, one side of one end of the signal level transformer is connected with one end of the resistor R1, the other side of the signal level transformer is grounded, one side of the other end of the signal level transformer is connected with the PWM, and the other side of the signal level transformer is grounded.
The utility model has the beneficial effects that:
1. according to the low-cost MOS tube driving circuit, the problem that the totem pole structure cannot meet the output requirement under the conditions of low-voltage application, wide-voltage application and double-voltage application in the prior art can be solved by designing the reverse totem pole circuit, the driving current circuit and the rear-stage circuit, and meanwhile, the gate voltage limiting structure is added in the MOS driving IC.
2. Through designing the reverse totem pole circuit, the driving current circuit and the back-stage circuit, the MOS tube with low-end voltage and PWM matched together to drive high-end voltage and the MOS tube with high gate voltage requirement driven by PWM signals with small amplitude can be realized, in the circuit design, the driving enhancement of bipolar PWM to the MOS tube can be realized by adopting a signal level transformer, and the switching loss is reduced.
3. Compared with the existing MOS tube driving in an integrated circuit mode, the MOS tube driving in a discrete device mode can greatly save the circuit cost.
Drawings
In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the utility model, and that other drawings can be obtained from them without inventive faculty for a person skilled in the art.
FIG. 1 is an overall circuit diagram of the present utility model;
FIG. 2 is a circuit diagram of a PMOS transistor according to the present utility model;
FIG. 3 is a circuit diagram of an NMOS transistor according to the present utility model;
FIG. 4 is a diagram of a bipolar PWM driving PMOS of the present utility model;
FIG. 5 is a diagram of a bipolar PWM driving NMOS according to the present utility model;
Detailed Description
The utility model is further described with reference to the following detailed drawings in order to make the technical means, the creation characteristics, the achievement of the purpose and the effect of the implementation of the utility model easy to understand.
Referring to fig. 1, a low-cost MOS transistor driving circuit includes a reverse totem pole circuit, a driving current circuit, a post-stage circuit, a PWM, a Gate-MOS transistor, a VI low-side power supply, and a Vh high-side power supply, wherein the driving current circuit is connected to the reverse totem pole circuit, the post-stage circuit, and the Vh high-side power supply, the PWM is connected to the reverse totem pole circuit, the VI low-side power supply is connected to the reverse totem pole circuit, the Gate-MOS transistor is connected to the post-stage circuit, in the circuit design, the MOS transistor is widely used in a circuit requiring an electronic switch due to a significant switching characteristic, the PWM signal and the VI low-side power supply drive the Gate-MOS transistor of high voltage through the reverse totem pole circuit, the driving current circuit, and the post-stage circuit, and the VI low-side power supply can be identical, but the voltage of the VI low-side power supply should not exceed the voltage of the Vh high-side power supply, the reverse totem pole circuit is isolated in the circuit, and the PMOS transistor is limited in the voltage by the voltage, and the MOS transistor is limited by the voltage limiting the voltage.
Referring to fig. 2, the reverse totem pole circuit includes a resistor R1, a triode Q2, a resistor R2, and a resistor R3, wherein one end of the resistor R1 is connected with PWM, the emitter of the triode Q1 and the emitter of the triode Q2 are both connected with the other end of the resistor R1, one end of the resistor R2 is connected with a VI low-end power supply, the other end is connected with a base electrode of the triode Q1 and a base electrode of the triode Q2 respectively, one end of the resistor R3 is connected with the other end of the resistor R2, and the other end is grounded;
the driving current circuit comprises a triode Q3 and a triode Q4, wherein the base electrode of the triode Q3 is connected with the collector electrode of the triode Q1, the base electrode of the triode Q4 is connected with the collector electrode of the triode Q2, the emitter electrode of the triode Q3 is connected with a Vh high-end power supply, the emitter electrode of the triode Q4 is grounded, and the collector electrode of the triode Q3 is connected with the collector electrode of the triode Q4;
the post-stage circuit comprises a triode Q5, a resistor R4, a resistor R5 and a resistor R6, wherein the base electrode of the triode Q5 is respectively connected with one end of the resistor R5 and one end of the resistor R6, the other end of the resistor R5 and the emitter electrode of the triode Q5 are both connected to a Vh high-end power supply, one end of the resistor R4 is connected with the collector electrode of the triode Q3, the other end of the resistor R4 is connected with the other end of the resistor R6, the other end of the resistor R6 is connected with the other end of the resistor R2, the other end of the resistor R6 is connected with a Gate-MOS tube, the low-voltage application, the wide-voltage application and the wide-voltage application are required to be paid attention in the design of the MOS tube driving circuit, the low-voltage application refers to the fact that if a 5V power supply is used, if a traditional totem pole structure is used, the voltage which is actually and finally applied to Gate is only 4.3V because of about 0.7V is caused by the be present between the bes of the triode, the same problem occurs in the case of using 3V or other low voltage power supply, the wide voltage application means that the input voltage is not a fixed value, and the input voltage can be changed along with time or other factors, the change causes the driving voltage provided to the Gate-MOS tube by PWM to be unstable, in order to ensure that the Gate-MOS tube is safe under high Gate voltage, a plurality of Gate-MOS tubes are internally provided with voltage stabilizing tubes for forcibly limiting the amplitude of the Gate voltage, in this case, when the provided driving voltage exceeds the voltage of the voltage stabilizing tubes, larger static power consumption is caused, meanwhile, if the simple principle of using resistance voltage division reduces the Gate voltage, when the input voltage is higher, the MOS tube works well, and when the input voltage reduces, the Gate voltage is insufficient, the conduction is insufficient, so that the power consumption is increased, the wide voltage application means that in some control circuits, a logic part uses typical 5V or 3.3V digital voltage, and a power part uses 12V or even higher voltage, the two voltages are connected in a common mode, when a Gate-MOS transistor is a PMOS transistor, the triode Q1 and the triode Q2 in the reverse totem pole circuit are used for realizing isolation, meanwhile, the triode Q3 and the triode Q4 are ensured not to be conducted simultaneously, a PWM voltage reference is provided by a resistor R2 and a resistor R3, the circuit can work at a position where PWM signal waveforms are compared, the resistor R1 provides base current limitation on the triode Q3 and the triode Q4, the triode Q3 and the triode Q4 in a driving current circuit are used for providing driving current, and when the Gate-MOS transistor is conducted, only one voltage drop of the triode Q3 and the triode Q4 relative to Vh and the ground is usually about 0.3V, the Vce which is greatly lower than 0.7V, the voltage drop in a back stage circuit is a resistor R5 and a resistor R4, the value of the triode Q4 can be limited by the resistor R5 and the triode Q4, the value of the triode Q4 can be limited by the resistor Q1, the value of the triode Q4 is also limited by the resistor Q1 and the triode Q4, the value of the triode Q4 can be limited by the voltage value of the resistor Q1 and the triode Q4.
Referring to fig. 3, the reverse totem pole circuit includes an inverter, a resistor R1, a triode Q2, a resistor R2 and a resistor R3, wherein one end of the inverter is connected with PWM, the other end is connected with one end of the resistor R1, the emitter of the triode Q1 and the emitter of the triode Q2 are both connected with the other end of the resistor R1, one end of the resistor R2 is connected with a VI low-end power supply, the other end is respectively connected with a base electrode of the triode Q1 and a base electrode of the triode Q2, one end of the resistor R3 is connected with the other end of the resistor R2, and the other end is grounded;
the driving current circuit comprises a triode Q3 and a triode Q4, wherein the base electrode of the triode Q3 is connected with the collector electrode of the triode Q1, the base electrode of the triode Q4 is connected with the collector electrode of the triode Q2, the emitter electrode of the triode Q3 is connected with a Vh high-end power supply, the emitter electrode of the triode Q4 is grounded, and the collector electrode of the triode Q3 is connected with the collector electrode of the triode Q4;
the rear-stage circuit comprises a triode Q5, a resistor R4, a resistor R5 and a resistor R6, wherein the base electrode of the triode Q5 is respectively connected with one end of the resistor R5 and one end of the resistor R6, the other end of the resistor R5 and the emitting electrode of the triode Q5 are grounded, one end of the resistor R4 is connected with the collecting electrode of the triode Q5, the other end of the resistor R6 is connected with the other end of the resistor R6, and the other end of the resistor R6 is connected with a Gate-MOS tube. The circuit can work at a position where the waveform of PWM signals is steeper, in the driving current circuit, the triode Q3 and the triode Q4 are used for providing driving current, when the driving current circuit is conducted, the triode Q3 and the triode Q4 have voltage drop of only one Vce relative to Vh and ground, the voltage drop is usually only about 0.3V and is greatly lower than Vce of 0.7V, the resistor R5 and the resistor R6 in the later-stage circuit are feedback resistors and are used for sampling Gate voltage, the sampled voltage generates strong negative feedback to the bases of the triode Q1 and the triode Q2 through the triode Q5, so that the Gate voltage is limited to a limited value, the value can be regulated through the resistor R5 and the resistor R6, the resistor R4 provides Gate current limit to the MOS tube, the resistor R1 provides base current limit to the triode Q3 and the triode Q4, namely the limit to the Ice of the triode Q3 and the triode Q4, when necessary, an accelerating capacitor can be connected in parallel on the R4, the triode Q1, the triode Q4 and the triode Q5 are NPN type, and the triode Q2 and the triode Q3 are PNP type.
Referring to fig. 4 and 5, a signal level transformer is disposed between the reverse totem pole circuit and the PWM, one side of one end of the signal level transformer is connected to one end of the resistor R1, the other side is grounded, one side of the other end of the signal level transformer is connected to the PWM, the other side is grounded, PWM control is a technique of modulating the width of the pulse, that is, modulating the width of a series of pulses to equivalently obtain a required waveform, the PWM is divided into single polarity and double polarity, the single polarity PWM is that the PWM waveform changes only in the single polarity range, the double polarity PWM is that the PWM waveform has positive or negative polarity, the single polarity and double polarity are defined according to the difference of the low level, then the single polarity refers to the low level with 0V, the double polarity refers to the low level with the potential with the polarity direction opposite to the high level (that is, under the horizontal axis), when the PWM input into the circuit is bipolar PWM, a signal level transformer is connected between the PWM and the resistor R1, the signal level transformer is driven by a symmetrical bipolar driving signal, the secondary winding of the signal level transformer is used for generating power of the buffer and providing input signals for the buffer, the buffer is the same as a unipolar driving circuit and is used for buffering the output impedance of the transformer to provide large current pulse so as to charge and discharge the MOSFET connected with the output end, the circuit has extremely high efficiency, because the grid electrode of the driving FET is negative and can provide quick switching, thereby minimizing switching loss, when the signal level transformer is connected, the MOS tube driving circuit using the PMOS tube is connected with the signal level transformer in a forward direction, the MOS tube driving circuit using the NMOS tube is connected with the signal level transformer in a reverse direction, the same effect as that of the inverter can be obtained, the NMOS tube can remove the inverter, and components in the circuit are reduced.
The foregoing has shown and described the basic principles and main features of the present utility model and the advantages of the present utility model. It will be understood by those skilled in the art that the present utility model is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present utility model, and various changes and modifications may be made without departing from the spirit and scope of the utility model, which is defined in the appended claims. The scope of the utility model is defined by the appended claims and equivalents thereof.
Claims (4)
1. The MOS tube driving circuit with low cost is characterized by comprising a reverse totem pole circuit, a driving current circuit, a rear-stage circuit, PWM (pulse width modulation), a Gate-MOS tube, a VI (VI) low-end power supply and a Vh high-end power supply, wherein the driving current circuit is respectively connected with the reverse totem pole circuit, the rear-stage circuit and the Vh high-end power supply, the PWM is connected with the reverse totem pole circuit, the VI low-end power supply is connected with the reverse totem pole circuit, and the Gate-MOS tube is connected with the rear-stage circuit.
2. The low-cost MOS transistor driving circuit according to claim 1, wherein the reverse totem pole circuit comprises a resistor R1, a triode Q2, a resistor R2 and a resistor R3, wherein one end of the resistor R1 is connected with PWM, the emitter of the triode Q1 and the emitter of the triode Q2 are both connected with the other end of the resistor R1, one end of the resistor R2 is connected with a VI low-end power supply, the other end is respectively connected with a base electrode of the triode Q1 and a base electrode of the triode Q2, one end of the resistor R3 is connected with the other end of the resistor R2, and the other end is grounded;
the driving current circuit comprises a triode Q3 and a triode Q4, wherein the base electrode of the triode Q3 is connected with the collector electrode of the triode Q1, the base electrode of the triode Q4 is connected with the collector electrode of the triode Q2, the emitter electrode of the triode Q3 is connected with a Vh high-end power supply, the emitter electrode of the triode Q4 is grounded, and the collector electrode of the triode Q3 is connected with the collector electrode of the triode Q4;
the rear-stage circuit comprises a triode Q5, a resistor R4, a resistor R5 and a resistor R6, wherein the base electrode of the triode Q5 is respectively connected with one end of the resistor R5 and one end of the resistor R6, the other end of the resistor R5 and the emitting electrode of the triode Q5 are both connected to a Vh high-end power supply, one end of the resistor R4 is connected with the collecting electrode of the triode Q3, the other end of the resistor R4 is connected with the other end of the resistor R6, the other end of the resistor R6 is connected with the other end of the resistor R2, and the other end of the resistor R6 is connected with a Gate-MOS tube.
3. The low-cost MOS transistor driving circuit according to claim 1, wherein the reverse totem pole circuit comprises an inverter, a resistor R1, a triode Q2, a resistor R2 and a resistor R3, wherein one end of the inverter is connected with PWM, the other end of the inverter is connected with one end of the resistor R1, the emitter of the triode Q1 and the emitter of the triode Q2 are both connected with the other end of the resistor R1, one end of the resistor R2 is connected with a VI low-end power supply, the other end of the resistor R2 is respectively connected with a base electrode of the triode Q1 and a base electrode of the triode Q2, one end of the resistor R3 is connected with the other end of the resistor R2, and the other end of the resistor R3 is grounded;
the driving current circuit comprises a triode Q3 and a triode Q4, wherein the base electrode of the triode Q3 is connected with the collector electrode of the triode Q1, the base electrode of the triode Q4 is connected with the collector electrode of the triode Q2, the emitter electrode of the triode Q3 is connected with a Vh high-end power supply, the emitter electrode of the triode Q4 is grounded, and the collector electrode of the triode Q3 is connected with the collector electrode of the triode Q4;
the rear-stage circuit comprises a triode Q5, a resistor R4, a resistor R5 and a resistor R6, wherein the base electrode of the triode Q5 is respectively connected with one end of the resistor R5 and one end of the resistor R6, the other end of the resistor R5 and the emitting electrode of the triode Q5 are both grounded, one end of the resistor R4 is connected with the collecting electrode of the triode Q5, the other end of the resistor R4 is connected with the other end of the resistor R6, and the other end of the resistor R6 is connected with a Gate-MOS tube.
4. The low-cost MOS transistor driving circuit of claim 2, wherein a signal level transformer is disposed between the reverse totem pole circuit and the PWM, one side of one end of the signal level transformer is connected to one end of the resistor R1, the other side is grounded, one side of the other end of the signal level transformer is connected to the PWM, and the other side is grounded.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202320218774.6U CN219554947U (en) | 2023-02-15 | 2023-02-15 | Low-cost MOS tube driving circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202320218774.6U CN219554947U (en) | 2023-02-15 | 2023-02-15 | Low-cost MOS tube driving circuit |
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| CN219554947U true CN219554947U (en) | 2023-08-18 |
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| CN202320218774.6U Active CN219554947U (en) | 2023-02-15 | 2023-02-15 | Low-cost MOS tube driving circuit |
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