CN219227609U - JESD204B data transmission system based on optical fiber medium - Google Patents

Abstract

The utility model discloses a JESD204B data transmission system based on an optical fiber medium, which comprises a data acquisition module and a data processing module, wherein the data acquisition module and the data processing module are interconnected through an optical fiber and transmit JESD204B protocol signals through a JESD204B protocol interface, and the JESD204B protocol signals comprise ADC sampling data, DAC baseband data, a synchronous signal Sync and a synchronous reference signal Sysref; the data acquisition module comprises: the device comprises an ADC circuit, a DAC circuit, a first clock distribution circuit, an FPGA1 and a first optical module; the data processing module comprises: the second clock distribution circuit, the FPGA2 and the second optical module. The problems of high cable transmission loss, weak anti-interference capability and the like are effectively solved, the system interconnection complexity is reduced, the cable weight is reduced, the limitation of each module of the system on layout is relieved, and the volume of each functional module is reduced.

Description

JESD204B data transmission system based on optical fiber medium

Technical Field

The utility model relates to the field of high-speed data transmission, in particular to a JESD204B data transmission system based on an optical fiber medium.

Background

The JESD204B interface is now the mainstream interface of the high-speed ADC/DAC conversion chip, and is an interface based on the high-speed serial data transmission protocol, and the high-speed data transmission is basically based on the high-speed serial data transmission protocol at present. Compared with the traditional parallel LVDS bus interface, the high-speed serial data transmission has two major advantages: the transmission bandwidth is higher; the bus interface is simpler. The high-speed serial transmission interface also has some own disadvantages, such as high power consumption, high resource consumption, and the like.

In JESD204B board-level transmission applications, high-speed digital signals will be highly lossy when the boards are interconnected by high-speed cables. Sync is a synchronization signal in JESD204B protocol, and is generated by the data receiving end and transmitted to the data transmitting end, and the data transmitting end perceives whether the data receiving end has completed synchronization or needs re-synchronization according to the level state of the Sync signal. In the JESD204B protocol, sysref is a system synchronization reference signal, and the rising edge of Sysref triggers synchronous counting of local multi-frame counters of a data sending end and a data receiving end, and the synchronous counting of the local multi-frame counters is guaranteed to obtain deterministic delay of data transmission. In the conventional application, the Sync and Sysref analog signals are transmitted through a printed wire or a cable, and the cable has large transmission loss and weak anti-interference capability, which limits the application of the JESD204B in a long-distance transmission scenario.

Disclosure of Invention

The utility model provides a JESD204B data transmission system based on an optical fiber medium, which comprises a data acquisition module and a data processing module, wherein the data acquisition module and the data processing module are interconnected through an optical fiber and transmit JESD204B protocol signals through a JESD204B protocol interface, and the JESD204B protocol signals comprise ADC sampling data, DAC baseband data, a synchronous signal Sync and a synchronous reference signal Sysref; the data acquisition module comprises: the device comprises an ADC circuit, a DAC circuit, a first clock distribution circuit, an FPGA1 and a first optical module; the data processing module comprises: the FPGA1 comprises an Aurora core, and the FPGA2 comprises an Aurora core and a JESD204B core; the system comprises an ADC sampling link and a DAC baseband data link;

ADC sampling link: completing conversion from analog signals to digital signals, converting the sampled digital signals into optical signals through a first optical module, and transmitting the optical signals to a data processing module; the Aurora core clock of the FPGA1 samples the Sysref into a digital signal and then sends the digital signal to the data processing module through the Aurora core of the FPGA1, and the data processing module sends the received digital signal of the Sysref to the Sysref input port of the JESD204B core of the FPGA 2; the Sync signal output by the JESD204B core of the FPGA2 is sampled by the Aurora core clock of the FPGA2 and then sent to a data acquisition module, and the Aurora core of the data acquisition module FPGA1 receives the Sync signal and distributes the Sync signal to each ADC chip;

DAC baseband data link: the data processing module sends the digital baseband signal to the data acquisition module through JESD204B core of the FPGA2, and the data acquisition module converts the digital baseband signal into an analog signal and outputs the analog signal; the Aurora core clock of the FPGA1 samples the Sysref into a digital signal and then sends the digital signal to the data processing module through the Aurora core of the FPGA1, and the data processing module sends the received digital signal of the Sysref to the Sysref input port of the JESD204B core of the FPGA 2; the DAC chip outputs a Sync signal, the Sync signal is sampled by an Aurora core clock of the data acquisition module FPGA1 and then is sent to the data processing module, and the data processing module sends a Sync digital signal received by the Aurora core of the FPGA2 to a Sync input port of a JESD204B core of the FPGA 2.

Further, the FPGA1 is a device having a high-speed transceiver function and relatively small logic resources.

Further, the FPGA2 is a device having a high-speed transceiver function and relatively more logic resources.

Further, the ADC circuit is a chip with a JESD204B interface.

Further, the DAC circuit is a chip with a JESD204B interface.

Further, the first clock distribution circuit is a device with a multi-channel clock distribution function.

Further, the second clock distribution circuit is a device with a multipath clock distribution function.

Further, the Sysref delay of the synchronous reference signal is adjusted to enable a plurality of link multi-frame arrival time points to be in the same local multi-frame counter period.

Further, the Aurora core interface data clock Userclk performs register sampling on the Sync signal, and the sampled Sync signal is placed in the lowest bit of the TX data bus field of Aurora and sent to the Aurora data receiving port of the opposite end.

Further, the Aurora interface data clock Userclk carries out register sampling on the Sysref signal, and the sampled Sysref signal is placed in the next lower bit of the TX data bus field of Aurora and is sent to an Aurora data receiving port at the opposite end.

The JESD204B data transmission system based on the optical fiber medium effectively solves the problems of high cable transmission loss, weak anti-interference capability and the like, reduces the system interconnection complexity, reduces the cable weight, removes the limitation of each module of the system on layout, and reduces the volume of each functional module.

Drawings

FIG. 1 is a block diagram of a system architecture of a JESD204B data transmission system based on optical fiber media provided by the present utility model;

fig. 2 is a schematic diagram of Sysref and Sync signal transmission of a JESD204B data transmission system based on an optical fiber medium according to the present utility model.

Detailed Description

The following detailed description of embodiments of the utility model, taken in conjunction with the accompanying drawings, illustrates only some, but not all embodiments, and for the sake of clarity, illustration and description not related to the utility model is omitted in the drawings and description.

As shown in fig. 1, the present utility model provides a JESD204B data transmission system based on an optical fiber medium, which includes a data acquisition module and a data processing module, wherein the data acquisition module and the data processing module are interconnected through an optical fiber and transmit JESD204B protocol signals through a JESD204B protocol interface, and the JESD204B protocol signals include ADC sampling data, DAC baseband data, a synchronous signal Sync and a synchronous reference signal syref; the data acquisition module comprises: the device comprises an ADC circuit, a DAC circuit, a first clock distribution circuit, an FPGA1 and a first optical module; the data processing module comprises: the FPGA1 comprises an Aurora core, and the FPGA2 comprises the Aurora core and a JESD204B core.

The system includes an ADC sampling link and a DAC baseband data link.

Wherein, ADC sampling link: completing conversion from analog signals to digital signals, converting the sampled digital signals into optical signals through a first optical module, and transmitting the optical signals to a data processing module; the Aurora core clock of the FPGA1 samples the Sysref into a digital signal and then sends the digital signal to the data processing module through the Aurora core of the FPGA1, and the data processing module sends the received digital signal of the Sysref to the Sysref input port of the JESD204B core of the FPGA 2; the Sync signal output by the JESD204B core of the FPGA2 is sampled by the Aurora core clock of the FPGA2 and then sent to the data acquisition module, and the Aurora core of the data acquisition module FPGA1 receives the Sync signal and distributes the Sync signal to each ADC chip.

DAC baseband data link: the data processing module sends the digital baseband signal to the data acquisition module through JESD204B core of the FPGA2, and the data acquisition module converts the digital baseband signal into an analog signal and outputs the analog signal; the Aurora core clock of the FPGA1 samples the Sysref into a digital signal and then sends the digital signal to the data processing module through the Aurora core of the FPGA1, and the data processing module sends the received digital signal of the Sysref to the Sysref input port of the JESD204B core of the FPGA 2; the DAC chip outputs a Sync signal, the Sync signal is sampled by an Aurora core clock of the data acquisition module FPGA1 and then is sent to the data processing module, and the data processing module sends a Sync digital signal received by the Aurora core of the FPGA2 to a Sync input port of a JESD204B core of the FPGA 2.

The ADC and the DAC adopt chips with JESD204B interface functions, such as AD4680, AD9154 and the like; the first clock distribution chip adopts devices with a multi-channel clock distribution function, such as HMC7043, HMC7044, LMX2594 and the like; the FPGA1 chip adopts a device with a high-speed transceiver function and relatively small logic resources, such as XC7A35T-2CSG325I, XC A50T-2CSG325I of Xilinx and the like. The second clock distribution chip adopts devices with a multipath clock distribution function, such as HMC7043, HMC7044, LMX2594 and the like; the FPGA2 chip adopts a device with a high-speed transceiver function and relatively more logic resources, such as XC7VX690T-2FFG1927I, XC7VX485T-2FFG1927I of Xilinx and the like.

As shown in FIG. 2, the JESD204B high-speed data transmission mode based on the optical fiber medium is mainly characterized in that Sysref and Sync are digitized and then transmitted through the optical fiber, and the mode has the advantage of simplifying the interconnection relation between modules. Register sampling is carried out on Sync signals by an Aurora interface data clock Userclk, and the sampled Sync signals are placed in the lowest bit of a TX data bus field of Aurora and sent to an Aurora data receiving port of an opposite end; the Aurora interface data clock Userclk carries out register sampling on the Sysref signal, and the sampled Sysref signal is placed in the next lower bit of the TX data bus field of Aurora and is sent to an Aurora data receiving port of the opposite end. In the DAC link, sync signals are sent to a data processing module by a data acquisition module; in the ADC link, a Sync signal is sent to a data acquisition module by a data processing module; the Sysref signal is sent to the data processing module by the data acquisition module.

In a JESD204B high-speed data transmission mode based on a cable, all signals in the JESD204B protocol are transmitted by the cable, the transmission path passes through a multi-stage connector, the loss of the signals by the cable and the connector is larger, and the higher the transmission rate is, the larger the loss is, which is a disadvantage of the cable in board-level transmission; in a JESD204B high-speed data transmission system based on an optical fiber medium, all signals in a JESD204B protocol, including a high-speed digital sampling signal, sysref and Sync signals, are transmitted by an optical fiber, all transmission cables are omitted, and one Aurora core is required to be independently exemplified to transmit the sampled digital signals of Sysref and Sync. The data acquisition module and the data processing module can be arranged at a far distance due to the small loss of the optical fiber transmission signal.

In the system debugging process, attention is paid to the processing of Sysref signals by the data acquisition module and the data processing module, so that the phenomenon of crossing multiple frames is avoided. When the multi-frame crossing condition occurs, the multi-link data arrival condition of the receiving end is observed, and Sysref delay is adjusted to enable the multi-link multi-frame arrival time points to be in the same local multi-frame counter (LMFC) period, so that the multi-frame crossing problem can be solved. The multi-frame crossing problem is that a plurality of link multi-frames reach the situation that the time point crosses the local multi-frame counter boundary of the receiving end, and the data receiving Buffer overflows to cause data disorder or data loss.

While the foregoing is directed to embodiments of the present utility model, other and further details of the utility model may be had by the present utility model, it should be understood that the foregoing description is merely illustrative of the present utility model and that no limitations are intended to the scope of the utility model, except insofar as modifications, equivalents, improvements or modifications are within the spirit and principles of the utility model.

Claims (10)

1. The JESD204B data transmission system based on the optical fiber medium is characterized by comprising a data acquisition module and a data processing module, wherein the data acquisition module and the data processing module are interconnected through optical fibers and transmit JESD204B protocol signals through a JESD204B protocol interface, and the JESD204B protocol signals comprise ADC sampling data, DAC baseband data, a synchronous signal Sync and a synchronous reference signal Sysref; the data acquisition module comprises: the device comprises an ADC circuit, a DAC circuit, a first clock distribution circuit, an FPGA1 and a first optical module; the data processing module comprises: the FPGA1 comprises an Aurora core, and the FPGA2 comprises an Aurora core and a JESD204B core; the system comprises an ADC sampling link and a DAC baseband data link;

ADC sampling link: completing conversion from analog signals to digital signals, converting the sampled digital signals into optical signals through a first optical module, and transmitting the optical signals to a data processing module; the Aurora core clock of the FPGA1 samples the Sysref into a digital signal and then sends the digital signal to the data processing module through the Aurora core of the FPGA1, and the data processing module sends the received digital signal of the Sysref to the Sysref input port of the JESD204B core of the FPGA 2; the Sync signal output by the JESD204B core of the FPGA2 is sampled by the Aurora core clock of the FPGA2 and then sent to a data acquisition module, and the Aurora core of the data acquisition module FPGA1 receives the Sync signal and distributes the Sync signal to each ADC chip;

DAC baseband data link: the data processing module sends the digital baseband signal to the data acquisition module through JESD204B core of the FPGA2, and the data acquisition module converts the digital baseband signal into an analog signal and outputs the analog signal; the Aurora core clock of the FPGA1 samples the Sysref into a digital signal and then sends the digital signal to the data processing module through the Aurora core of the FPGA1, and the data processing module sends the received digital signal of the Sysref to the Sysref input port of the JESD204B core of the FPGA 2; the DAC chip outputs a Sync signal, the Sync signal is sampled by an Aurora core clock of the data acquisition module FPGA1 and then is sent to the data processing module, and the data processing module sends a Sync digital signal received by the Aurora core of the FPGA2 to a Sync input port of a JESD204B core of the FPGA 2.

2. A JESD204B data transmission system based on optical fiber medium as claimed in claim 1, wherein said FPGA1 is a device having a high-speed transceiver function and relatively small logic resources.

3. A JESD204B data transmission system based on fiber media as claimed in claim 1, wherein said FPGA2 is a device with high-speed transceiver function and relatively more logic resources.

4. A JESD204B data transmission system based on fiber media as claimed in claim 1, wherein the ADC circuit is a chip with a JESD204B interface.

5. A JESD204B data transmission system based on fiber media as claimed in claim 1, wherein the DAC circuit is a chip with a JESD204B interface.

6. A JESD204B data transmission system based on optical fiber medium as claimed in claim 1, wherein said first clock distribution circuit is a device having a multi-channel clock distribution function.

7. A JESD204B data transmission system based on optical fiber medium as claimed in claim 1, wherein said second clock distribution circuit is a device having a multi-channel clock distribution function.

8. A JESD204B data transmission system based on optical fiber media as claimed in claim 1, wherein the synchronization reference signal Sysref delay is adjusted so that the multiple link multi-frame arrival time points are within the same local multi-frame counter period.

9. The JESD204B data transmission system based on optical fiber media of claim 1, wherein the Aurora core interface data clock Userclk performs register sampling on the synchronization signal Sync, and the sampled synchronization signal Sync is placed in the lowest bit of the TX data bus field of Aurora and sent to the Aurora data receiving port at the opposite end.

10. The JESD204B data transmission system based on optical fiber media of claim 1, wherein the Aurora interface data clock Userclk performs register sampling on the synchronous reference signal syref, and the sampled synchronous reference signal syref is placed in the next lower order of the TX data bus field of Aurora and sent to the Aurora data receiving port at the opposite end.

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