CN218939682U

CN218939682U - Power MOSFET and MOSFET driver combined IC package

Info

Publication number: CN218939682U
Application number: CN202223342294.5U
Authority: CN
Inventors: 张海峰
Original assignee: Shanghai Haixin Electronic Technology Co ltd
Current assignee: Shanghai Haixin Electronic Technology Co ltd
Priority date: 2022-12-14
Filing date: 2022-12-14
Publication date: 2023-04-28
Anticipated expiration: 2032-12-14

Abstract

The utility model relates to the technical field of semiconductors, and particularly discloses an Integrated Circuit (IC) package combining a Power MOSFET and a MOSFET Driver, which comprises a Multi-die IC, wherein a Driver IC crystal grain and a Power MOSFET crystal grain are packaged on the Multi-die IC; the utility model combines the crystal grains with two functions in the package, so that the space of one IC can be used for the functions of the two ICs, thereby saving the area of a system board.

Description

Power MOSFET and MOSFET driver combined IC package

Technical Field

The utility model relates to the technical field of semiconductors, in particular to an Integrated Circuit (IC) package combining a Power MOSFET and a MOSFET driver.

Background

In a general system board, the power mosfet and driver ICs are two different ICs, as shown in fig. 2, corresponding dies are laid on the corresponding ICs, which increases the area of the system board, and further corresponding elements are required to be laid, so that the whole package structure is increased. In response to the above problems, a Power MOSFET and MOSFET driver combined IC package is proposed.

Disclosure of Invention

The present utility model is directed to an IC package combining a Power MOSFET and a MOSFET driver, so as to solve the above-mentioned problems in the related art.

In order to achieve the above purpose, the present utility model provides the following technical solutions:

a Power MOSFET and MOSFET Driver combined IC package comprising a Multi-die IC on which Driver IC die and Power MOSFET die are packaged.

In one alternative: the Multi-die IC is connected with the system board at the side far away from the Driver IC die.

In one alternative: and leads connected with the Multi-diodes IC are arranged on the Driver IC crystal grain and the Power MOSFET crystal grain.

In one alternative: a silicon intermediate layer is arranged between the Driver IC crystal grain and the Multi-die IC.

In one alternative: a silicon interposer is disposed between the Power MOSFET die and the Multi-die IC.

In one alternative: the Driver IC die and the Power MOSFET die are disposed on a side of the Multi-die IC remote from the system board, and the Driver IC die and the Power MOSFET die are horizontally aligned.

Compared with the prior art, the utility model has the beneficial effects that:

the utility model combines the crystal grains with two functions in the package, so that the space of one IC can be used for the functions of the two ICs, thereby saving the area of a system board.

Drawings

Fig. 1 is a schematic structural view of the present utility model.

Fig. 2 is a schematic structural diagram of a conventional package.

In the figure: 100. a system board; 200. multi-notes IC; 300. driver IC die; 400. power MOSFET die.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

Referring to fig. 1, in this embodiment, a Power MOSFET and MOSFET Driver combined IC package includes a Multi-die IC200, where a Driver IC die 300 and a Power MOSFET die 400 are packaged on the Multi-die IC 200; the side of the Multi-dies IC200 far from the Driver IC die 300 is connected with the system board 100;

multi-notes IC: a multi-die IC;

the two kinds of functional crystal grains are combined in the package, so that the space of one IC can be used for the functions of two ICs, and the area of a system board is further saved.

Leads connected to the Multi-die IC200 are provided on both the Driver IC die 300 and the Power MOSFET die 400.

A silicon intermediate layer is arranged between the Driver IC die 300 and the Multi-die IC 200; a silicon interposer is arranged between the Power MOSFET die 400 and the Multi-die IC 200;

the interposer realizes interconnection of upper and lower layers Through Silicon Vias (TSVs), is a silicon substrate made of silicon and organic materials, is a pipeline for transmitting electric signals by the multi-chip module in advanced packaging, can realize interconnection between chips, can also realize interconnection with a packaging substrate, and serves as a bridge between a plurality of bare chips and a circuit board.

The Driver IC die 300 and the Power MOSFET die 400 are disposed on a side of the Multi-die IC200 remote from the system board 100, and the Driver IC die 300 and the Power MOSFET die 400 are horizontally aligned.

The working principle of the utility model is as follows: combining the two functional dies, namely Driver IC die 300 and Power MOSFET die 400, in a package allows space for one Multi-die IC200 to serve the functions of both ICs, thereby saving area on the system board 100.

The preferred embodiments of the utility model disclosed above are intended only to assist in the explanation of the utility model. The preferred embodiments are not exhaustive or to limit the utility model to the precise form disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the utility model and the practical application, to thereby enable others skilled in the art to best understand and utilize the utility model. The utility model is limited only by the claims and the full scope and equivalents thereof.

Claims

1. A Power MOSFET and MOSFET driver combined IC package comprising a Multi-die IC (200), characterized by: the Multi-die IC (200) is packaged with Driver IC die (300) and Power MOSFET die (400).

2. The Power MOSFET and MOSFET driver combined IC package of claim 1, wherein: the Multi-dies IC (200) is connected to the system board (100) on a side remote from the Driver IC die (300).

3. The Power MOSFET and MOSFET driver combined IC package of claim 1, wherein: leads connected with the Multi-die IC (200) are arranged on the Driver IC die (300) and the Power MOSFET die (400).

4. The Power MOSFET and MOSFET driver combined IC package of claim 1, wherein: a silicon interposer is disposed between the Driver IC die (300) and the Multi-die IC (200).

5. The Power MOSFET and MOSFET driver combined IC package of claim 1, wherein: a silicon interposer is disposed between the Power MOSFET die (400) and the Multi-Dies IC (200).

6. The Power MOSFET and MOSFET driver combined IC package of claim 2, wherein: the Driver IC die (300) and the Power MOSFET die (400) are disposed on a side of the Multi-Dies IC (200) remote from the system board (100), and the Driver IC die (300) and the Power MOSFET die (400) are horizontally aligned.