CN218039195U - Semiconductor packaging structure - Google Patents

Abstract

The semiconductor package structure provided by the application utilizes the bridging element as a signal transmission path between the first upper electronic element and the second upper electronic element. The choice of bridging element is based primarily on considerations of both structural thickness and signal transmission loss. From the aspect of structural thickness and size, the bridging element belongs to a wafer (wafer) level product, the manufacturing precision is high, the yield is high, the impedance is easy to control in a certain range, and therefore the signal transmission loss can be reduced. The bridging element is small in size from the aspect of signal transmission loss, and the effect of reducing the overall thickness can be achieved by thinning the bridging element. Therefore, the bridging element is used as a signal transmission path between the first upper electronic element and the second upper electronic element, and the effects of reducing signal transmission loss and reducing the whole thickness can be achieved at the same time.

Description

Semiconductor packaging structure

Technical Field

The application relates to the technical field of semiconductors, in particular to a semiconductor packaging structure.

Background

With the increasing demand for miniaturization, multi-functionalization and high performance of electronic product systems, attention is paid to a Double-sided package Module (DSM), which is a high-density package structure capable of integrating a plurality of electronic components.

In one case, a plurality of chip-lets (chip-lets) and memory chips (memory) into which an Application Specific Integrated Circuit (ASIC) chip is divided are respectively disposed on both sides of a substrate. However, as the memory capacity requirement is getting larger and larger, the transmission distance between the adjacent chips corresponding to the adjacent memory chips is lengthened, resulting in serious signal transmission loss between the chips. For example, the substrate may be used to connect adjacent chips, and although the cross-sectional area of the circuit is large, the signal transmission loss can be reduced, but the thickness is too large, and the circuit impedance is unstable due to insufficient circuit precision, which affects the performance. For example, a redistribution Layer (RDL) may be used to connect adjacent dies, but the thickness is small, but the cross-sectional area of the line is small, the impedance is large, the yield is low, and the signal transmission loss between the adjacently arranged dies is serious under long-distance transmission.

SUMMERY OF THE UTILITY MODEL

The application provides a semiconductor package structure, including:

a first upper electronic element and a first lower electronic element which are arranged in an overlapping mode, and projections of the first upper electronic element and the first lower electronic element on the same horizontal plane are at least partially overlapped;

a second upper electronic element and a second lower electronic element, which are arranged in an overlapping manner, wherein projections of the second upper electronic element and the second lower electronic element on the same horizontal plane at least partially overlap, and a distance between the first upper electronic element and the second upper electronic element is larger than a distance between the first lower electronic element and the second lower electronic element;

a bridge element connecting the first upper electronic element and the second upper electronic element.

In some optional embodiments, the semiconductor package structure further comprises:

and an intermediate circuit structure separating the first upper electronic element and the first lower electronic element, and separating the second upper electronic element and the second lower electronic element.

In some alternative embodiments, the intermediate circuit structure is disposed between the first upper electronic element and the first lower electronic element, and between the second upper electronic element and the second lower electronic element.

In some optional embodiments, the first upper electronic component and the first lower electronic component are symmetrically disposed on two sides of the middle circuit structure, and the second upper electronic component and the second lower electronic component are symmetrically disposed on two sides of the middle circuit structure.

In some alternative embodiments, the intermediate circuit structure connects the first upper electronic element and the first lower electronic element, and the intermediate circuit structure connects the second upper electronic element and the second lower electronic element.

In some optional embodiments, the intermediate line structure comprises:

a dielectric layer, which covers the bridging element;

an interconnect structure extending through the dielectric layer;

and the lower circuit layer is arranged below the dielectric layer and connected with the interconnection structure.

In some optional embodiments, the intermediate circuit structure further comprises:

and the upper circuit layer is arranged above the dielectric layer, and the interconnection structure is connected with the upper circuit layer and the lower circuit layer.

In some optional embodiments, the semiconductor package structure further comprises:

and the connecting piece is arranged on the lower circuit layer and is used for providing an external connecting path.

In some alternative embodiments, the pad pitch of the bridge element, the pad pitch of the first upper electronic element, and the pad pitch of the second upper electronic element are the same.

In some optional embodiments, the density of the lines in the bridge chip is greater than the density of the upper line layer.

In some optional embodiments, a dimension of the first lower electronic element in the X-axis direction is greater than a dimension of the first upper electronic element in the X-axis direction, and a dimension of the second lower electronic element in the X-axis direction is greater than a dimension of the second upper electronic element in the X-axis direction.

In some optional embodiments, a dimension of the first lower electronic element in the Y-axis direction is greater than a dimension of the first upper electronic element in the Y-axis direction, and a dimension of the second lower electronic element in the Y-axis direction is greater than a dimension of the second upper electronic element in the Y-axis direction.

In some optional embodiments, the first upper electronic element is located within a projection range of the first lower electronic element in a vertical direction.

In some optional embodiments, the second upper electronic element is located within a projection range of the second lower electronic element in a vertical direction.

In some optional embodiments, the semiconductor package structure further comprises:

a stiffener disposed between the first upper electronic component and the second upper electronic component.

In some alternative embodiments, the stiffener is located within a projection of the bridging element in a vertical direction.

In some optional embodiments, a portion of the stiffener is located within a projection range of the first lower electronic element or the second lower electronic element in a vertical direction.

In some optional embodiments, the semiconductor package structure further comprises:

and the coating layer is arranged among the first upper electronic element, the second upper electronic element and the reinforcing piece.

The semiconductor package structure provided by the application utilizes the bridging element as a signal transmission path between the first upper electronic element and the second upper electronic element. The choice of bridging element is based primarily on considerations of both structural thickness and signal transmission loss. From the aspect of structural thickness and size, the bridging element belongs to a wafer (wafer) level product, the manufacturing precision is high, the yield is high, and the impedance is easy to control in a certain range, so that the signal transmission loss can be reduced. In terms of signal transmission loss, the size of the bridging element is small, and the effect of reducing the overall thickness can be achieved by thinning the bridging element. Therefore, the bridging element is used as a signal transmission path between the first upper electronic element and the second upper electronic element, and the effects of reducing signal transmission loss and reducing the whole thickness can be achieved at the same time.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:

fig. 1 to 8 are first to eighth schematic structural views of a semiconductor package according to the present application;

fig. 9 to 14 are schematic structural diagrams in the manufacturing process of the semiconductor package structure according to the embodiment of the present application.

Description of the symbols:

11-a first upper electronic element, 12-a first lower electronic element, 21-a second upper electronic element, 22-a second lower electronic element, 3-a bridge element, 31-a first bridge chip, 32-a second bridge chip, 4-an intermediate circuit structure, 41-an upper circuit layer, 42-a dielectric layer, 43-a lower circuit layer, 44-an interconnect structure, 5-a connector, 6-a stiffener, 7-a cladding layer, 8-a signal transmission component, 91-a third upper electronic element, 92-a third lower electronic element, 10-a fourth electronic element, 13-a fifth electronic element, 14-a carrier, 15-a protective layer, L1-a first distance, L2-a second distance, S1-a first side, S2-a second side.

Detailed Description

The following description of the embodiments of the present application will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects that the present application solves and provides by the contents of the present specification. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and are not limiting of the invention. In addition, for convenience of description, only the portions related to the related utility model are shown in the drawings.

It should be noted that the structures, proportions, sizes, and other elements shown in the drawings are only used for understanding and reading the contents of the specification, and are not used for limiting the conditions under which the present application can be implemented, so they do not have the technical significance, and any structural modifications, changes in proportion, or adjustments of sizes, which do not affect the efficacy and achievement of the purposes of the present application, shall still fall within the scope of the technical content disclosed in the present application. In addition, the terms "above", "first", "second" and "a" as used herein are for the sake of clarity only, and are not intended to limit the scope of the present application, and changes or modifications of the relative relationship may be made without substantial technical changes.

It should be further noted that, in the embodiments of the present application, the corresponding longitudinal section may be a front view direction section, the transverse section may be a right view direction section, and the horizontal section may be a top view direction section.

It should be readily understood that the meaning of "in.. On," "over,", and "above" in this application should be interpreted in the broadest sense such that "in.. On" not only means "directly on something," but also means "on something" including an intermediate member or layer between the two.

Furthermore, spatially relative terms, such as "under", "below", "lower", "above", "upper", and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used in this application interpreted accordingly.

In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Fig. 1 is a first structural schematic diagram of a semiconductor package structure according to the present application. As shown in fig. 1, the semiconductor package structure includes a first upper electronic element 11, a first lower electronic element 12, a second upper electronic element 21, a second lower electronic element 22, and a bridge element 3. The first upper electronic element 11 and the first lower electronic element 12 are disposed to overlap each other. The projections of the first upper electronic element 11 and the first lower electronic element 12 in the same horizontal plane at least partly overlap. The second upper electronic component 21 and the second lower electronic component 22 are arranged to overlap. The projections of the second upper electronic element 21 and the second lower electronic element 22 in the same horizontal plane at least partly overlap. A first distance L1 between the first upper electronic element 11 and the second upper electronic element 21 is greater than a second distance L2 between the first lower electronic element 12 and the second lower electronic element 22. The bridge element 3 connects the first upper electronic element 11 and the second upper electronic element 21.

In the present embodiment, the first upper electronic element 11, the first lower electronic element 12, the second upper electronic element 21, and the second lower electronic element 22 may be an active element and a passive element. The active elements may be, for example, various chips (application specific integrated circuit chips, high bandwidth memory chips, power management chips, logic function chips, memory chips, communication chips, microprocessor chips, graphics chips, photonic chips). The passive elements may be, for example, capacitors, resistors, inductors, and the like. In one scenario, the first upper electronic element 11 and the second upper electronic element 21 may be application specific integrated circuit chips, and the first lower electronic element 12 and the second lower electronic element 22 may be memory chips. In yet another scenario, the first upper electronic element 11 and the second upper electronic element 21 may be application specific integrated circuit chips and the first lower electronic element 12 and the second lower electronic element 22 may be power management chips.

In this embodiment, the Bridge element 3 may be a Bridge chip (Bridge die). The L/S (line width/line pitch) of the lines in the bridging element 3 may be 10 μm/10 μm or more. The wires in the bridging element 3 may be made of a metal material such as copper, and the thickness of the wires may be 10 μm or more.

From the perspective of signal transmission loss, the bridge component 3 belongs to a wafer (wafer) level product, and has high manufacturing accuracy, high yield, and easy control of impedance within a certain range, thereby reducing signal transmission loss. From the structural thickness point of view, the dimensions of the bridging element 3 are small and an overall thickness reduction can be achieved by thinning the bridging element 3. Based on the above two angles, the effect of reducing signal transmission loss and reducing the overall thickness can be achieved at the same time by using the bridge element 3 as a signal transmission path between the first upper electronic element 11 and the second upper electronic element 21.

In one embodiment, the size of the first lower electronic element 12 in the X-axis direction may be larger than the size of the first upper electronic element 11 in the X-axis direction. The size of the second lower electronic element 22 in the X-axis direction may be larger than the size of the second upper electronic element 21 in the X-axis direction. The size of the first lower electronic element 12 in the Y-axis direction may be larger than the size of the first upper electronic element 11 in the Y-axis direction. The size of the second lower electronic element 22 in the Y-axis direction may be larger than the size of the second upper electronic element 21 in the Y-axis direction. The first upper electronic element 11 may be located within a projection range of the first lower electronic element 12 in the vertical direction. The second upper electronic component 21 may be located within a projection range of the second lower electronic component 22 in the vertical direction.

In one embodiment, the semiconductor package structure may further include an intermediate wiring structure 4. The intermediate wiring structure 4 may separate the first upper electronic element 11 and the first lower electronic element 12. The intermediate circuit structure 4 may separate the second upper electronic component 21 and the second lower electronic component 22. Specifically, the first upper electronic element 11 and the second upper electronic element 21 may be disposed on the first side S1 of the middle circuit structure 4, and the first lower electronic element 12 and the second lower electronic element 22 may be disposed on the second side S2 of the middle circuit structure 4. The intermediate circuit structure 4 may connect the first upper electronic element 11 and the first lower electronic element 12. The intermediate wiring structure 4 may connect the second upper electronic component 21 and the second lower electronic component 22.

In one embodiment, intermediate line structure 4 may include a dielectric layer 42, an interconnect structure 44, a lower line layer 43, and an upper line layer 41. Wherein the dielectric layer 42 may cover the bridging element 3. The lower wiring layer 43 may be disposed below the dielectric layer 42. The upper wiring layer 41 may be disposed above the dielectric layer 42. Interconnect structure 44 may extend through dielectric layer 42. Interconnect structure 44 may connect upper line layer 41 and lower line layer 43. The interconnect structure 44 may serve as a conductive path between the first upper electronic element 11 and the first lower electronic element 12. The interconnect structure 44 may serve as a conductive path between the second upper electronic element 21 and the second lower electronic element 22. The interconnect structure 44 may be, for example, a conductive pillar.

In one embodiment, the number of layers of the upper line layer 41 or the lower line layer 43 may be smaller than the number of line layers in the bridging element 3. For example, upper line layer 41 and lower line layer 43 may include 1-2 redistribution layers. The lines in the bridging element 3 may comprise at least 6 rewiring layers. The number of layers of the rewiring layer can be reduced by the bridge member 3.

In one embodiment, the line density in the bridging element 3 may be greater than the line density of the upper line layer 41 to facilitate high speed transmission of signals.

In one embodiment, the semiconductor package structure may further include an encapsulation layer 7. The clad layer 7 may clad the first upper electronic element 11 and the second upper electronic element 21.

In one embodiment, the semiconductor package structure may further include a connector 5 disposed on the lower wiring layer 43. The connecting piece 5 can be used for external connection. The connectors 5 may be, for example, high speed signal connectors (high speed connectors), solder balls, ball Grid Array (BGA) balls, controlled collapse chip connection (C4) bumps, or micro-bumps.

In one embodiment, the semiconductor package structure may further include a signal transmission member 8 disposed on the upper wiring layer 41. The signal transmission component 8 may be a physical layer (PHY) chip having a serializer/deserializer (SerDes) for transmitting signals, such as data signals, power signals, and ground signals.

In one embodiment, the upper circuit layer 41 can allow the routing of the signal transmission components 8 to the outside to amplify the pad size/pad pitch effect. After the pad size/pad pitch is enlarged by the upper wiring layer 41, it goes vertically down through the interconnect structure 44 and connects to the connector 5 for external connection.

In one embodiment, the first side S1 of the intermediate line structure 4 may also be provided with a third upper electronic element 91. The third upper electronic element 91 is spaced apart from the first upper electronic element 11 and the second upper electronic element 21. The distance between the third upper electronic element 91 and the second upper electronic element 21 may be the same as the distance between the second upper electronic element 21 and the first upper electronic element 11. The second side S2 of the intermediate circuit structure 4 may also be provided with a third lower electronic component 92. The third upper electronic element 91 is spaced apart from the first lower electronic element 12 and the second lower electronic element 22. The distance between the third lower electronic element 92 and the second lower electronic element 22 may be the same as the distance between the second lower electronic element 22 and the first lower electronic element 12.

Fig. 2 is a second structural schematic diagram of a semiconductor package structure according to the present application. With respect to the semiconductor package structure shown in fig. 1, the semiconductor package structure shown in fig. 2 may further include a stiffener 6. Wherein the reinforcement 6 may be provided between the first upper electronic element 11 and the second upper electronic element 21. The clad layer 7 may be provided between the first upper electronic element 11, the second upper electronic element 21, and the stiffener 6. The stiffener 6 may be a dummy die, the main material of which is silicon. The dummy die may not have an electrical function. Stiffener 6 may also be an electronic component of other functionality, such as a High Band Memory (HBM) chip.

In particular, the stiffener 6 may be located within the projection of the bridging element 3 in the vertical direction. A portion of the stiffener 6 may be located within a projection range of the first lower electronic element 12 or the second lower electronic element 22 in the vertical direction.

Since warpage is easily induced due to mismatch of Coefficient of Thermal Expansion (CTE) between the cladding layer 7 and the first and second upper electronic elements 11 and 21, the stiffener 6 with material similar to that of the first and second upper electronic elements 11 and 21 is used to reduce the ratio of the cladding layer 7, thereby reducing the warpage of the semiconductor package structure.

In addition, since the sizes of the first upper electronic element 11 and the second upper electronic element 21 are different from the sizes of the first lower electronic element 12 and the second lower electronic element 22, the stiffener 6 may be disposed between the first upper electronic element 11 and the second upper electronic element 21, so that the structures of the first side S1 and the second side S2 are closer to a symmetrical structure relative to the middle circuit structure 4, and the warpage of the semiconductor package structure may be reduced.

Fig. 3 is a third structural schematic diagram of a semiconductor package structure according to the present application. With respect to the semiconductor package structure shown in fig. 2, the semiconductor package structure shown in fig. 3 may further include a fourth electronic component 10 and a fifth electronic component 13. The fourth electronic component 10 and the fifth electronic component 13 may be disposed side by side above the third upper electronic component 91. In one case, the fourth electronic component 10 may be a System on Chip (SoC), and the fifth electronic component 13 may be a High Bandwidth Memory (HBM) Chip, that is, the semiconductor package structure shown in fig. 3 may be suitable for integrating various electronic components with different functions.

Fig. 4 is a fourth structural schematic diagram of a semiconductor package structure according to the present application. In the case where the sizes of the first upper electronic element 11 and the second upper electronic element 21 are equal to or larger than the sizes of the first lower electronic element 12 and the second lower electronic element 22, the stiffener 6 for reducing the occupation ratio of the clad layer 7 may be omitted, i.e., the stiffener 6 may not be included between the first upper electronic element 11 and the second upper electronic element 21 as shown in fig. 4.

Fig. 5 is a fifth structural schematic diagram of a semiconductor package structure according to the present application. The semiconductor package structure shown in fig. 5 may be manufactured by a Chip first (Chip first) process, that is, the first upper electronic element 11, the second upper electronic element 21 and the middle circuit structure 4 are not electrically connected by solder balls, so as to avoid a non-junction phenomenon.

Fig. 6 is a sixth structural schematic diagram of a semiconductor package structure according to the present application. In case the pad pitch of the bridge element 3 is the same as the pad pitch of the electronic components (e.g. the first upper electronic component 11, the second upper electronic component 21, the signal transmission assembly 8) on the first side S1 of the intermediate line structure 4, the upper line layer 41 (see fig. 5) between the bridge element 3 and the first upper electronic component 11 and the second upper electronic component 21 may be omitted, i.e. the intermediate line structure 4 in the semiconductor package structure as shown in fig. 6 may not comprise the upper line layer 41.

Fig. 7 is a seventh structural schematic diagram of a semiconductor package structure according to the present application. In the case that the electronic components on the second side S2 of the middle circuit structure 4 can be miniaturized, and the pad pitch of the bridge component 3 is the same as the pad pitch of the electronic components (e.g., the first upper electronic component 11, the second upper electronic component 21, the signal transmission assembly 8) on the first side S1 of the middle circuit structure 4 and the pad pitch of the electronic components (e.g., the first lower electronic component 12, the second lower electronic component 22, and the connector 5) on the second side S2, the upper circuit layer 41 (see fig. 5) between the bridge component 3 and the first upper electronic component 11 and the second upper electronic component 21, and the lower circuit layer 43 (see fig. 5) between the bridge component 3 and the first lower electronic component 12 and the second lower electronic component 22 can be omitted.

Fig. 8 is an eighth structural schematic diagram of a semiconductor package structure according to the present application. When the upper circuit layer 41 cannot amplify the pad size/pad pitch of the trace routed from the signal transmission component 8, the trace can be vertically connected to the first embedded bridge chip 31 in advance and then connected to the second bridge chip 32 with a wider pad pitch, so that the pad size/pad pitch can be vertically connected to the connection component 5 through the interconnection structure 44 after being amplified.

Fig. 9 to 14 are schematic structural diagrams in the manufacturing process of the semiconductor package structure according to the embodiment of the present application.

As shown in fig. 9, a carrier 14 is provided. An interconnect structure 44 is then formed on the carrier 14.

As shown in fig. 10, the bridging element 3 is placed on the carrier 14 between the interconnect structures 44. Since the bridge device 3 is prepared in advance, it can be detected in advance whether the bridge device 3 is a Known Good Die (Known Good Die) for reuse, so as to improve the yield of the whole structure.

As shown in fig. 11, a dielectric layer 42 is formed on the carrier 14 encasing the bridging element 3 and the interconnect structure 44. Dielectric layer 42 and interconnect structure 44 are then thinned using a thinning process, such as grinding, to expose bridging elements 3 and interconnect structure 44 from dielectric layer 42. Then, an upper circuit layer 41 is formed on the dielectric layer 42. By reducing the height of interconnect structure 44, signal/transmission distance can be reduced, thereby reducing transmission losses.

As shown in fig. 12, the first upper electronic element 11, the second upper electronic element 21, the third upper electronic element 91, the stiffener 6, and the signal transmission member 8 are Flip-chip bonded to the (FCB) upper wiring layer 41, respectively. Then, a clad layer 7 is formed on the upper wiring layer 41 to clad the first upper electronic element 11, the second upper electronic element 21, the third upper electronic element 91, the reinforcement 6, and the signal transmission element 8. One side of the cladding 7 is thinned.

As shown in fig. 13, a protective layer 15 is formed on the clad layer 7. The carrier 14 is then removed (see fig. 12). The dielectric layer 42 is thinned on the side opposite to the upper line layer 41. A lower wiring layer 43 continues to be formed on the dielectric layer 42.

The upper line layer 41, the dielectric layer 42, the bridging element 3, the interconnect structure 44 and the lower line layer 43 together form the intermediate line structure 4.

As shown in fig. 14, the structure in fig. 13 is turned over, and the first lower electronic component 12, the second lower electronic component 22, the third lower electronic component 92, and the connector 5 are mounted on the lower wiring layer 43, respectively. Finally, the protective layer 15 (see fig. 13) is removed, and the semiconductor package structure is obtained.

For other details and technical effects of the method in this embodiment, reference may be made to the description of the semiconductor package structure in the foregoing embodiment, which is not described herein again.

While the present application has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present application. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments without departing from the true spirit and scope of the present application as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction in the present application and the actual device due to variables in the manufacturing process and the like. There may be other embodiments of the application that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present application. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present application. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present application.

Claims (10)

1. A semiconductor package structure, comprising:

a first upper electronic element and a first lower electronic element, which are arranged in an overlapping manner, wherein the projections of the first upper electronic element and the first lower electronic element on the same horizontal plane are at least partially overlapped;

a second upper electronic element and a second lower electronic element, which are arranged in an overlapping manner, wherein projections of the second upper electronic element and the second lower electronic element on the same horizontal plane are at least partially overlapped, and a distance between the first upper electronic element and the second upper electronic element is larger than a distance between the first lower electronic element and the second lower electronic element;

a bridge element connecting the first upper electronic element and the second upper electronic element.

2. The semiconductor package structure of claim 1, further comprising:

an intermediate circuit structure separating the first upper electronic element and the first lower electronic element, and separating the second upper electronic element and the second lower electronic element.

3. The semiconductor package structure of claim 2, wherein the intermediate circuit structure comprises:

a dielectric layer, which covers the bridging element;

an interconnect structure extending through the dielectric layer;

and the lower circuit layer is arranged below the dielectric layer and connected with the interconnection structure.

4. The semiconductor package structure of claim 3, wherein the intermediate circuit structure further comprises:

and the upper circuit layer is arranged above the dielectric layer, and the interconnection structure is connected with the upper circuit layer and the lower circuit layer.

5. The semiconductor package structure of claim 3, further comprising:

and the connecting piece is arranged on the lower circuit layer and is used for providing an external connecting path.

6. The semiconductor package structure of claim 4, wherein a density of the lines in the bridging element is greater than a density of the upper line layer.

7. The semiconductor package structure according to claim 1, wherein a dimension of the first lower electronic element in an X-axis direction is larger than a dimension of the first upper electronic element in the X-axis direction, and a dimension of the second lower electronic element in the X-axis direction is larger than a dimension of the second upper electronic element in the X-axis direction.

8. The semiconductor package structure according to claim 7, wherein the first upper electronic element is located within a projection range of the first lower electronic element in a vertical direction.

9. The semiconductor package structure of claim 1, further comprising:

a stiffener disposed between the first upper electronic component and the second upper electronic component.

10. The semiconductor package structure according to claim 9, wherein the stiffener is located within a projection range of the bridge element in a vertical direction.

Images