CN218039195U - Semiconductor packaging structure - Google Patents

Abstract

In the semiconductor package structure provided by the present application, a bridging element is used as a signal transmission path between the first upper electronic element and the second upper electronic element. The selection of bridging components is mainly based on the considerations of structure thickness and signal transmission loss. In terms of structural thickness and size, the bridge element is a wafer-level product with high manufacturing precision, high yield, and easy control of impedance within a certain range, thereby reducing signal transmission loss. In terms of signal transmission loss, the size of the bridging element is small, and the effect of overall thickness reduction can be achieved by thinning the bridging element. Therefore, using the bridging element as the signal transmission path between the first upper electronic component and the second upper electronic component can simultaneously achieve the effects of reducing signal transmission loss and reducing the overall thickness.

Description

Semiconductor Package Structure

technical field

The present application relates to the technical field of semiconductors, in particular to semiconductor packaging structures.

Background technique

With the increasing demand for miniaturization, multi-function and high performance of electronic product systems, the high-density packaging structure that can integrate multiple electronic components - double-sided packaging module (Double Side Module, DSM) is getting more and more attention .

In one case, a plurality of chip-lets and memory chips that are divided into Application Specific Integrated Circuit (ASIC) chips are disposed on two sides of the substrate respectively. However, due to the increasing demand for memory capacity, the transmission distance between adjacently configured chip dies corresponding to adjacently configured memory chips becomes longer, resulting in serious signal transmission loss between chip dies. For example, a substrate can be used to connect adjacent chip dies. Although its large cross-sectional area can reduce signal transmission loss, its thickness is too large, and the insufficient precision of the circuit leads to unstable circuit impedance and affects performance. For example, a redistribution layer (Re-distribution Layer, RDL) can be used to connect adjacent chips. Although its thickness is small, its line cross-sectional area is small, its impedance is large, and its yield is low. The signal transmission loss between the configured chip dies is serious.

Utility model content

The application provides a semiconductor packaging structure, including:

The first upper electronic component and the first lower electronic component are overlapped, and the projections of the first upper electronic component and the first lower electronic component on the same horizontal plane at least partially overlap;

The second upper electronic component and the second lower electronic component are overlapped, and the projections of the second upper electronic component and the second lower electronic component on the same horizontal plane at least partially overlap, and the first upper electronic component and the second lower electronic component overlap at least partially. The distance between the two upper electronic components is greater than the distance between the first lower electronic component and the second lower electronic component;

A bridging element, connecting the first upper electronic element and the second upper electronic element.

In some optional implementation manners, the semiconductor package structure also includes:

The middle circuit structure separates the first upper electronic component from the first lower electronic component, and separates the second upper electronic component from the second lower electronic component.

In some optional embodiments, the intermediate wiring structure is provided between the first upper electronic component and the first lower electronic component, and between the second upper electronic component and the second lower electronic component. between electronic components.

In some optional implementation manners, the first upper electronic component and the first lower electronic component are arranged symmetrically on both sides of the middle circuit structure, and the second upper electronic component and the second lower electronic The elements are arranged symmetrically on both sides of the middle circuit structure.

In some optional embodiments, the intermediate circuit structure connects the first upper electronic component and the first lower electronic component, and the intermediate circuit structure connects the second upper electronic component and the second lower electronic component. Electronic component.

In some optional implementation manners, the intermediate circuit structure includes:

a dielectric layer encapsulating the bridging element;

an interconnection structure penetrating through the dielectric layer;

The lower circuit layer is disposed under the dielectric layer and connected to the interconnection structure.

In some optional implementation manners, the intermediate circuit structure further includes:

The upper circuit layer is disposed above the dielectric layer, and the interconnection structure connects the upper circuit layer and the lower circuit layer.

In some optional implementation manners, the semiconductor package structure also includes:

The connecting piece is arranged on the lower line layer, and the connecting piece is used to provide an external connection path.

In some optional embodiments, the pad spacing of the bridging element, the pad spacing of the first upper electronic component, and the pad spacing of the second upper electronic component are the same.

In some optional implementation manners, the density of the circuits in the bridge chip is greater than the density of the upper circuit layer.

In some optional embodiments, the size of the first lower electronic component in the X-axis direction is larger than the size of the first upper electronic component in the X-axis direction, and the size of the second lower electronic component in the X-axis direction is larger than the size of the second upper electronic component in the X-axis direction.

In some optional embodiments, the size of the first lower electronic component in the Y-axis direction is larger than the size of the first upper electronic component in the Y-axis direction, and the size of the second lower electronic component in the Y-axis direction is larger than the size of the second upper electronic component in the Y-axis direction.

In some optional implementation manners, the first upper electronic component is located within a vertical projection range of the first lower electronic component.

In some optional implementation manners, the second upper electronic component is located within a vertical projection range of the second lower electronic component.

In some optional implementation manners, the semiconductor package structure also includes:

The reinforcing member is arranged between the first upper electronic component and the second upper electronic component.

In some optional implementation manners, the reinforcing member is located within a projection range of the bridging element along the vertical direction.

In some optional implementation manners, a portion of the reinforcing member is located within a vertical projection range of the first lower electronic component or the second lower electronic component.

In some optional implementation manners, the semiconductor package structure also includes:

The cladding layer is arranged between the first upper electronic component, the second upper electronic component and the reinforcing member.

In the semiconductor package structure provided by the present application, the bridging element is used as a signal transmission path between the first upper electronic element and the second upper electronic element. The selection of bridging components is mainly based on the considerations of structure thickness and signal transmission loss. In terms of structural thickness and size, the bridge element is a wafer-level product with high manufacturing precision, high yield, and easy control of impedance within a certain range, thereby reducing signal transmission loss. In terms of signal transmission loss, the size of the bridging element is small, and the effect of overall thickness reduction can be achieved by thinning the bridging element. Therefore, using the bridging element as the signal transmission path between the first upper electronic component and the second upper electronic component can simultaneously achieve the effects of reducing signal transmission loss and reducing the overall thickness.

Description of drawings

Other characteristics, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

1 to 8 are first to eighth structural schematic diagrams of a semiconductor package structure according to the present application;

9 to 14 are structural schematic diagrams during the manufacturing process of the semiconductor package structure according to the embodiment of the present application.

Symbol Description:

11-first upper electronic component, 12-first lower electronic component, 21-second upper electronic component, 22-second lower electronic component, 3-bridge component, 31-first bridge chip, 32-second bridge chip , 4-intermediate circuit structure, 41-upper circuit layer, 42-dielectric layer, 43-lower circuit layer, 44-interconnection structure, 5-connector, 6-strengthener, 7-cladding layer, 8-signal Transmission assembly, 91-third upper electronic component, 92-third lower electronic component, 10-fourth electronic component, 13-fifth electronic component, 14-carrier, 15-protective layer, L1-first distance, L2- Second distance, S1-first side, S2-second side.

detailed description

The specific implementation of the present application will be described below in conjunction with the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by the present application and the technical effects produced through the contents recorded in this specification. It can be understood that the specific embodiments described here are only used to explain the relevant utility model, rather than to limit the utility model. In addition, for the convenience of description, only the parts related to the relevant utility model are shown in the drawings.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the specification are only used to match the content recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the implementation of this application. Limiting conditions, so it has no technical substantive meaning, any modification of structure, change of proportional relationship or adjustment of size, without affecting the effect and purpose of this application, should still fall within the scope of this application. The disclosed technical content must be within the scope covered. At the same time, terms such as "above", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of implementation of this application. The change or adjustment of the relative relationship shall also be regarded as the implementable scope of the present application without substantive change in the technical content.

It should also be noted that the longitudinal section corresponding to the embodiment of the present application may be a section corresponding to the front view direction, the transverse section may be a section corresponding to the right view direction, and the horizontal section may be a section corresponding to the top view direction.

It should be readily understood that the meanings of "on", "over" and "on" in this application should be interpreted in the broadest possible manner such that "on" Not only does it mean "directly on something", but it also means "on something" including an intermediate component or layer that exists between the two.

In addition, for the convenience of description, spatially relative terms such as "below", "below", "lower", "above", "upper" may be used in this application to describe Describes the relationship of one element or component to another element or component shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90° or at other orientations) and the spatially relative descriptors used in this application interpreted accordingly.

In addition, the embodiments in the present application and the features in the embodiments can be combined with each other under the condition of no conflict. The present application will be described in detail below with reference to the accompanying drawings and embodiments.

FIG. 1 is a schematic diagram of a first structure of a semiconductor package structure according to the present application. As shown in FIG. 1 , the semiconductor package structure includes a first upper electronic component 11 , a first lower electronic component 12 , a second upper electronic component 21 , a second lower electronic component 22 and a bridging component 3 . Wherein, the first upper electronic component 11 and the first lower electronic component 12 are arranged overlappingly. Projections of the first upper electronic component 11 and the first lower electronic component 12 on the same horizontal plane are at least partially overlapped. The second upper electronic component 21 and the second lower electronic component 22 are overlapped. The projections of the second upper electronic component 21 and the second lower electronic component 22 on the same horizontal plane are at least partially overlapped. A first distance L1 between the first upper electronic component 11 and the second upper electronic component 21 is greater than a second distance L2 between the first lower electronic component 12 and the second lower electronic component 22 . The bridging element 3 connects the first upper electronic element 11 and the second upper electronic element 21 .

In this embodiment, the first upper electronic component 11 , the first lower electronic component 12 , the second upper electronic component 21 and the second lower electronic component 22 may be active components and passive components. Active components can be, for example, various chips (ASIC chips, high-bandwidth memory chips, power management chips, logic function chips, storage chips, communication chips, microprocessor chips, graphics chips, photonic chips). Passive components may be, for example, capacitors, resistors, inductors, and the like. In one scenario, the first upper electronic component 11 and the second upper electronic component 21 may be ASIC chips, and the first lower electronic component 12 and the second lower electronic component 22 may be memory chips. In yet another scenario, the first upper electronic component 11 and the second upper electronic component 21 may be ASIC chips, and the first lower electronic component 12 and the second lower electronic component 22 may be power management chips.

In this embodiment, the bridge element 3 may be a bridge die. The L/S (line width/line space) of the lines in the bridge element 3 may be greater than or equal to 10 μm/10 μm. The wires in the bridging element 3 can be made of metal materials such as copper, and the thickness of the wires can be greater than or equal to 10 μm.

From the perspective of signal transmission loss, the bridge element 3 is a wafer-level product with high manufacturing precision, high yield, and easy control of impedance within a certain range, thereby reducing signal transmission loss. From the perspective of structural thickness, the size of the bridging element 3 is small, and the overall thickness can be reduced by thinning the bridging element 3 . Based on the above two perspectives, using the bridging element 3 as the signal transmission path between the first upper electronic component 11 and the second upper electronic component 21 can achieve the effects of reducing signal transmission loss and reducing the overall thickness at the same time.

In one embodiment, the size of the first lower electronic component 12 in the X-axis direction may be greater than the size of the first upper electronic component 11 in the X-axis direction. The size of the second lower electronic component 22 in the X-axis direction may be larger than the size of the second upper electronic component 21 in the X-axis direction. The size of the first lower electronic component 12 in the Y-axis direction may be greater than the size of the first upper electronic component 11 in the Y-axis direction. The size of the second lower electronic component 22 in the Y-axis direction may be greater than the size of the second upper electronic component 21 in the Y-axis direction. The first upper electronic component 11 may be located within the projection range of the first lower electronic component 12 along the vertical direction. The second upper electronic component 21 may be located within the projection range of the second lower electronic component 22 along the vertical direction.

In an embodiment, the semiconductor package structure may further include an intermediate wiring structure 4 . The intermediate circuit structure 4 can separate the first upper electronic component 11 and the first lower electronic component 12 . The middle circuit structure 4 can separate the second upper electronic component 21 and the second lower electronic component 22 . Specifically, the first upper electronic component 11 and the second upper electronic component 21 can be arranged on the first side S1 of the middle circuit structure 4, and the first lower electronic component 12 and the second lower electronic component 22 can be arranged on the side S1 of the middle circuit structure 4. Second side S2. The intermediate wiring structure 4 can connect the first upper electronic component 11 and the first lower electronic component 12 . The middle wiring structure 4 can connect the second upper electronic component 21 and the second lower electronic component 22 .

In one embodiment, the middle wiring structure 4 may include a dielectric layer 42 , an interconnection structure 44 , a lower wiring layer 43 and an upper wiring layer 41 . Wherein, the dielectric layer 42 may cover the bridging element 3 . The lower circuit layer 43 can be disposed under the dielectric layer 42 . The upper wiring layer 41 can be disposed on the dielectric layer 42 . The interconnect structure 44 may penetrate through the dielectric layer 42 . The interconnect structure 44 may connect the upper wiring layer 41 and the lower wiring layer 43 . The interconnection structure 44 may serve as a conductive path between the first upper electronic component 11 and the first lower electronic component 12 . The interconnection structure 44 may serve as a conductive path between the second upper electronic component 21 and the second lower electronic component 22 . The interconnect structure 44 may be, for example, a conductive pillar.

In one embodiment, the number of layers of the upper wiring layer 41 or the lower wiring layer 43 may be less than the number of wiring layers in the bridging element 3 . For example, the upper wiring layer 41 and the lower wiring layer 43 may include 1-2 redistribution layers. The wiring in the bridging element 3 may include at least 6 redistribution layers. The number of redistribution layers can be reduced by using the bridging element 3 .

In one embodiment, the circuit density in the bridging element 3 may be greater than that of the upper circuit layer 41 to facilitate high-speed signal transmission.

In an embodiment, the semiconductor package structure may further include a cladding layer 7 . The coating layer 7 can cover the first upper electronic component 11 and the second upper electronic component 21 .

In one embodiment, the semiconductor package structure may further include a connector 5 disposed on the lower circuit layer 43 . The connecting piece 5 can be used for external connection. The connector 5 may be, for example, a high speed signal connector (high speed connector), solder ball, ball grid array (BGA) ball, controlled collapse chip connection (C4) bump or micro bump.

In one embodiment, the semiconductor package structure may further include a signal transmission component 8 disposed on the upper circuit layer 41 . The signal transmission component 8 may be a serializer/serializer (serializer) for transmitting signals (such as data signal (data signal), power signal (power signal) (or electrical signal) and ground signal (ground signal)). /deserializer, SerDes) physical layer (physical layer, PHY) chip.

In one embodiment, the upper circuit layer 41 can make the routing of the signal transmission component 8 to expand its pad size/pad spacing. After enlarging the pad size/pad spacing through the upper circuit layer 41 , it passes through the interconnection structure 44 vertically downwards, and is connected to the connector 5 for external connection.

In an embodiment, the first side S1 of the intermediate circuit structure 4 may also be provided with a third upper electronic component 91 . The third upper electronic component 91 is spaced apart from the first upper electronic component 11 and the second upper electronic component 21 . The distance between the third upper electronic component 91 and the second upper electronic component 21 may be the same as the distance between the second upper electronic component 21 and the first upper electronic component 11 . The second side S2 of the intermediate wiring structure 4 may also be provided with a third lower electronic component 92 . The third upper electronic component 91 is spaced apart from the first lower electronic component 12 and the second lower electronic component 22 . The distance between the third lower electronic component 92 and the second lower electronic component 22 may be the same as the distance between the second lower electronic component 22 and the first lower electronic component 12 .

FIG. 2 is a schematic diagram of a second structure of a semiconductor package structure according to the present application. Compared with the semiconductor package structure shown in FIG. 1 , the semiconductor package structure shown in FIG. 2 may further include a reinforcing member 6 . Wherein, the reinforcing member 6 may be disposed between the first upper electronic component 11 and the second upper electronic component 21 . The cladding layer 7 can be disposed between the first upper electronic component 11 , the second upper electronic component 21 and the stiffener 6 . The stiffener 6 can be a dummy die whose main material is silicon. A dummy die may have no electrical function. The stiffener 6 may also be an electronic component with other functions, such as a high bandwidth memory (High Band Memory, HBM) chip.

Specifically, the reinforcing member 6 may be located within the projection range of the bridging element 3 along the vertical direction. A portion of the reinforcement member 6 may be located within the projection range of the first lower electronic component 12 or the second lower electronic component 22 along the vertical direction.

Due to the mismatch of the thermal expansion coefficient (coefficient of thermal expansion, CTE) between the cladding layer 7 and the first upper electronic component 11 and the second upper electronic component 21, it is easy to cause warping, so using the first upper electronic component 11 and the second upper electronic component Second, the reinforcing member 6 with a material similar to that of the electronic component 21 is used to reduce the proportion of the cladding layer 7 , thereby reducing the degree of warping of the semiconductor packaging structure.

In addition, since the size of the first upper electronic component 11 and the second upper electronic component 21 is different from the size of the first lower electronic component 12 and the second lower electronic component 22, the first upper electronic component 11 and the second upper electronic component The reinforcing member 6 is provided between the electronic components 21 to make the structure of the first side S1 and the second side S2 closer to a symmetrical structure with respect to the intermediate circuit structure 4 , thereby reducing the degree of warping of the semiconductor package structure.

FIG. 3 is a schematic diagram of a third structure of a semiconductor package structure according to the present application. Compared with the semiconductor package structure shown in FIG. 2 , the semiconductor package structure shown in FIG. 3 may further include a fourth electronic component 10 and a fifth electronic component 13 . The fourth electronic component 10 and the fifth electronic component 13 may be arranged side by side above the third upper electronic component 91 . In one case, the fourth electronic component 10 can be a system-on-chip (System on Chip, SoC), and the fifth electronic component 13 can be a high-bandwidth storage (High Band Memory, HBM) chip, that is, the semiconductor shown in FIG. 3 The packaging structure can be applied to the situation of integrating a variety of electronic components with different functions.

FIG. 4 is a schematic diagram of a fourth structure of a semiconductor package structure according to the present application. In the case where the size of the first upper electronic component 11 and the second upper electronic component 21 is greater than or equal to the size of the first lower electronic component 12 and the second lower electronic component 22, the method for reducing the proportion of the cladding layer 7 can be omitted. The reinforcement 6 , that is, the reinforcement 6 may not be included between the first upper electronic component 11 and the second upper electronic component 21 as shown in FIG. 4 .

FIG. 5 is a schematic diagram of a fifth structure of a semiconductor package structure according to the present application. The semiconductor package structure shown in FIG. 5 can be prepared by a chip first process, that is, the first upper electronic component 11, the second upper electronic component 21 and the intermediate circuit structure 4 do not need to be electrically connected through solder balls, thereby avoiding There is no joint (non-joint) phenomenon.

FIG. 6 is a schematic diagram of a sixth structure of a semiconductor package structure according to the present application. In the case where the pad pitch of the bridging element 3 is the same as the pad pitch of each electronic component (such as the first upper electronic component 11, the second upper electronic component 21, and the signal transmission component 8) on the first side S1 of the intermediate circuit structure 4, The upper circuit layer 41 (see FIG. 5 ) between the bridging element 3 and the first upper electronic component 11 and the second upper electronic component 21 can be omitted, that is, the intermediate circuit structure 4 in the semiconductor package structure shown in FIG. 6 can be The upper line layer 41 is not included.

FIG. 7 is a schematic diagram of a seventh structure of a semiconductor package structure according to the present application. The size of the electronic components on the second side S2 of the intermediate circuit structure 4 can be miniaturized, and the spacing between the pads of the bridging element 3 and the electronic components on the first side S1 of the intermediate circuit structure 4 (for example, the first upper electronic component 11, the second upper In the case where the electronic components 21, the signal transmission components 8), and the electronic components on the second side S2 (such as the first lower electronic component 12, the second lower electronic component 22, and the connector 5) have the same pad spacing, the bridging can be omitted. The upper circuit layer 41 between the component 3 and the first upper electronic component 11 and the second upper electronic component 21 (see FIG. 5 ), the lower circuit layer between the bridging component 3 and the first lower electronic component 12 and the second lower electronic component 22 The wiring layer 43 (see FIG. 5 ).

FIG. 8 is a schematic diagram of an eighth structure of a semiconductor package structure according to the present application. When the upper line layer 41 cannot allow the wiring of the signal transmission component 8 to enlarge its pad size/pad spacing, it can be vertically connected downwards to the buried first bridge chip 31 in advance, and then connected upwards with The second bridge chip 32 with a wider pad pitch can pass through the interconnection structure 44 vertically and connect to the connecting element 5 after the pad size/pad pitch is enlarged.

9 to 14 are structural schematic diagrams during the manufacturing process of the semiconductor package structure according to the embodiment of the present application.

As shown in Figure 9, a carrier 14 is provided. Interconnect structure 44 is then formed on carrier 14 .

As shown in FIG. 10 , the bridging elements 3 are placed on the carrier 14 between the interconnect structures 44 . Since the bridging element 3 is pre-fabricated, it can be pre-tested to determine whether the bridging element 3 is a known good chip (Known Good Die) and reused, so as to improve the yield of the overall structure.

As shown in FIG. 11 , a dielectric layer 42 covering the bridging elements 3 and the interconnection structure 44 is formed on the carrier 14 . Then, the dielectric layer 42 and the interconnection structure 44 are thinned by a thinning process such as grinding, so that the bridging element 3 and the interconnection structure 44 are exposed from the dielectric layer 42 . An upper circuit layer 41 is then formed on the dielectric layer 42 . By reducing the height of the interconnect structure 44, the signal/transmission distance can be reduced, thereby reducing transmission loss.

As shown in FIG. 12, the first upper electronic component 11, the second upper electronic component 21, the third upper electronic component 91, the stiffener 6 and the signal transmission component 8 are flip-chip bonded to (Flip chip bonding, FCB) respectively. Line layer 41. Then, a cladding layer 7 covering the first upper electronic component 11 , the second upper electronic component 21 and the third upper electronic component 91 , the stiffener 6 and the signal transmission component 8 is formed on the upper circuit layer 41 . One side of the coating layer 7 is further thinned.

As shown in FIG. 13 , a protective layer 15 is formed on the clad layer 7 . The carrier 14 is then removed (see Figure 12). The side of the dielectric layer 42 opposite to the upper circuit layer 41 is further thinned. Continue to form the lower circuit layer 43 on the dielectric layer 42 .

The upper wiring layer 41 , the dielectric layer 42 , the bridging elements 3 , the interconnection structure 44 and the lower wiring layer 43 together form the middle wiring structure 4 .

As shown in FIG. 14 , the structure in FIG. 13 is turned over, and the first lower electronic component 12 , the second lower electronic component 22 , the third lower electronic component 92 and the connector 5 are respectively mounted on the lower circuit layer 43 . Finally, the protection layer 15 (see FIG. 13 ) is removed to obtain a semiconductor package structure.

For other details and technical effects of the method in this embodiment, reference may be made to the description of the semiconductor package structure in the foregoing embodiments, which will not be repeated here.

While the application has been described and illustrated with reference to particular embodiments of the application, these descriptions and illustrations do not limit the application. It will be clearly understood by those skilled in the art that various changes may be made and equivalent elements may be substituted within the embodiments without departing from the true spirit and scope of the application as defined by the appended claims. Illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the technical reproduction in this application and the actual device. There may be other embodiments of the application not specifically described. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the application. All such modifications are intended to fall within the scope of the claims appended hereto. Although methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that such operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this application. Accordingly, the order and grouping of operations does not limit the application unless otherwise indicated herein.

Claims (10)

1. A semiconductor packaging structure, comprising: The first upper electronic component and the first lower electronic component are overlapped, and the projections of the first upper electronic component and the first lower electronic component on the same horizontal plane at least partially overlap; The second upper electronic component and the second lower electronic component are overlapped, and the projections of the second upper electronic component and the second lower electronic component on the same horizontal plane at least partially overlap, and the first upper electronic component and the second lower electronic component overlap at least partially. The distance between the two upper electronic components is greater than the distance between the first lower electronic component and the second lower electronic component; A bridging element, connecting the first upper electronic element and the second upper electronic element. 2. The semiconductor package structure according to claim 1, wherein the semiconductor package structure further comprises: The middle circuit structure separates the first upper electronic component from the first lower electronic component, and separates the second upper electronic component from the second lower electronic component. 3. The semiconductor package structure according to claim 2, wherein the intermediate circuit structure comprises: a dielectric layer encapsulating the bridging element; an interconnection structure penetrating through the dielectric layer; The lower circuit layer is disposed under the dielectric layer and connected to the interconnection structure. 4. The semiconductor package structure according to claim 3, wherein the intermediate circuit structure further comprises: The upper circuit layer is disposed above the dielectric layer, and the interconnection structure connects the upper circuit layer and the lower circuit layer. 5. The semiconductor package structure according to claim 3, wherein the semiconductor package structure further comprises: The connecting piece is arranged on the lower line layer, and the connecting piece is used to provide an external connection path. 6 . The semiconductor package structure according to claim 4 , wherein the density of the wires in the bridging element is greater than the density of the upper wire layer. 6 . 7. The semiconductor package structure according to claim 1, wherein the size of the first lower electronic component in the X-axis direction is larger than the size of the first upper electronic component in the X-axis direction, and the second lower electronic component The size of the electronic component in the X-axis direction is larger than the size of the second upper electronic component in the X-axis direction. 8 . The semiconductor package structure according to claim 7 , wherein the first upper electronic component is located within a projection range of the first lower electronic component along the vertical direction. 9. The semiconductor package structure according to claim 1, wherein the semiconductor package structure further comprises: The reinforcing member is arranged between the first upper electronic component and the second upper electronic component. 10 . The semiconductor package structure according to claim 9 , wherein the reinforcing member is located within a projected range of the bridging element along the vertical direction. 11 .

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