CN217788403U

CN217788403U - Car-gauge-grade 4H-SiC-based super-junction power MOSFET element

Info

Publication number: CN217788403U
Application number: CN202221986451.3U
Authority: CN
Inventors: 谢速
Original assignee: Jiefang Semiconductor Shanghai Co ltd
Current assignee: Jiefang Semiconductor Shanghai Co ltd
Priority date: 2022-07-29
Filing date: 2022-07-29
Publication date: 2022-11-11
Anticipated expiration: 2032-07-29

Abstract

The utility model discloses a car rule level 4H-SiC base super junction power MOSFET component, its cellular structure of unit includes the grid, source electrode and drain electrode, the top of buffer layer is located to the resistance to pressure layer, set up the grid in the left side of resistance to pressure layer, set up the semiconductor body area on the right side of resistance to pressure layer, the semiconductor source area is located the semiconductor body area, the grid covers the surface of going up side and the left side surface of partial semiconductor body area and partial semiconductor source area at partial resistance to pressure layer, still be formed with the subsider in the semiconductor body area, set up the source electrode in the subsider, the semiconductor substrate layer covers at the lower surface of buffer layer and is formed with the drain electrode; the buffer blocking layer is divided into two parts according to the thickness, the thicker part is positioned below the first semiconductor drift region and part of the second semiconductor drift region, and the thinner part is positioned below the second semiconductor drift region. The device improves the current conducting capacity of the device, reduces the cell size of the device, and improves the UIS avalanche tolerance capacity of the MOSFET device.

Description

Car-gauge-grade 4H-SiC-based super-junction power MOSFET element

Technical Field

The utility model relates to semiconductor power device technical field, concretely relates to car rule level 4H-SiC base surpasses knot power MOSFET component.

Background

The super junction power MOSFET (namely, the metal-oxide-semiconductor field effect transistor) is a structure which is proposed for improving the contradiction between the Breakdown Voltage (BV) and the specific on-resistance (RON, SP) in the traditional power MOSFET, and the structure changes the relation between the breakdown voltage and the specific on-resistance from RON, SP ═ BV2.5 to RON, SP ℃; BV1.3 of the traditional power MOSFET, greatly reduces the on-resistance of the power MOSFET, reduces the area of a chip, and is widely applied to middle and low power supply equipment.

The super junction power MOSFET is a few-electron conducting device, only one kind of current carrier participates in conduction when the super junction power MOSFET is conducted, for example, in an n-type channel device, only electrons participate in conduction, and the electrons flow in an n column of a super junction structure; meanwhile, the p column in the super junction structure does not contribute to the capability of conducting current of the device, and the function of the super junction structure is to provide ionized acceptor impurities when the super junction structure is in forward blocking so as to absorb electric lines of force emitted by the ionized donor impurities in the n column, thereby improving the breakdown voltage of the device. Therefore, how to further improve the on-current capability of the device by using p-pillar conduction, reduce the specific on-resistance of the device, reduce the chip area, and shorten the turn-off time becomes a new research direction.

Disclosure of Invention

The utility model aims at the not enough of prior art, the utility model aims at providing a car rule level 4H-SiC base surpasses knot power MOSFET component to shorten turn-off time, reduce the switching power consumption, can also reduce device cell size, improve the UIS avalanche tolerance of device.

In order to achieve the purpose, the utility model adopts the technical proposal as follows:

the key point of the vehicle-scale 4H-SiC-based super junction power MOSFET element is that: the cell structure comprises a grid electrode, a source electrode, a drain electrode, a pressure-resistant layer, a buffer barrier layer, a semiconductor body region, a semiconductor source region and a semiconductor substrate layer, wherein the pressure-resistant layer is arranged above the buffer barrier layer, the grid electrode is arranged on the left side of the pressure-resistant layer, the semiconductor body region is arranged on the right side of the pressure-resistant layer, the semiconductor source region is positioned in the semiconductor body region, the grid electrode covers part of the upper side surface of the pressure-resistant layer and part of the semiconductor body region and part of the left side surface of the semiconductor source region, a subsider is further formed in the semiconductor body region, the source electrode is arranged in the subsider and is further connected with the semiconductor source region through a conductor, the semiconductor substrate layer covers the lower surface of the buffer barrier layer, and a conductor covers the lower surface of the semiconductor substrate layer to form the drain electrode;

the voltage-resisting layer is composed of a first semiconductor drift region with a certain conduction type and a second semiconductor drift region with a conduction type opposite to the conduction type of the first semiconductor drift region, wherein the first semiconductor drift region is in contact with the grid and the lower surface of part of the semiconductor body region, and the second semiconductor drift region is in contact with the semiconductor body region;

the buffer blocking layer is divided into two parts according to the thickness, the thicker part is located below the first semiconductor drift region and part of the second semiconductor drift region, and the thinner part is located below the second semiconductor drift region.

Further, the height of the first semiconductor drift region in the vertical direction is smaller than that of the second semiconductor drift region.

Further, the super junction structure formed by the first semiconductor drift region and the second semiconductor drift region is arranged in a manner including, but not limited to, any one of a stripe shape, a hexagon shape, a rectangle shape or a circle shape.

Further, the gate electrode is composed of a gate insulating layer, a semiconductor polysilicon gate layer and a conducting layer, the gate insulating layer is in an L shape and covers part of the upper side surface of the voltage-withstanding layer, part of the semiconductor body region and part of the left side surface of the semiconductor source region, the semiconductor polysilicon gate layer is arranged between the horizontal part and the vertical part of the gate insulating layer, and the conducting layer covers the upper surface of the semiconductor polysilicon gate layer.

Furthermore, the left side surface and the upper side surface of the semiconductor polycrystalline silicon gate layer are flush with the gate insulating layer, and the projection area of the conducting layer in the vertical direction is smaller than that of the semiconductor polycrystalline silicon gate layer.

The utility model discloses a show the effect and be:

1. the semiconductor body region is sunk, and the source electrode is arranged at the sinking position, so that the current path is effectively shortened, the current conducting capacity of the device is improved, the cell size of the device is reduced, the area of the device is reduced, the UIS avalanche tolerance capacity of the MOSFET device is improved, the turn-off time is shortened, and the switch power consumption is reduced;

2. the thicker part of the buffer barrier layer is simultaneously used as a semiconductor minority carrier blocking region to block the current carriers of the second conductivity type from entering the semiconductor first drift region, so that the formation of conductance modulation in the voltage-resisting layer is avoided; meanwhile, the buffer barrier layer serving as the semiconductor minority carrier blocking region can further increase the thickness of the part of the semiconductor minority carrier blocking region with the thicker buffer barrier layer to block minority carriers, so that the formation of conductance modulation in the voltage-resistant layer is avoided, the capability of conducting current of the device is improved, the specific on-resistance of the device is reduced, and the element area is reduced compared with the traditional technology.

Drawings

Fig. 1 is a schematic structural diagram of the present invention.

Detailed Description

The following describes the embodiments and the operation principle of the present invention in detail with reference to the accompanying drawings.

As shown in fig. 1, a vehicle-scale 4H-SiC-based super junction power MOSFET device is formed by mutually splicing a plurality of repeating cell structures, each cell structure includes a drain 10, a source 20, a gate 30, a voltage-withstanding layer 40, a buffer barrier layer 50, a semiconductor body 60, a semiconductor source region 70, and a semiconductor substrate layer 80, the voltage-withstanding layer 40 is disposed above the buffer barrier layer 50, the gate 30 is disposed on the left side of the voltage-withstanding layer 40, the semiconductor body 60 is disposed on the right side of the voltage-withstanding layer 40, the semiconductor source region 70 is located in the semiconductor body 60, the gate 30 covers part of the upper surface of the voltage-withstanding layer 40 and part of the semiconductor body 60 and part of the left surface of the semiconductor source region 70, a sinker is further formed in the semiconductor body 60, the source 20 is disposed in the sinker, the source 20 is further connected to the semiconductor source region 70 through a conductor, the semiconductor substrate layer 80 covers the lower surface of the buffer barrier layer 50, and the drain 10 is formed by covering the conductor on the lower surface of the semiconductor substrate layer 80.

As shown in fig. 1, the gate 30 is composed of a gate insulating layer 31, a semiconductor polysilicon gate layer 32 and a conductive layer 33, the gate insulating layer 31 is L-shaped and covers part of the upper surface of the voltage-withstanding layer 40 and part of the left side surface of the semiconductor body 60 and part of the semiconductor source region 70, the semiconductor polysilicon gate layer 32 is disposed between the horizontal portion and the vertical portion of the gate insulating layer 31, and the conductive layer 33 covers the upper surface of the semiconductor polysilicon gate layer 32.

Further, the left side surface and the upper side surface of the semiconductor polysilicon gate layer 32 are flush with the gate insulating layer 31, and the projection area of the conductive layer 33 in the vertical direction is smaller than that of the semiconductor polysilicon gate layer 32.

In this example, the voltage-withstanding layer 40 is composed of a first semiconductor drift region 41 having a first conductivity type and a second semiconductor drift region 42 having a second conductivity type opposite to the conductivity type of the first semiconductor drift region 41, wherein the first conductivity type is N type, and the second conductivity type is P type; the upper surface of the first semiconductor drift region 41 is in contact with the gate 30 and the lower surface of a part of the semiconductor body region 60, the upper surface of the second semiconductor drift region 42 is in contact with the semiconductor body region 60, and the height of the first semiconductor drift region 41 in the vertical direction is smaller than that of the second semiconductor drift region 42.

Optionally, the arrangement of the super junction structure formed by the first semiconductor drift region 41 and the second semiconductor drift region 42 includes, but is not limited to, any one of a stripe, a hexagon, a rectangle, or a circle.

As can also be seen from fig. 1, the buffer barrier layer 50 is divided into two parts according to thickness, a thicker part is located below the first semiconductor drift region 41 and a part of the second semiconductor drift region 42, and a thinner part is located below the second semiconductor drift region 42.

The thicker part of the buffer barrier layer 50 is simultaneously used as a semiconductor minority carrier blocking region to block the second conductive type of carriers from entering the first semiconductor drift region 41, so that the formation of conductance modulation in the voltage-resistant layer is avoided; meanwhile, the buffer barrier layer serving as the semiconductor minority carrier blocking region can block minority carriers by further increasing the thickness of the part of the semiconductor minority carrier blocking region with the thicker buffer barrier layer, so that the formation of conductance modulation in the voltage-resistant layer 40 is avoided, the capability of conducting current of the device is improved, the specific on-resistance of the device is reduced, and the element area is reduced compared with the conventional technology.

In this embodiment, the conductivity type of the buffer blocking layer 50 is N type, the conductivity type of the semiconductor body region 60 is P type, the conductivity type of the semiconductor source region 70 is N type, and the conductivity type of the semiconductor substrate layer 80 is P type.

A part of the source electrode 20, the gate electrode 30, the first semiconductor drift region 41, the buffer blocking layer 50, the semiconductor substrate layer 80 and the drain electrode 10 form a MOSFET with N-type conductivity, so that carriers of the first conductivity type mainly flow in the MOSFET; part of the source 20 forms with the semiconductor body 60, the second semiconductor drift region 42, the semiconductor buffer region 51, part of the semiconductor substrate layer 80 and the drain 10 a bipolar junction transistor-BJT of conductivity type P, such that carriers of the second conductivity type flow mainly in the BJT.

In the embodiment, the semiconductor body region 60 is sunk, and the source electrode 20 is arranged at the sinking position, so that the current path is effectively shortened, the cell size of a device is reduced, the area of the device is reduced, the UIS avalanche tolerance capability of the MOSFET device is improved, the turn-off time is shortened, and the switching power consumption is reduced.

The technical scheme provided by the utility model is introduced in detail above. The principles and embodiments of the present invention have been explained herein using specific examples, and the above descriptions of the embodiments are only used to help understand the method and its core ideas of the present invention. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, the present invention can be further modified and modified, and such modifications and modifications also fall within the protection scope of the appended claims.

Claims

1. A car-scale 4H-SiC-based super junction power MOSFET element is characterized in that a cell structure comprises a grid electrode, a source electrode and a drain electrode, and the power MOSFET element comprises: the semiconductor device further comprises a voltage-resisting layer, a buffer barrier layer, a semiconductor body region, a semiconductor source region and a semiconductor substrate layer, wherein the voltage-resisting layer is arranged above the buffer barrier layer, the grid electrode is arranged on the left side of the voltage-resisting layer, the semiconductor body region is arranged on the right side of the voltage-resisting layer, the semiconductor source region is located in the semiconductor body region, the grid electrode covers part of the upper side surface of the voltage-resisting layer and part of the left side surface of the semiconductor body region and part of the left side surface of the semiconductor source region, a settling tank is formed in the semiconductor body region, the source electrode is arranged in the settling tank and is connected with the semiconductor source region through a conductor, the semiconductor substrate layer covers the lower surface of the buffer barrier layer, and the conductor covers the lower surface of the semiconductor substrate layer to form the drain electrode;

the voltage-resistant layer is composed of a first semiconductor drift region with a certain conduction type and a second semiconductor drift region with a conduction type opposite to the conduction type of the first semiconductor drift region, the upper surface of the first semiconductor drift region is in contact with the grid and the lower surface of part of the semiconductor body region, and the upper surface of the second semiconductor drift region is in contact with the semiconductor body region;

2. The vehicle scale grade 4H-SiC based superjunction power MOSFET element of claim 1, wherein: the height of the first semiconductor drift region in the vertical direction is smaller than that of the second semiconductor drift region.

3. The vehicle scale grade 4H-SiC based superjunction power MOSFET element of claim 2, wherein: the arrangement mode of the super junction structure formed by the first semiconductor drift region and the second semiconductor drift region includes, but is not limited to, any one of a stripe shape, a hexagon shape, a rectangle shape or a circle shape.

4. The vehicular grade 4H-SiC based superjunction power MOSFET element of claim 1, wherein: the gate comprises a gate insulating layer, a semiconductor polycrystalline silicon gate layer and a conducting layer, the gate insulating layer is L-shaped and covers the upper side surface of part of the pressure-resistant layer, the left side surface of part of the semiconductor body region and the left side surface of part of the semiconductor source region, the semiconductor polycrystalline silicon gate layer is arranged between the horizontal part and the vertical part of the gate insulating layer, and the conducting layer covers the upper surface of the semiconductor polycrystalline silicon gate layer.

5. The vehicle scale grade 4H-SiC based superjunction power MOSFET element of claim 4, wherein: the left side surface and the upper side surface of the semiconductor polycrystalline silicon gate layer are flush with the gate insulating layer, and the projection area of the conducting layer in the vertical direction is smaller than that of the semiconductor polycrystalline silicon gate layer.