CN215496711U

CN215496711U - Electronic device

Info

Publication number: CN215496711U
Application number: CN202120704231.6U
Authority: CN
Inventors: F·奎尔恰; J-M·里维雷
Original assignee: STMicroelectronics Grenoble 2 SAS
Current assignee: STMicroelectronics Grenoble 2 SAS
Priority date: 2020-04-08
Filing date: 2021-04-07
Publication date: 2022-01-11
Anticipated expiration: 2031-04-07
Also published as: CN113497018A

Abstract

An electronic device is disclosed. An electronic device includes a base substrate having a mounting surface. The electronic chip is fixed to the mounting surface of the base substrate. The transparent encapsulation structure is bonded to the base substrate. The transparent encapsulation structure includes a housing having an interior cavity defining a cavity that houses an electronic chip. The package structure has an outer surface that supports a filtered optical wafer positioned facing the optical elements of the electronic chip. The opaque cover covers the transparent encapsulation structure and includes a partial opening facing the filtering optics wafer. The technical scheme of the embodiment can reduce the production uncertainty of the transparent element for packaging the electronic chip.

Description

Electronic device

Technical Field

Embodiments and implementations of the present invention relate to the field of microelectronics, and more particularly, to the field of packaging of electronic devices including electronic integrated circuit chips integrated with optical elements.

Background

Conventional electronic devices include electronic Integrated Circuit (IC) chips that integrate optical elements embedded in a transparent resin layer distributed over the surface of a base substrate.

The transparent resin layer typically supports an optical wafer that forms an optical assembly with integrated optical elements.

In a conventional electronic device manufacturing process, several electronic integrated circuit chips are fixed on the same substrate, they are embedded in a transparent resin layer, and then they are subsequently separated from other electronic integrated circuit chips of the substrate.

To separate the electronic chips, the transparent resin layer is cut, for example, using a saw. Each resin block then encapsulates a single electronic chip and its associated optical element.

Such an arrangement is problematic because each resin block may have shape uncertainty caused by the production method used, impairing, in particular, the precise assembly of the package cover on the resin block, or indeed the optical assembly formed by the integrated optical element and the optical wafer.

In practice, a gap may be formed between the transparent resin and the cover, for example, after the heat treatment.

Further, the resin block may have shape defects due to, for example, misalignment and/or abrasion of a saw cutting the resin layer.

It is therefore desirable to reduce the production uncertainty of transparent elements encapsulating electronic chips (which integrate optical elements).

SUMMERY OF THE UTILITY MODEL

In view of the above-described production uncertainty issues for transparent elements that encapsulate electronic chips, embodiments of the present disclosure aim to provide electronic devices with improved performance.

An embodiment of the present disclosure provides an electronic device, including: a base substrate having a mounting surface; at least one electronic chip having a back surface and a front surface, the back surface being secured to the mounting surface of the base substrate, the front surface integrating the optical element; a transparent encapsulation structure bonded to the base substrate, the transparent encapsulation structure comprising at least one housing, the at least one housing comprising an interior cavity defining a cavity to house the at least one electronic chip; a filtering optics die supported by and on the outer surface of the package structure and facing each of the optical elements; and an opaque cover covering the transparent encapsulation structure and the filtering optics wafer, the opaque cover including a partial opening exposing at least a portion of the filtering optics wafer.

In some embodiments, the transparent package structure is provided with a hollow front recess on an outer surface of the package structure facing each optical element, wherein the filtering optics die is mounted within the hollow front recess.

In some embodiments, the at least one electronic chip includes a first electronic chip and a second electronic chip, and further includes an opaque separator between the first electronic chip and the second electronic chip.

In some embodiments, the at least one housing is formed from a single transparent housing defining a single chamber that houses both the first electronic chip and the second electronic chip, and wherein the opaque partition comprises an opaque volume located inside the single chamber.

In some embodiments, the opaque volume is made of an adhesive material.

In some embodiments, the at least one housing comprises: a first transparent housing defining a first chamber housing a first electronic chip; and a second transparent housing defining a second chamber containing a second electronic chip, and wherein the opaque partition occupies an intermediate space outside the first and second chambers between the first and second chambers.

In some embodiments, the at least one housing comprises a single transparent housing defining a first chamber and a second chamber, the first chamber housing the first electronic chip and the second chamber housing the second electronic chip, and wherein the opaque partition occupies an intermediate space outside of the first and second chambers between the first and second chambers.

In some embodiments, the single transparent housing includes a planar portion connecting the first and second chambers and located on the base substrate.

In some embodiments, the base substrate includes a hollow recess in a mounting face of the base substrate, and wherein the planar portion of the single transparent housing is mounted within the recess.

In some embodiments, the opaque cover incorporates an opaque partition in the intermediate space.

In some embodiments, the opaque dividers completely fill the intermediate space.

In some embodiments, the opaque cover is joined to the free top surface of the opaque divider.

In some embodiments, the opaque cover and the opaque divider are made of an opaque material sputtered onto an outer surface of the transparent encapsulation structure.

In some embodiments, the optical element integrated in the first electronic chip comprises a radiation emitter, and wherein the optical element integrated in the second electronic chip comprises a radiation receiver configured to receive radiation emitted by the radiation emitter after reflection from an element external to the opaque cover.

The technical scheme of the embodiment can reduce the production uncertainty of the transparent element for packaging the electronic chip.

Embodiments of the present disclosure provide electronic devices with improved performance that can reduce production uncertainty of transparent elements that encapsulate electronic chips.

Drawings

Further advantages and characteristics of the utility model will emerge in a non-limiting manner from a study of the examples and embodiments and the detailed description of the drawings, in which:

FIGS. 1A, 2A, and 3A illustrate three embodiments of an electronic device;

FIGS. 1B, 2B and 3B show three-dimensional views of a transparent encapsulation structure;

FIGS. 4A, 4B, and 4C illustrate embodiments of opaque covers; and

fig. 5 is a flowchart.

Detailed Description

According to one aspect, an electronic device comprises: a base substrate having a mounting surface; at least one electronic chip including a back surface fixed to the mounting surface of the base substrate and having an optical element integrated on a front surface of the at least one electronic chip; a transparent encapsulation structure bonded to the base substrate, comprising at least one housing comprising an internal cavity defining a cavity housing the at least one electronic chip and supporting a filtered optics wafer positioned facing each optical element on an outer surface of the encapsulation structure; and an opaque cover covering the transparent encapsulation structure and including a partial opening positioned facing each optics die.

Thus, the shape and optical properties of the transparent encapsulation structure can be controlled from upstream of the bonding on the base substrate. The package structure also enables the holding of the filtered optics die on the outer surface of the package structure, the position and shape of which can be controlled from upstream of the bonding on the base substrate.

Therefore, problems of the conventional art such as saw alignment or saw wear are not caused, and the structure of the electronic apparatus is better controlled.

Furthermore, the opaque cover enables to cover the transparent encapsulation structure so that only each filtered optics wafer allows the passage of light entering the interior of the chamber and light coming from the outside of the chamber and vice versa. Similarly, the opaque cover may have a controlled shape before covering the transparent encapsulation structure.

According to an embodiment, the transparent encapsulation is provided with a hollow front recess located on the outer surface of the encapsulation facing each optical element and housing the filtering optics die.

In other words, the empty front recess in the package structure enables the optical die to be held in a fixed position on the outer surface of the package structure.

According to an embodiment, the at least one electronic chip comprises a first electronic chip and a second electronic chip, the device further comprising an opaque separator between the first electronic chip and the second electronic chip.

Thus, the opaque partition enables to advantageously prevent an optical path between the first optical element of the first electronic chip and the second optical element of the second electronic chip.

According to an embodiment, the at least one housing comprises a single transparent housing defining a single chamber housing the first and second electronic chips, and the opaque partition comprises an opaque adhesive volume located inside the chamber.

Thus, a single chamber then accommodates the first and second electronic chips, and it is the opaque adhesive volume that makes it possible to prevent a direct optical path inside the chamber between the first optical element of the first electronic chip and the second optical element of the second electronic chip.

According to a further embodiment, the at least one housing comprises a first transparent housing defining a first chamber housing the first electronic chip and a second transparent housing defining a second chamber housing the second electronic chip, an intermediate space outside the chambers separating the first and second chambers.

Thus, the relative position of the first chamber with respect to the second chamber is free, and the intermediate space between the first chamber and the second chamber makes it possible not to form a waveguide between the first chamber and the second chamber.

According to a further embodiment, the at least one housing comprises a single transparent housing defining a first chamber housing the first electronic chip and a second chamber housing the second electronic chip, an intermediate space outside the chambers separating the first and second chambers, the housing comprising a planar portion connecting the chambers and located on the base substrate.

Thus, the relative position of the first chamber with respect to the second chamber is limited by the size of the planar portion connecting the two chambers, which makes it possible to accurately position the first chamber with respect to the second chamber.

According to an embodiment, the base substrate comprises a recess which is hollow in the mounting face of the base substrate and which contains the planar portion of the housing.

Advantageously, the hollow recess in the mounting face of the base substrate makes it possible for the planar portion of the housing not to form an optical path between the first and second chambers.

The opaque cover may or may not include an opaque partition that optically separates the first and second chambers.

According to an embodiment, the opaque cover incorporates an opaque partition inserted into the intermediate space between the first and second chambers.

According to a further embodiment, an opaque partition fills an intermediate space between the first and second chambers, and an opaque cover is joined to a free top surface of the opaque partition.

According to a further embodiment, the opaque cover and the opaque divider comprise an opaque material sputtered onto an outer surface of the transparent encapsulation structure.

According to an embodiment, the optical element integrated in the first electronic chip comprises a radiation emitter and the optical element integrated in the second electronic chip comprises a radiation receiver, the optical element integrated in the second electronic chip being intended to receive the radiation emitted by the optical element integrated in the first electronic chip after reflection on an external element.

According to another aspect, a method for manufacturing an electronic device is shown, comprising: securing a back surface of at least one electronic chip to the mounting surface of the base substrate, the at least one electronic chip integrating the optical element on the front surface; bonding a transparent encapsulation structure on the mounting surface of the substrate, the transparent encapsulation structure comprising at least one housing including an internal cavity defining cavities such that each cavity contains the at least one electronic chip; mounting a filtered optical die to the transparent package structure facing each of the integrated optical elements; an opaque cover covering the package structure is mounted to position a partial opening of the opaque cover facing each integrated optical element.

According to one embodiment, the filtering optics die is mounted in a hollow front recess located on the outer surface of the packaging structure facing each optical element and is envisaged to house the optics die.

According to one embodiment, the at least one electronic chip includes a first electronic chip and a second electronic chip, and the bonding of the package structure includes placing an opaque spacer between the first electronic chip and the second electronic chip.

According to one embodiment, the at least one housing defines a single cavity, the joining of the encapsulation structure includes the housing in the cavity of the first electronic chip and the second electronic chip, and the placing of the opaque partition includes forming an opaque adhesive volume between the first electronic chip and the second electronic chip.

According to one embodiment, the at least one housing comprises a first transparent housing defining a first chamber and a second transparent housing defining a second chamber, the joining of the transparent encapsulation structure comprising an arrangement of the first housing and the second housing so as to house the first electronic chip in the first chamber and the second electronic chip in the second chamber, and leaving an intermediate space outside the chambers, which separates the first chamber from the second chamber.

According to one embodiment, the at least one housing comprises a single transparent housing defining a first chamber and a second chamber, an intermediate space outside the chambers separating the first chamber and the second chamber, the housing comprising a planar portion connecting the chambers, the bonding of the package structure comprises accommodating the first electronic chip in the first chamber and the second electronic chip in the second chamber, and the planar portion is positioned on the base substrate.

According to one embodiment, the method further comprises: a hollow recess is formed in the mounting surface, the hollow recess being intended to receive a planar portion of the housing, and the planar portion being positioned in the hollow recess of the mounting surface.

According to one embodiment, placing the opaque partition comprises inserting the opaque partition contained in the opaque cover in an intermediate space between the first transparent chamber and the second transparent chamber.

According to one embodiment, placing the opaque divider comprises filling an intermediate space between the first and second chambers with an opaque material, followed by bonding an opaque cover onto a free top surface of the opaque divider.

According to one embodiment, mounting the opaque cover on the encapsulation structure and placing the opaque partition includes sputtering an opaque material onto an outer surface of the transparent encapsulation structure.

According to an implementation mode, the optical element integrated in the first electronic chip comprises a radiation emitter and the optical element integrated in the second electronic chip comprises a radiation receiver, the optical element integrated in the second electronic chip being intended to receive the radiation emitted by the optical element integrated in the first electronic chip after reflection on an external element.

Fig. 1A, 2A, and 3A illustrate three embodiments of an electronic device that includes a base substrate SS that includes a mounting surface FM on which electronic Integrated Circuit (IC) chips are mounted and electrically coupled to an interconnection network of the base substrate SS.

The base substrate includes a back side on which metal connections of the interconnection network are used to connect the device with external equipment.

The transparent package structure is bonded to the mounting surface FM of the base substrate SS.

The encapsulation structure may be, for example, a component made of transparent plastic which is manufactured separately from the base substrate SS, for example, by means of injection molding techniques.

The transparent encapsulation structure comprises one or more transparent shells ST1-1, ST1-2, ST2, ST3, each having an internal cavity forming one or more chambers, each chamber being intended to house one or more electronic chips PE1, PE2 of the integrated optical element.

Herein, the phrase "chamber for accommodating an electronic chip" means a free space capable of accommodating a volume of at least one electronic chip.

The chamber is defined on the one hand by the inner surface of the transparent casing and on the other hand by the mounting face of the base substrate SS. In other words, the chamber housing the electronic chip is optionally a sealed, closed free space, optionally filled with a quasi-vacuum gas.

The transparent encapsulation structure is particularly intended to support a filtering optics wafer PA1, PA2 located on the outer surface of the encapsulation structure facing each optical element of the electronic chip. These filtering optics dies PA1, PA2 may have, for example, a square or rectangular shape in plan view (i.e., view towards the top surface of the transparent package structure).

In other words, the optics wafers PA1, PA2 are positioned so that the light rays reaching each optical element are filtered in advance by the respective optics wafer, and conversely, so that the light rays emitted by each optical element are filtered by the respective optics wafer exiting the chamber housing the optical element.

The filter optics PA1, PA2 may advantageously be located in the empty recesses EV1, EV2, the empty recesses EV1, EV2 being located on the outer surface of the package structure.

Alternatively, the optics wafers PA1, PA2 may be disposed (e.g., bonded) on the planar outer surface of the package structure facing the respective optical elements.

According to various examples, the package structure may include one or more housings, each housing including a cavity, each cavity containing one or more electronic chips.

The packaging structure may for example comprise a single casing ST2, wherein a first cavity contains the first electronic chip PE1 and a second cavity contains the second electronic chip PE 2.

Otherwise, the packaging structure may for example comprise a single casing ST3, wherein a single cavity accommodates the first electronic chip PE1 and the second electronic chip PE 2.

Otherwise, the packaging structure may for example comprise two separate shells, a first shell ST1-1 comprising a first cavity housing the first electronic chip PE1 and a second shell ST1-2 comprising a second cavity housing the second electronic chip PE 2.

Each housing may have a generally polyhedral shape, for example having a square or rectangular base. Obviously, other shapes for the housings are conceivable, such as a block with trapezoidal base, or a cylinder, each housing comprising an internal cavity defining a cavity suitable for housing at least one electronic chip PE1, PE2, an external surface suitable for supporting an optics wafer PA1, PA2 and at least one open face, joined to the mounting face FM of the base substrate SS.

Fig. 1A, 2A and 3A show more specifically an application example of a "TOF" time-of-flight distance sensor, in which a first electronic chip PE1 and a second electronic chip PE2 operate in pairs. For example, the first electronic chip PE1 emits a signal which is reflected onto a surface outside the device and then detected by the second electronic chip PE2 after reflection. The device may then determine the time elapsed between transmission and reception of the signal and infer the distance separating the device and the external surface accordingly.

The first electronic chip PE1 then integrates an optical emitter, typically a laser diode, and the second electronic chip PE2 integrates an optical detector, typically a photosensitive sensor, associated with the emitter.

Fig. 1A shows an embodiment in which a transparent encapsulation structure includes a first case ST1-1 and a second case ST1-2, the first case ST1-1 and the second case ST1-2 being separated by an intermediate space and bonded to a mounting surface FM of a base substrate SS.

The intermediate space is, for example, a space physically separating the first casing ST1-1 and the second casing ST1-2 in this embodiment.

Typically, the intermediate space is defined by two opposing faces of the first and second housings, which are spaced apart by a distance of the order of 150 to 500 μm (micrometers).

Fig. 1B illustrates a three-dimensional view of a transparent encapsulation structure including a first case ST1-1 and a second case ST1-2, as described above with reference to fig. 1A.

The first casing ST1-1 includes a first planar outer surface forming a support for a first filtered optics wafer PA 1. The first outer surface supporting the optics wafer PA1 is a surface parallel to the mounting surface FM of the base substrate SS, and the first optics wafer PA1 is arranged so as to face the optical element of the first electronic chip PE 1.

The second case ST1-2 includes a second planar outer surface forming a support for the second filtered optics wafer PA 2. The second outer surface supporting the optics wafer PA2 is also a face parallel to the mounting face FM of the base substrate SS, and the second optics wafer PA2 is arranged so as to face the optical element of the second electronic chip PE 2.

Fig. 2A shows a transparent encapsulation structure including a transparent case ST2, the transparent case ST2 including a first chamber and a second chamber separated by an intermediate space and connected by a planar portion on a base substrate SS.

The first cavity accommodates a first electronic chip PE1, and the second cavity accommodates a second electronic chip PE 2.

The flat part of the transparent case ST2 is advantageously positioned in a hollow recess in the mounting face FM of the base substrate SS.

The empty recess in the base SS is deep enough to accommodate the flat portion of the transparent case ST2 completely below the mounting surface FM of the base.

Therefore, these arrangements make it possible to prevent the planar portion of the case ST2 from forming a direct optical path between the optical element of the first electronic chip and the optical element of the second electronic chip.

Fig. 2B shows a three-dimensional view of a transparent encapsulation structure including a transparent case ST2, the transparent case ST2 including two separate chambers connected by a planar portion as described with reference to fig. 2A.

The housing has at least one open face bonded to the mounting face FM of the base substrate SS.

The casing ST2 includes a first recess EV1 and a second recess EV2, each respectively located on an outer surface of each cavity parallel to the mounting surface FM of the base. The first and second recesses EV1 and EV2 are positioned to face the optical elements of the first and second chips PE1 and PE2, respectively. The recess is thus conceived to accommodate the filtering optics wafers PA1, PA2 facing said optical element.

Fig. 3A shows a transparent encapsulation structure including a transparent case ST3, the transparent case ST3 including an inner cavity forming a single chamber housing a first electronic chip PE1 and a second electronic chip PE 2.

Within the cavity, the first and second electronic chips PE1, PE2 are separated by an opaque adhesive volume C3A in a single chamber between the first and second chips PE1, PE 2. The opaque adhesive volume C3A completely prevents the transmission of direct light between the first electronic chip PE1 and the second electronic chip PE 2.

Fig. 3B illustrates a three-dimensional view of a transparent encapsulation structure including a transparent case ST3, and a transparent case ST3 including an inner cavity forming a single chamber, described with reference to fig. 3A.

The case ST3 includes a first recess EV1 on the outer surface of the case facing the optical element of the first electronic chip PE1 and a second recess EV2 on the outer surface of the case facing the optical element of the second electronic chip PE 2.

Fig. 4A, 4B and 4C show embodiments of opaque covers CO4A, CO4B, CO4C-1, CO4C-2, covering the transparent encapsulation structure and opaque partitions C4A, C4B, C4C between the first and second chambers of the transparent encapsulation structure.

The opaque partitions C4A, C4B, C4C block a direct optical path between the first optical element of the first electronic chip PE1 housed in the first chamber and the second optical element of the second electronic chip PE2 housed in the second chamber.

In the case of the application of the "TOF" time-of-flight sensor type, the opaque partition makes it possible to prevent the spurious detection of the signal emitted by the transmitter optical element by the receiver optical element, and this signal is not reflected by the external surface whose presence is sought to be determined.

Furthermore, each opaque cover CO4A, CO4B, CO4C-1, CO4C-2 has a partial opening disposed facing the optics wafer PA1, PA2 supported by the transparent encapsulation structure.

In the embodiment example of fig. 4A and 4B, the transparent encapsulation structure ST2 is arbitrarily selected according to the embodiment example described above with reference to fig. 2A and 2B.

Fig. 4A shows an opaque cover CO4A with an opaque partition C4A inserted into the intermediate space between the first and second chambers. In this example, opaque partition C4A is a component of opaque cover CO4A (i.e., it is integral with opaque cover CO 4A).

Fig. 4B shows an opaque partition C4B formed in the intermediate space between the first and second chambers. An opaque cover CO4B is bonded to the top surface of opaque partition C4B and to mounting surface FM of substrate SS.

Opaque divider CO4B is formed in the intermediate space and molded onto the walls of the encapsulation structure, thereby enabling the formation of opaque divider C4A to be tailored to any particular shape of the encapsulation structure and preventing any alignment issues of the positioning of the opaque divider relative to the lid in the intermediate space.

Obviously, the embodiment example in fig. 4A and 4B may be perfectly applied to the embodiment example of the transparent encapsulation structure described above with reference to fig. 1A and 1B.

FIG. 4C shows opaque lids CO4C-1, CO4C-2 formed by sputtering an opaque material along the outline of the transparent encapsulation structure. In this example, the package structure is formed from two separate housings ST4C-1, ST4C-2, as described above with reference to FIGS. 1A and 1B.

It is assumed that the opaque cover CO4C-1-CO4C-2 is formed by sputtering of an opaque material, which is moulded onto the walls of the packaging structure comprising the two shells, in particular at the level of the intermediate space between the first and second chambers.

Opaque covers CO4C-1, CO4C-2 formed by sputtered material place opaque covers on all outer surfaces of the two separate housings ST4C-1, ST4C-2, thereby making it possible to prevent a direct light path from being formed between the first and second chambers. The opaque partition C4C is formed of the same material and is completely rigidly connected to the opaque covers CO4C-1, CO 4C-2.

This embodiment example of the opaque covers CO4C-1, CO4C-2 may obviously be applied to the embodiment example of the transparent encapsulation structure described with reference to fig. 2A, 2B, 3A and 3B.

Fig. 5 shows the steps of producing or assembling an electronic device as described above with reference to fig. 1A to 4C.

During step R1 before assembling the electronic device, a transparent encapsulation structure as described above with reference to fig. 1A to 3B is manufactured. For example, the manufacture of the transparent encapsulation structure comprises the injection of a transparent plastic material into a mould provided for this purpose.

The first step S1 includes fastening the optical element-integrated electronic chip to the mounting surface of the base substrate.

The fastening of an electronic chip usually involves soldering the solder balls envisaged on the electronic chip to the soldering surface of the base substrate which receives the solder balls, or indeed joining the electronic chip, and the electrical connection of the electronic chip to the solder lines drawn between the solder plate of the chip and the soldering surface of the base substrate.

In a second step S2, a transparent package structure including one or more cavities on the mounting face FM of the substrate is bonded such that each cavity of the package structure accommodates an electronic chip.

In a third step S3, a filtered optics wafer PA1, PA2 is mounted on the transparent encapsulation structure facing each optical element. For example, the optical wafer is wedged and/or bonded in a hollow front recess on the outer surface of the package structure, or bonded to a planar outer surface of the package structure.

A fourth step S4 includes covering the encapsulation structure with an opaque cover such that the partial opening of the opaque cover is positioned facing each optical element and opaque dividers are placed between the chambers of the same encapsulation structure.

To manufacture the device as described with reference to fig. 4B, step S4 includes placing an opaque partition C4B in the intermediate space between the first and second chambers of the same housing ST2, then disposing an adhesive volume G4B on the top surface of the opaque partition C4B, and finally covering the encapsulation and top structures of the opaque partition C4B with an opaque cover CO 4B.

To manufacture the device as described with reference to fig. 4C, step S4 includes sputtering opaque materials CO4C-1, CO4C-2 such that the outer surface of the encapsulation structure is covered by the same opaque material, thereby simultaneously forming opaque covers CO4C-1, CO4C-2 and opaque partition C4C.

Claims

1. An electronic device, comprising:

a base substrate having a mounting surface,

at least one electronic chip having a back surface and a front surface, the back surface being secured to the mounting surface of the base substrate, the front surface integrating an optical element;

a transparent encapsulation structure bonded to the base substrate, the transparent encapsulation structure comprising at least one housing including an interior cavity defining a cavity containing the at least one electronic chip;

a filtering optics die supported by and on an outer surface of the package structure and facing each optical element; and

an opaque cover covering the transparent encapsulation structure and the filter optics die, the opaque cover including a partial opening exposing at least a portion of the filter optics die.

2. The apparatus of claim 1, wherein the transparent encapsulation structure is provided with a hollow front recess on the outer surface of the encapsulation structure facing each optical element, wherein the filtering optics die is mounted within the hollow front recess.

3. The device of claim 1, wherein the at least one electronic chip comprises a first electronic chip and a second electronic chip, and further comprising an opaque separator between the first electronic chip and the second electronic chip.

4. The apparatus of claim 3, wherein the at least one housing is formed from a single transparent housing defining a single chamber that houses both the first and second electronic chips, and wherein the opaque partition comprises an opaque volume located inside the single chamber.

5. The apparatus of claim 4, wherein the opaque volume is made of an adhesive material.

6. The apparatus of claim 3, wherein the at least one housing comprises: a first transparent housing defining a first chamber housing the first electronic chip; and a second transparent housing defining a second chamber housing the second electronic chip, and wherein the opaque partition occupies an intermediate space outside of the first and second chambers between the first and second chambers.

7. The apparatus of claim 3, wherein the at least one housing comprises a single transparent housing defining a first chamber containing the first electronic chip and a second chamber containing the second electronic chip, and wherein the opaque partition occupies an intermediate space between the first chamber and the second chamber outside of the first chamber and the second chamber.

8. The apparatus of claim 7, wherein the single transparent housing comprises a planar portion connecting the first and second chambers and located on the base substrate.

9. The apparatus of claim 8, wherein the base substrate includes a hollow recess in the mounting face of the base substrate, and wherein the planar portion of the single transparent housing is mounted within the recess.

10. The apparatus of claim 7, wherein the opaque cover incorporates the opaque partition in the intermediate space.

11. The apparatus of claim 7, wherein the opaque divider completely fills the intermediate space.

12. The apparatus of claim 11, wherein the opaque cover is joined to a free top surface of the opaque divider.

13. The apparatus of claim 7, wherein the opaque cover and the opaque divider are made of an opaque material sputtered onto the outer surface of the transparent encapsulation structure.

14. The device of claim 3, wherein the optical element integrated in the first electronic chip comprises a radiation emitter, and wherein the optical element integrated in the second electronic chip comprises a radiation receiver configured to receive radiation emitted by the radiation emitter after reflection from an element external to the opaque cover.