CN214624389U

CN214624389U - Display panel and display device

Info

Publication number: CN214624389U
Application number: CN202120051225.5U
Authority: CN
Inventors: 赖青俊; 朱绎桦
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2021-01-08
Filing date: 2021-01-08
Publication date: 2021-11-05
Anticipated expiration: 2031-01-08

Abstract

The utility model discloses a display panel and display device relates to and shows technical field, and display panel includes: the driving circuit comprises N stages of shift registers which are mutually cascaded, wherein N is more than or equal to 2; the shift register includes: a first control unit; a second control unit; a third control unit; a fourth control unit for receiving the third voltage signal and the fourth voltage signal and generating an output signal in response to the signal of the second node and the signal of the fourth node; the third voltage signal is a high level signal, and the fourth voltage signal is a low level signal; the potential of the first voltage signal is higher than the potential of the third voltage signal, and/or the potential of the second voltage signal is lower than the potential of the fourth voltage signal. The utility model provides an among the prior art shift register can not satisfy the problem of pixel circuit to the different voltage demands of different signals.

Description

Display panel and display device

Technical Field

The utility model relates to a show technical field, more specifically relates to a display panel and display device.

Background

At present, display technology is widely applied to television, mobile phone and public information display, and brings great convenience to daily life and work of people. In the prior art, a scan driving circuit is required to be used in a display panel for displaying a picture to provide a driving signal for a pixel circuit so as to control the display panel to implement a function of scanning, so that image data input to the display panel can be refreshed in real time, thereby implementing dynamic display.

However, the conventional scan driving circuit cannot meet the different voltage requirements of the pixel circuit for different signals.

SUMMERY OF THE UTILITY MODEL

In view of this, the utility model provides a display panel and display device to solve the problem that shift register can not satisfy the different voltage demands of pixel circuit to different signals among the prior art.

The utility model provides a display panel, include: the driving circuit comprises N stages of shift registers which are mutually cascaded, wherein N is more than or equal to 2; the shift register includes: a first control unit for receiving an input signal and controlling a signal of the first node in response to a first clock signal; a second control unit for receiving the first voltage signal and the second voltage signal and controlling a signal of a second node in response to a signal of the first node, the first clock signal, and the second clock signal; a third control unit, configured to receive the first voltage signal and the second voltage signal, and control a signal of a fourth node in response to a signal of a second node and a signal of a third node, where the third node is connected to the first node, the first voltage signal is a high-level signal, and the second voltage signal is a low-level signal; a fourth control unit for receiving the third voltage signal and the fourth voltage signal and generating an output signal in response to the signal of the second node and the signal of the fourth node; the third voltage signal is a high level signal, and the fourth voltage signal is a low level signal; the potential of the first voltage signal is higher than the potential of the third voltage signal, and/or the potential of the second voltage signal is lower than the potential of the fourth voltage signal.

Based on same thought, the utility model also provides a display device, this display device includes above-mentioned display panel.

Compared with the prior art, the utility model provides a display panel and display device has realized following beneficial effect at least:

the utility model provides an among the display panel, through first the control unit, second the control unit and third the control unit based on input signal, first clock signal, the second clock signal, the signal of first voltage signal and second voltage signal control second node and the signal of fourth node, the fourth the control unit is used for receiving third voltage signal and fourth voltage signal, and respond to first the control unit, the signal of the second node that second the control unit and third the control unit controlled and the signal of fourth node, produce output signal, first the control unit promptly, second the control unit and third the control unit are control part in the shift register, play the control action. The fourth control unit is an output part in the shift register and is used for generating an output signal. The voltage signals (the third voltage signal and the fourth voltage signal) received by the fourth control unit and the voltage signals (the first voltage signal and the second voltage signal) received by the first control unit, the second control unit and the third control unit are separately arranged, that is, the voltage signal of the control part and the voltage signal of the output part in the shift register are separately arranged, so that the voltage signal received by the fourth control unit can be arranged according to the requirements of the pixel circuit in the display panel for different signals, the required signals can be selectively output, and the flexibility of the signals output by the driving circuit is improved.

Further, since the potential of the first voltage signal is higher than the potential of the third voltage signal and/or the potential of the second voltage signal is lower than the potential of the fourth voltage signal, the waveform stability of the output signal generated by the fourth control unit can be improved, thereby improving the stability of the output signal of the driving circuit.

Of course, it is not necessary for any product to achieve all of the above-described technical effects simultaneously.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic plan view of a display panel provided by the present invention;

fig. 2 is a schematic structural diagram of a driving circuit provided by the present invention;

fig. 3 is a schematic diagram of a frame structure of a shift register according to the present invention;

fig. 4 is a schematic circuit diagram of a shift register according to the present invention;

fig. 5 is a schematic circuit diagram of another shift register provided by the present invention;

fig. 6 is a schematic circuit diagram of another shift register provided by the present invention;

fig. 7 is a schematic circuit diagram of another shift register provided by the present invention;

fig. 8 is a schematic circuit diagram of another shift register provided by the present invention;

fig. 9 is a schematic circuit diagram of another shift register provided by the present invention;

fig. 10 is a schematic circuit diagram of another shift register provided by the present invention;

fig. 11 is a schematic circuit diagram of another shift register provided by the present invention;

fig. 12 is a timing diagram of driving the shift register according to the present invention;

fig. 13 is another driving timing diagram of the shift register according to the present invention;

fig. 14 is a schematic structural diagram of another driving circuit provided by the present invention;

fig. 15 is a schematic structural diagram of another driving circuit provided by the present invention;

fig. 16 is a circuit schematic diagram of a pixel circuit provided in the present invention;

fig. 17 is a circuit schematic diagram of another pixel circuit provided by the present invention;

fig. 18 is a schematic plan view of another display panel provided by the present invention;

fig. 19 is a schematic plan view of another display panel provided by the present invention;

fig. 20 is a schematic plan view of a display device according to the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: unless specifically stated otherwise, the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present invention.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

Fig. 1 is a schematic plan view of a display panel provided by the present invention, referring to fig. 1, the present embodiment provides a display panel, including: a driving circuit 100 and a plurality of pixels 200, each pixel 200 having a pixel circuit 210 disposed therein. The driving circuit 100 is connected to the pixel circuit 210 via a signal line, and supplies a driving signal to the pixel circuit 210, so that the pixel circuit 210 drives the pixel 200 to emit light, thereby displaying a screen.

It should be noted that fig. 1 illustrates only one structure of the display panel as an example, and fig. 1 illustrates that the driving circuit 200 is located on one side of the display panel, in other embodiments of the present invention, the driving circuit 200 may also be located on two sides of the display panel, which is not described herein again.

Fig. 2 is a schematic structural diagram of a driving circuit provided by the present invention, fig. 3 is a schematic structural diagram of a frame of a shift register provided by the present invention, referring to fig. 2 and fig. 3, in an embodiment of the present invention, the driving circuit 100 in the display panel includes N-stage shift registers 110 that are cascaded with each other, where N is greater than or equal to 2;

the shift register 110 in the driving circuit 100 includes a first control unit 10, a second control unit 20, a third control unit 30, and a fourth control unit 40.

Wherein, the first control unit 10 is configured to receive an input signal IN and control a signal of a first node N1 IN response to a first clock signal CK;

the second control unit 20 is configured to receive the first voltage signal VGH1 and the second voltage signal VGL1, and control a signal of the second node N2 in response to the signal of the first node N1, the first clock signal CK, and the second clock signal XCK;

the third control unit 30 is configured to receive a first voltage signal VGH1 and a second voltage signal VGL1, and control a signal of a fourth node N4 in response to a signal of a second node N2 and a signal of a third node N3, wherein the third node N3 is connected to the first node N1, the first voltage signal VGH1 is a high level signal, and the second voltage signal VGL1 is a low level signal;

the fourth control unit 40 is configured to receive the third voltage signal VGH2 and the fourth voltage signal VGL2, and generate an output signal OUT in response to the signal of the second node N2 and the signal of the fourth node N4; the third voltage signal VGH2 is a high level signal, and the fourth voltage signal VGL2 is a low level signal; the first voltage signal VGH1 has a higher potential than the third voltage signal VGH2, and/or the second voltage signal VGL1 has a lower potential than the fourth voltage signal VGL 2.

Specifically, IN the embodiment of the present invention, the first control unit 10, the second control unit 20 and the third control unit 30 control the signal of the second node N2 and the signal of the fourth node N4 based on the input signal IN, the first clock signal CK, the second clock signal XCK, the first voltage signal VGH1 and the second voltage signal VGL1, and the fourth control unit 40 is configured to receive the third voltage signal VGH2 and the fourth voltage signal VGL2, and generate the output signal OUT IN response to the signal of the second node N2 and the signal of the fourth node N4 controlled by the first control unit 10, the second control unit 20 and the third control unit 30, that is, the first control unit 10, the second control unit 20 and the third control unit 30 are control portions IN the shift register 110, and perform a control function. The fourth control unit 40 is an output part of the shift register 110 for generating an output signal. The voltage signals (the third voltage signal VGH2 and the fourth voltage signal VGL2) received by the fourth control unit 40 and the voltage signals (the first voltage signal VGH1 and the second voltage signal VGL1) received by the first control unit 10, the second control unit 20 and the third control unit 30 are set separately, that is, the voltage signal of the control part in the shift register 110 and the voltage signal of the output part are set separately, so that the voltage signal received by the fourth control unit 40 can be set according to the requirements of the pixel circuits in the display panel for different signals, the required signals can be selectively output, and the flexibility of the signals output by the driving circuit 100 is improved.

Also, since the first voltage signal VGH1 has a higher potential than the third voltage signal VGH2 and/or the second voltage signal VGL1 has a lower potential than the fourth voltage signal VGL2, the waveform stability of the output signal OUT generated by the fourth control unit 40 can be improved, thereby improving the stability of the output signal of the driving circuit 100.

Fig. 4 is a circuit schematic diagram of a shift register according to the present invention, referring to fig. 4, optionally, wherein the fourth control unit 40 includes a first transistor M1 and a second transistor M2;

the first transistor M1 receives the third voltage signal VGH2, and the second transistor M2 receives the fourth voltage signal VGL2 to generate the output signal OUT.

Specifically, the fourth control unit 40 includes a first transistor M1 and a second transistor M2, the first transistor M1 receives the third voltage signal VGH2, the second transistor M2 receives the fourth voltage signal VGL2, and generates an output signal OUT, which is controlled by the first transistor M1 and the second transistor M2, respectively, and is the third voltage signal VGH2 when the first transistor M1 is turned on, and is the fourth voltage signal VGL2 when the second transistor M2 is turned on.

With continued reference to fig. 4, optionally, wherein the first transistor M1 and the second transistor M2 are both PMOS transistors;

the source of the first transistor M1 is connected to the third voltage signal VGH2, the drain is connected to the output signal OUT, and the gate is connected to the fourth node N4;

the second transistor M2 has a source connected to the fourth voltage signal VGL2, a drain connected to the output signal OUT, and a gate connected to the second node N2.

Specifically, when the fourth node N4 is at a low level, the first transistor M1 is turned on, and the third voltage signal VGH2 is transmitted to the drain of the first transistor M1, generating the output signal OUT. When the fourth node N4 is at a high level, the first transistor M1 is turned off. When the second node N2 is at a low level, the second transistor M2 is turned on, and the fourth voltage signal VGL2 is transmitted to the drain of the second transistor M2, generating the output signal OUT. When the second node N2 is at a high level, the second transistor M2 is turned off. That is, the high level of the output signal OUT is determined by the fourth node N4, and the low level of the output signal OUT is determined by the second node N2.

Fig. 5 is a circuit schematic diagram of another shift register according to the present invention, referring to fig. 5, optionally, wherein the first transistor M1 and the second transistor M2 are both NMOS transistors;

the source of the first transistor M1 is connected to the third voltage signal VGH2, the drain is connected to the output signal OUT, and the gate is connected to the second node N2;

the second transistor M2 has a source connected to the fourth voltage signal VGL2, a drain connected to the output signal OUT, and a gate connected to the fourth node N4.

Specifically, when the second node N2 is low, the first transistor M1 is turned off. When the second node N2 is at a high level, the first transistor M1 is turned on, and the third voltage signal VGH2 is transmitted to the drain of the first transistor M1, generating the output signal OUT. When the fourth node N4 is at a low level, the second transistor M2 is turned off. When the fourth node N4 is at a high level, the second transistor M2 is turned on, and the fourth voltage signal VGL2 is transmitted to the drain of the second transistor M2, generating the output signal OUT. That is, the high level of the output signal OUT is determined by the second node N2, and the low level of the output signal OUT is determined by the fourth node N4.

Fig. 6 is a circuit schematic diagram of another shift register according to the present invention, referring to fig. 6, optionally, wherein the first transistor M1 and the second transistor M2 are both PMOS transistors;

Specifically, when the second node N2 is at a low level, the first transistor M1 is turned on, and the third voltage signal VGH2 is transmitted to the drain of the first transistor M1, generating the output signal OUT. When the second node N2 is at a high level, the first transistor M1 is turned off. When the fourth node N4 is at a low level, the second transistor M2 is turned on, and the fourth voltage signal VGL2 is transmitted to the drain of the second transistor M2, generating the output signal OUT. When the fourth node N4 is at a high level, the second transistor M2 is turned off. That is, the high level of the output signal OUT is determined by the second node N2, and the low level of the output signal OUT is determined by the fourth node N4.

Fig. 7 is a circuit schematic diagram of another shift register according to the present invention, referring to fig. 7, optionally, wherein the first transistor M1 and the second transistor M2 are both NMOS transistors;

Specifically, when the fourth node N4 is at a low level, the first transistor M1 is turned off. When the fourth node N4 is at a high level, the first transistor M1 is turned on, and the third voltage signal VGH2 is transmitted to the drain of the first transistor M1, generating the output signal OUT. When the second node N2 is at a low level, the second transistor M2 is turned off. When the second node N2 is at a high level, the second transistor M2 is turned on, and the fourth voltage signal VGL2 is transmitted to the drain of the second transistor M2, generating the output signal OUT. That is, the high level of the output signal OUT is determined by the fourth node N4, and the low level of the output signal OUT is determined by the second node N2.

On the basis of any of the above embodiments, in some embodiments of the present invention, in order to ensure the stability of the potentials of the second node N2 and the fourth node N4 and ensure the stability of the output signal OUT, optionally, the fourth control unit 40 further includes a first capacitor C1 and a second capacitor C2.

Fig. 8 is a circuit schematic diagram of another shift register according to the present invention, referring to fig. 8, a first plate of a first capacitor C1 is connected to a second voltage signal VGL1, and a second plate of the first capacitor C1 is connected to a fourth node N4. The first plate of the second capacitor C2 is connected to the second node N2, and the second plate of the second capacitor C2 is connected to the fourth voltage signal VGL 2.

Fig. 9 is a schematic circuit diagram of another shift register according to the present invention, referring to fig. 9, a first plate of a first capacitor C1 is connected to a second voltage signal VGL1, and a second plate of the first capacitor C1 is connected to a fourth node N4. The first plate of the second capacitor C2 is connected to the second node N2, and the second plate of the second capacitor C2 is connected to the third voltage signal VGH 2.

Fig. 10 is a circuit schematic diagram of another shift register according to the present invention, referring to fig. 9 and 10, a first plate of a first capacitor C1 is connected to a second voltage signal VGL1, and a second plate of the first capacitor C1 is connected to a fourth node N4. The first plate of the second capacitor C2 is connected to the second node N2, and the second plate of the second capacitor C2 is connected to the third voltage signal VGH 2.

Fig. 11 is a circuit schematic diagram of another shift register according to the present invention, referring to fig. 11, a first plate of a first capacitor C1 is connected to a second voltage signal VGL1, and a second plate of the first capacitor C1 is connected to a fourth node N4. The first plate of the second capacitor C2 is connected to the second node N2, and the second plate of the second capacitor C2 is connected to the fourth voltage signal VGL 2.

In other embodiments of the present application, the second plate of the first capacitor C1 is connected to the fourth node N4, the connection manner of the first plate of the first capacitor C1 is adjustable, the first plate is connected to one of the first voltage signal VGH1, the second voltage signal VGL1, the third voltage signal VGH2, the fourth voltage signal VGL2 and the output signal OUT, and the potential of the fourth node N4 is stabilized by a fixed potential or an output signal.

The first plate of the second capacitor C2 is connected to the second node N2, the second plate of the second capacitor C2 is connected in an adjustable manner, the second plate is connected to one of the first voltage signal VGH1, the second voltage signal VGL1, the third voltage signal VGH2, the fourth voltage signal VGL2 and the output signal OUT, and the potential of the second node N2 is stabilized by a fixed potential or an output signal.

On the basis of any of the above embodiments, as shown in fig. 8 to 11, optionally, the first control unit 10 includes: the fifth transistor M5 has a source connected to the input signal IN, a drain connected to the first node N1, and a gate connected to the first clock signal CK, and the fifth transistor M5.

The second control unit 20 includes: a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a fifth capacitor C5, wherein the source of the sixth transistor M6 is connected to the first node N1, the drain of the sixth transistor M6 is connected to the drain of the seventh transistor M7, and the gate of the sixth transistor M6 is connected to the second clock signal XCK; the source of the seventh transistor M7 is connected to the first voltage signal VGH1, the drain is connected to the drain of the sixth transistor M6, and the gate is connected to the fifth node N5; the eighth transistor M8 has a source connected to the first clock signal CK, a drain connected to the fifth node N5, and a gate connected to the first node N1; the ninth transistor M9 has a source connected to the second clock signal XCK, a drain connected to the fifth node N5, and a gate connected to the first clock signal CK; a source of the tenth transistor M10 is connected to the second clock signal XCK, a drain thereof is connected to the sixth node N6, and a gate thereof is connected to the fifth node N5; the eleventh transistor M11 has a source connected to the sixth node N6, a drain connected to the second node N2, and a gate connected to the second clock signal XCK; the source of the twelfth transistor M12 is connected to the first voltage signal VGH1, the drain is connected to the second node N2, and the gate is connected to the third node N3; a first pole of the fifth capacitor C5 is connected to the fifth node N5, and a second pole of the fifth capacitor C5 is connected to the sixth node N6.

On the basis of any of the above embodiments, as shown in fig. 8 to 11, optionally, the second control unit 20 further includes a thirteenth transistor M13 and a fourteenth transistor M14.

A source of the thirteenth transistor M13 is connected to the fifth node N5, a drain of the thirteenth transistor M13 is connected to the gate of the tenth transistor M10, and a gate of the thirteenth transistor M13 is connected to the second voltage signal VGL 1; the source of the fourteenth transistor M14 is connected to the first node N1, the drain is connected to the third node N3, and the gate is connected to the second voltage signal VGL 1.

On the basis of any of the above embodiments, as shown in fig. 8 to 11, optionally, the third control unit 30 includes a third transistor M3 and a fourth transistor M4.

The source of the third transistor M3 is connected to the first voltage signal VGH1, the drain is connected to the fourth node N4, and the gate is connected to the second node N2; the fourth transistor M4 has a source connected to the second voltage signal VGL1, a drain connected to the fourth node N4, and a gate connected to the third node N3.

Since the first transistor M1 and the second transistor M2 are output transistors, in order to ensure the stability of the output signal OUT, the requirement on the output performance of the first transistor M1 and the second transistor M2 is higher, and therefore, in some embodiments of the present invention, in order to improve the output performance of the first transistor M1 and the second transistor M2, the width-to-length ratio of the channel region of the first transistor M1 is greater than the width-to-length ratio of the channel region of the third transistor M3, and/or the width-to-length ratio of the channel region of the second transistor M2 is greater than the width-to-length ratio of the channel region of the fourth transistor M4.

On the basis of any of the above embodiments, as shown in fig. 8 to 11, optionally, the third control unit 30 further includes a third capacitor C3 and a fourth capacitor C4.

A first plate of the third capacitor C3 is connected to the first voltage signal VGH1, and a second plate of the third capacitor C3 is connected to the second node N2; a first plate of the fourth capacitor C4 is connected to the second clock signal XCK or the second voltage signal VGL1, and a second plate of the fourth capacitor C4 is connected to the third node N3.

Since the first capacitor C1 and the second capacitor C2 are used to stabilize the potentials of the second node N2 and the fourth node N4 and further stabilize the output signal OUT, the capacitances of the first capacitor C1 and the second capacitor C2 need to be large enough to ensure that the potentials of the second node N2 and the fourth node N4 do not fluctuate easily.

Based on this, in some embodiments of the present invention, the capacitance values of the first capacitor C1 and the second capacitor C2 are greater than the capacitance value of the third capacitor C3 and greater than the capacitance value of the fourth capacitor C4. Of course, the present invention is not limited thereto, and in other embodiments, in order to simplify the manufacturing process, the capacitance of the first capacitor C1, the capacitance of the second capacitor C2, the capacitance of the third capacitor C3 and the capacitance of the fourth capacitor C4 may be equal.

Optionally, in other embodiments of the present invention, in order to ensure the stability of the potentials of the second node N2 and the fourth node N4, the capacitance of the fifth capacitor C5 may be smaller than the capacitance of the first capacitor C1, and smaller than the capacitance of the second capacitor C2. And since the stability of the second node N2 and the fourth node N4 may affect the stability of the output signal OUT, and the stability of the fifth node N5 has little influence on the stability of the output signal OUT, the fifth capacitor C5 may be set to be smaller to save space.

Optionally, in other embodiments of the present invention, the capacitance of the fifth capacitor C5 is smaller than the capacitance of the third capacitor C3, and is smaller than the capacitance of the fourth capacitor C4. The fifth capacitor C5 may be further smaller to save space.

The operation of the shift register of the present invention will be described with reference to the timing diagram of each signal in the shift register.

Fig. 12 is a timing diagram of a shift register according to the present invention, please refer to fig. 8 and fig. 12.

At the stage of T1, the input signal IN is at a high level, the first clock signal CK is at a low level, the fifth transistor M5 is turned on, the input signal IN is transmitted to the first node N1, such that the first node N1 is at a high level, the ninth transistor M9 is turned on, the second voltage signal VGL1 is transmitted to the fifth node N5, such that the fifth node N5 is at a low level, the tenth transistor M10 is turned on, the second clock signal XCK is at a high level, the sixth node N6 is kept at a high level, the sixth transistor M6 is turned off, the eleventh transistor M11 is turned off, the twelfth transistor M12 is turned off, the second node N2 is kept at a high level, the second transistor M2 is turned off, the third transistor M3 is turned off, the third node N3 is kept at a high level, the fourth transistor M4 is turned off, the fourth node N4 is kept at a low level, the first transistor M1 is turned on, the third voltage VGH signal CK is transmitted to the output terminal 2, such that the output signal OUT is at a high level.

IN a stage T2, the input signal IN is at a high level, the first clock signal CK is at a high level, the fifth transistor M5 is turned off, the ninth transistor M9 is turned off, the first node N1 is at a high level, the second clock signal XCK is at a low level, the sixth transistor M6 is turned on, the eighth transistor M8 is turned off, the fifth node N5 is at a low level, the tenth transistor M10 is turned on, the second clock signal XCK is transmitted to the sixth node N6, the sixth node N6 is at a low level, the eleventh transistor M11 is turned on, the signal of the sixth node N6 is transmitted to the second node N2, the second node N2 is at a low level, the third transistor M3 is turned on, the first voltage signal VGH1 is transmitted to the fourth node N4, the fourth node N4 is at a high level, the first transistor M1 is turned off, the second transistor M2 is turned on, the fourth voltage signal VGL2 is transmitted to the output terminal OUT, and the output signal OUT is at a low level.

IN a stage T3, the input signal IN is at a high level, the first clock signal CK is at a low level, the fifth transistor M5 is turned on, the input signal IN is transmitted to the first node N1, so that the first node N1 is at a high level, the ninth transistor M9 is turned on, the second voltage signal VGL1 is transmitted to the fifth node N5, so that the fifth node N5 is at a low level, the tenth transistor M10 is turned on, the second clock signal XCK is at a high level, the sixth node N6 is kept at a high level, the sixth transistor M6 is turned off, the eleventh transistor M11 is turned off, the twelfth transistor M12 is turned off, the third transistor M3 is turned off, the third node N3 is kept at a high level, the fourth transistor M4 is turned off, the fourth node N4 is kept at a high level, the first transistor M1 is turned off, the second node N2 is kept at a low level, the third transistor M2 is turned on, and the fourth voltage VGL2 is transmitted to the output terminal OUT, so that the output signal OUT is at a low level.

IN a stage T4, the input signal IN is at a low level, the first clock signal CK is at a high level, the fifth transistor M5 is turned off, the ninth transistor M9 is turned off, the first node N1 is kept at a high level, the second clock signal XCK is at a low level, the sixth transistor M6 is turned on, the eighth transistor M8 is turned off, the fifth node N5 is kept at a low level, the tenth transistor M10 is turned on, the second clock signal XCK is transmitted to the sixth node N6, the sixth node N6 is at a low level, the eleventh transistor M11 is turned on, the signal of the sixth node N6 is transmitted to the second node N2, the second node N2 is at a low level, the third transistor M3 is turned on, the first voltage signal VGH1 is transmitted to the fourth node N4, the fourth node N4 is at a high level, the first transistor M1 is turned off, the second transistor M2 is turned on, the fourth voltage signal VGL2 is transmitted to the output terminal OUT, and the output signal is at a low level.

IN the period T5, the input signal IN is low level, the first clock signal CK is low level, the fifth transistor M5 is turned on, the input signal IN is transmitted to the first node N1, so that the first node N1 is low level, the ninth transistor M9 is turned on, the second voltage signal VGL1 is transmitted to the fifth node N5, so that the fifth node N5 is low level, the tenth transistor M10 is turned on, the second clock signal XCK is high level, the sixth node N6 is kept high level, the sixth transistor M6 is turned off, the eleventh transistor M11 is turned off, the first node N1 controls the twelfth transistor M12 to be turned on, the first voltage signal VGH1 is transmitted to the second node N2, so that the second node N2 is high level, the third transistor M3 is turned off, the second transistor M2 is turned off, the fourteenth transistor M14 is turned on, the signal of the first node N1 is transmitted to the third node N3, the third node N867 is turned on, the fourth node N3687458 is controlled by the fourth node N4, the second voltage signal VGL1 is transmitted to the fourth node N4, such that the fourth node N4 is low, the first transistor M1 is turned on, and the third voltage signal VGH2 is transmitted to the output terminal, such that the output signal OUT is high.

In the shift register shown in fig. 9, although the types of the first transistor M1 and the second transistor M2 are different from the types of the first transistor M1 and the second transistor M2 in the shift register shown in fig. 8, the levels of the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5 are the same as the above-described process from the stage T1 to the stage T5, the voltage signal input to the first transistor M1 in fig. 9 is different from the voltage signal input to the first transistor M1 in fig. 8, the voltage signal input to the second transistor M2 in fig. 9 is different from the voltage signal input to the second transistor M2 in fig. 8, and thus the level of the output signal OUT in fig. 9 is the same as the level of the output signal OUT in fig. 8. That is, the timing chart of signals at each node in the shift register shown in fig. 9 is also shown in fig. 12.

In the shift register shown in fig. 10, only the connection node of the first transistor M1 and the second transistor M2 is different from the connection node shown in fig. 8, and therefore, the levels of the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5 are the same as the above-described process from the T1 stage to the T5 stage, and are different only in the level of the output signal OUT. As shown in fig. 12, the level change state of the output signal OUT is the same as that of the second node N2. Fig. 13 is another driving timing diagram of the shift register according to the present invention, please refer to fig. 10 and 13, in which the level variation state of the output signal OUT is the same as the level variation state of the fourth node N4.

In the shift register shown in fig. 11, although the types of the first transistor M1 and the second transistor M2 are different from the types of the first transistor M1 and the second transistor M2 in the shift register shown in fig. 10, the levels of the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5 are the same as the above-described process from the stage T1 to the stage T5, the voltage signal input to the first transistor M1 in fig. 11 is different from the voltage signal input to the first transistor M1 in fig. 10, the voltage signal input to the second transistor M2 in fig. 11 is different from the voltage signal input to the second transistor M2 in fig. 10, and thus the level of the output signal OUT in fig. 11 is the same as the level of the output signal OUT in fig. 10. That is, the timing chart of signals at each node in the shift register shown in fig. 11 is also shown in fig. 13.

It should be noted that, since the first transistor M1 and the second transistor M2 respectively generate the output signal OUT under the control of the fourth node N4 and the second node N2, and the high level signal and the low level signal of the second node N2 and the fourth node N4 are the first voltage signal VGH1 and the second voltage signal VGL1 respectively, that is, the control signal of the fourth control unit 40 is the first voltage signal VGH1 and the second voltage signal VGL1, and the receiving signal of the fourth control unit 40 is the third voltage signal VGH2 and the fourth voltage signal VGL2, when the potential of the first voltage signal VGH1 is higher than the potential of the third voltage signal VGH2, and/or the potential of the second voltage signal VGL1 is lower than the potential of the fourth voltage signal VGL2, the control signal of the fourth control unit 40 can be made to have a higher level or a lower level than the receiving signal.

When the first transistor M1 and the second transistor M2 are PMOS transistors, when receiving a low level, and the level of the control signal is lower than that of the received low level signal, the PMOS transistors can be ensured to work in a more saturated state, so that the stability of the output signal OUT is ensured, and the tailing phenomenon of signal output is reduced. In addition, when control signal is higher high level, when the level that if the PMOS transistor was received also was high level, the transistor that can fully guarantee the PMOS was closed, fully reduced the risk of electric leakage, consequently, the embodiment of the utility model provides an in, can fully promote the stability of output waveform, avoid the emergence of trailing and leakage current scheduling problem.

Similarly, when the first transistor M1 and the second transistor M2 are NMOS transistors, when receiving a high level, and the level of the control signal is higher than that of the received high level signal, the NMOS transistors can be ensured to operate in a more saturated state, so that the stability of the output signal OUT is ensured, and the tailing phenomenon of signal output is reduced. In addition, when control signal is lower low level, when the level that if the NMOS transistor was received also was low level, can fully guarantee that the NMOS transistor closes, fully reduces the risk of electric leakage, consequently, the embodiment of the utility model provides an in, can fully promote the stability of output waveform, avoid the emergence of tailing and leakage current scheduling problem.

On the basis of the shift registers shown in fig. 8 and 10, optionally, the width-to-length ratio of the channel region of the second transistor M2 is greater than or equal to the width-to-length ratio of the channel region of the first transistor M1.

Specifically, since the second transistor M2 is a transistor connected to the fourth voltage signal VGL2, when the fourth voltage signal VGL2 is transmitted to the output terminal, so that the output signal OUT is at a low level, the potential of the second node N2 is at a low potential, and when the source and the gate of the PMOS transistor are at the same low potential, in order to ensure the stability of the output signal OUT, which is a low-level signal output by the PMOS transistor, the output capability of the PMOS transistor needs to be improved as much as possible, and since the larger the width-to-length ratio of the channel region of the PMOS transistor, the stronger the output capability of the PMOS transistor is, the larger the width-to-length ratio of the channel region of the PMOS transistor needs to be appropriately increased.

The third voltage signal VGH2 connected to the first transistor M1 is a high level signal, and when the fourth node N4 is a low level, the PMOS transistor operates in a more saturated state and is fully turned on, so that the requirement for the output capability is smaller than that of the second transistor M2, and the aspect ratio can be set to be smaller.

Based on this, in some embodiments of the present invention, the width-to-length ratio of the channel region of the second transistor M2 may be greater than the width-to-length ratio of the channel region of the first transistor M1, and similarly, in order to simplify the manufacturing process, the width-to-length ratio of the channel region of the second transistor M2 may also be equal to the width-to-length ratio of the channel region of the first transistor M1.

Of course, on the basis of the shift registers shown in fig. 9 and fig. 11, in some embodiments of the present invention, the width-to-length ratio of the channel region of the second transistor M2 may also be greater than or equal to the width-to-length ratio of the channel region of the first transistor M1, for reasons similar to those described above, and will not be described herein again.

On the basis of the shift register shown in fig. 8, optionally, the capacitance value of the first capacitor C1 is smaller than or equal to the capacitance value of the second capacitor C2.

Since the second plate of the second capacitor C2 is connected to the fourth voltage signal VGL2, the first plate of the second capacitor C2 is connected to the second node N2, the source of the second transistor M2 is connected to the fourth voltage signal VGL2, and the gate is connected to the second node N2, when the second transistor M2 is a PMOS transistor, the output of the second transistor M2 is unstable when the second node N2 is a low-level signal. By increasing the capacitance of the second capacitor C2, the stability of the potential at the second node N2 can be improved. At this time, the capacitance value of the first capacitor C1 may be set to be smaller than that of the second capacitor C2. Of course, in order to simplify the manufacturing process, the capacitance of the first capacitor C1 may be equal to the capacitance of the second capacitor C2.

On the basis of the shift registers shown in fig. 9-11, in some embodiments of the present invention, the capacitance value of the first capacitor C1 may also be less than or equal to the capacitance value of the second capacitor C2, which is not described herein again.

With continuing reference to fig. 1, 2 and 8, optionally, the driver circuit includes N stages of shift registers, i.e., N cascaded shift registers ASG1 through ASGN. In the N-stage shift register of the driving circuit, a signal of a fourth node N4 of the Mth-stage shift register is connected to an input signal end of the M + 1-stage shift register to be used as an input signal of the M + 1-stage shift register, wherein M is more than or equal to 1 and less than or equal to N.

Specifically, IN the driving circuit, the signal Next at the fourth node N4 of the previous stage shift register is used as the input signal IN of the Next stage shift register, and the output signal OUT of each stage shift register is used as the driving signal to be input to the pixel circuit. However, the present invention is not limited thereto, and IN other embodiments, as shown IN fig. 13, when the output signal OUT is the same as the changing state of the fourth node N4, the output signal OUT of the M-th stage shift register may be input to the pixel circuit as the input signal IN of the M + 1-th stage shift register, and the signal Next of the fourth node N4 may be input to the pixel circuit as the driving signal.

With continuing reference to fig. 1 and 2, optionally, wherein the display panel further comprises:

a first voltage signal line XVGH1 for providing a first voltage signal VGH1 for the driving circuit;

a second voltage signal line XVGL1 for providing a second voltage signal VGL1 for the driving circuit;

a third voltage signal line XVGH2 for providing a third voltage signal VGH2 for the driving circuit;

and a fourth voltage signal line XVGL2 for providing a fourth voltage signal VGL2 to the driving circuit.

Since the third voltage signal VGH2 and the fourth voltage signal VGL2 are used to generate the output signal OUT, and the output signal OUT is used to provide a driving signal for the pixel circuit 210 in the display area AA of the display panel, the third voltage signal line XVGH2 and the fourth voltage signal line XVGL2 may be disposed at a side close to the display area AA in order to save the space of the driving circuit 100 as much as possible and avoid an excessively long trace.

Based on this, in some embodiments of the present invention, at least one of the third voltage signal line XVGH2 and the fourth voltage signal line XVGL2 is located at a side of at least one of the first voltage signal line XVGH1 and the second voltage signal line XVGL1 facing the display area of the display panel.

With reference to fig. 2, optionally, the first voltage signal line XVGH1, the second voltage signal line XVGL1, the third voltage signal line XVGH2, and the fourth voltage signal line XVGL2 are all located on a side of the driving circuit 100 away from the display area AA of the display panel. In addition, the third voltage signal line XVGH2 and the fourth voltage signal line XVGL2 are both located at a side of the first voltage signal line XVGH1 and the second voltage signal line XVGL1 close to the display area AA or facing the display area AA of the display panel, so as to maximally save the space of the driving circuit 100 and shorten the trace length.

Of course, the present invention is not limited thereto, and alternatively, as shown in fig. 14, fig. 14 is a schematic structural diagram of another driving circuit provided by the present invention, wherein the first voltage signal line XVGH1 and the second voltage signal line XVGL1 are located on a side of the driving circuit away from the display area AA of the display panel; the third voltage signal line XVGH2 and the fourth voltage signal line XVGL2 are located at a side of the driving circuit facing the display area AA of the display panel, so as to further save the space of the driving circuit 11 and shorten the trace length.

Since the first voltage signal VGH1 is higher than the third voltage signal VGH2, and/or the second voltage signal VGL1 is lower than the fourth voltage signal VGL2, the voltages carried on the first voltage signal line XVGH1 and the second voltage signal line XVGL1 are larger, and if the line width is smaller, the resistance is larger, and the voltage loss is larger. Therefore, optionally, at least one of the first voltage signal line XVGH1 and the second voltage signal line XVGL1 has a line width greater than at least one of the third voltage signal line XVGH2 and the fourth voltage signal line XVGL 2.

Since the first transistor M1 and the second transistor M2 in the shift register generate the output signal OUT, and the first transistor M1 and the second transistor M2 are generally transistors with large width-length ratio, in order to further reduce the frame of the display panel and reduce the space of the driving circuit 100, optionally, referring to fig. 15, fig. 15 is a schematic structural diagram of another driving circuit provided by the present invention, wherein the shift register 110 is cascaded with each other along a first direction X1, and the first transistor M1 and the second transistor M2 are arranged along a second direction X2, wherein the first direction X1 is parallel to the second direction X2.

With continued reference to fig. 1, optionally, wherein the display panel includes a pixel circuit 210, the driving circuit 100 provides the pixel circuit 210 with a first driving signal through the first driving signal line 120, and the first driving signal is the output signal OUT.

Fig. 16 is a circuit schematic diagram of a pixel circuit provided by the present invention, fig. 17 is a circuit schematic diagram of another pixel circuit provided by the present invention, and referring to fig. 16 and 17, the pixel circuit includes a driving transistor T0. Here, the driving transistor T0 in fig. 16 is a PMOS transistor, and the driving transistor T0 in fig. 17 is an NMOS transistor. Of course, the pixel driving circuit further includes other transistors T1 to T6 and other signal input terminals, which are not described herein again.

The gate of the driving transistor T0 is coupled to the first driving signal line 120, and the first driving signal, i.e. the output signal OUT of the shift register, is used to selectively reset the gate of the driving transistor T0, so that the gate of the driving transistor T0 is initialized.

When the output signal OUT of the shift register is V0(Vref/Vbias) in fig. 16 and the transistor T5 and the transistor T2 are turned on, the output signal OUT of the shift register, i.e., V0(Vref/Vbias), is transmitted to the gate of the driving transistor T0, and the gate of the driving transistor T0 is reset.

When the output signal OUT of the shift register is Vobs/Vini in fig. 17 and the transistor T4 and the transistor T2 are turned on, the output signal OUT of the shift register, i.e., Vobs/Vini, is transmitted to the gate of the driving transistor T0, and the gate of the driving transistor T0 is reset.

When the driving transistor T0 is a PMOS transistor, the gate reset mainly gives a low level signal to the gate. However, in order to realize high frequency refresh of the display panel, the gate reset signal should not be too low to shorten the charging time of the node N1' in fig. 16 during the data writing phase, and therefore, the absolute value V of the voltage of the fourth voltage signal VGL2_GL2It needs to be set smaller. And the absolute value V of the voltage of the third voltage signal VGH2_GH2The non-reset phase, which is correspondingly required to be a relatively high level, ensures that the gate of the driving transistor T0 is protected from the signal during the non-reset phase, and thus, for a PMOS transistor, V_GH2It may be appropriate to set it higher, and for NMOS transistors the situation of the levels is just the opposite, but the principle is the same.

Based on this, optionally, the absolute value of the voltage of the first voltage signal VGH1 is V_GH1The absolute value of the voltage of the second voltage signal VGL1 is V_GL1The absolute value of the voltage of the third voltage signal VGH2 is V_GH2The absolute value of the voltage of the fourth voltage signal VGL2 is V_GL2(ii) a When the driving transistor T0 is a PMOS transistor, the voltage level | V_GH1-V_GH2|≤|V_GL1-V_GL2L, |; or, when the driving transistor T0 is an NMOS transistor, then | V_GH1-V_GH2|≥|V_GL1-V_GL2|。

Further, for a PMOS transistor, if | V_GL1-V_GL2|≥V_GL2E.g. V_GH1Is 9V, V_GL2Is only 4V, then | V_GL1-V_GL2I/V_GL2If the voltage is too large, the voltage level at the gate of the driving transistor T0 will not be too low during the reset phase, and smooth operation of the driving transistor T0 is ensured. For an NMOS transistor, the level situation is just the opposite, but the principle is the same.

With continuing reference to fig. 16 and 17, optionally, the pixel circuit includes a data writing module 211, a compensation module 212, and a reset module 213;

the data writing module 211 is connected to the source of the driving transistor T0;

the compensation module 212 is connected between the gate and the drain of the driving transistor T0;

the reset module 213 is connected to the drain of the driving transistor T0;

the working process of the pixel circuit comprises a reset phase and a bias phase, in the reset phase, the reset module 213 and the compensation module 212 are both started, and the grid electrode of the driving transistor T0 receives a reset signal; in the bias phase, the reset module 213 is turned on, the compensation module 212 is turned off, and the drain of the driving transistor T0 receives the bias signal.

Specifically, when the output signal OUT of the shift register is V0(Vref/Vbias) in fig. 16, in the reset phase, the output signal OUT, i.e., the reset signal, is used to reset the gate of the driving transistor T0; in the bias phase, the reset module 213 is turned on, and the output signal OUT, i.e., the bias signal, is used to charge the N3 'node in fig. 16, so that the potential of the N3' node in fig. 16 is higher than the potential of the N1 'node in fig. 16, thereby preventing the leakage current flowing from the N1' node to the N3 'node in the driving transistor T0, which may cause the potential of the N1' node to drop, and thus affect the display of the display panel.

When the output signal OUT of the shift register is Vobs/Vini in fig. 17, in the reset phase, the output signal OUT, i.e., the reset signal, is used to reset the gate of the driving transistor T0; in the bias phase, the output signal OUT, i.e., the bias signal, is used to adjust the potential of the N3 ' node in fig. 17 so that the potential of the N3 ' node in fig. 17 is lower than the potential of the N1 ' node in fig. 17. The difference from fig. 16 is that the levels of the reset signal and the bias signal are different.

With continued reference to fig. 16, optionally, the reset signal is the fourth voltage signal VGL2, the bias signal is the third voltage signal VGH2, or the reset signal is the output signal OUT generated by the fourth voltage signal VGL2, and the bias signal is the output signal OUT generated by the third voltage signal VGH 2.

Specifically, in the light emitting period of the pixel circuit shown in fig. 16, there may be a situation where the potential of the gate N1 'node of the driving transistor T0 is higher than the potential of the drain N3' node, for example, the N2 'node is 4.6V, the N1' node is 3V, and the N3 'node may be 2V, and for the PMOS transistor, after a long time, the stability of the PMOS transistor is affected, so that it is necessary to set the bias period in the non-light emitting period, and the potential of the N3' node is raised by the bias signal, so as to eliminate the above effect in the light emitting period, and in order to fully implement this period, the high level signal VGH2 of the bias signal needs to be as high as possible, and the low level signal VGL2 of the reset signal does not need to be set too low, so that V may be set_GH1-V_GH2|≤|V_GL1-V_GL2|。

Alternatively, with continued reference to fig. 17, the driving transistor is an NMOS transistor, the reset signal is the third voltage signal VGH2, and the bias signal is the fourth voltage signal VGL 2. In other words, the reset signal is the output signal OUT generated by the third voltage signal VGH2, and the bias signal is the output signal OUT generated by the fourth voltage signal VGL 2.

Specifically, the pixel circuit shown in fig. 17In the light phase, there may be a situation that the potential of the gate N1 ' node of the driving transistor T0 is lower than the potential of the drain N3 ' node, for example, the N3 ' node is 4.6V, the N1 ' node is 3V, and for the NMOS transistor, after a long time, the stability of the NMOS transistor is affected, so that it is necessary to set the bias phase in the non-light emitting phase, and the potential of the N3 ' node is pulled down by the bias signal, so as to eliminate the above-mentioned effect in the light emitting phase, in order to fully realize this process, the low level signal VGL2 of the bias signal needs to be as low as possible, and the high level signal VGH2 of the reset signal does not need to be set too low, so that V may be set_GH1-V_GH2|≥|V_GL1-V_GL2|。

Fig. 18 is a schematic plan view of another display panel provided by the present invention, referring to fig. 18, optionally, wherein the display panel further includes a light emitting element 220, and the light emitting element 220 includes a cathode, an anode, and a light emitting layer located between the cathode and the anode. The driving circuit 100 provides a second driving signal to the pixel circuit 210 through the second driving signal line 130, where the second driving signal is an output signal OUT; wherein,

the anode of the light emitting element 220 is coupled to the second driving signal line 130, and the second driving signal, i.e., the output signal OUT, is used for selectively resetting the light emitting element 220.

Specifically, when the output signal OUT of the shift register is Vini in fig. 16 and the transistor T4 is turned on, the output signal OUT of the shift register, that is, Vini is transmitted to the anode of the light-emitting element 220, and the anode of the light-emitting element 220 is reset.

Alternatively, when the output signal OUT of the shift register is VAR in fig. 17 and the transistor T5 is turned on, the output signal OUT of the shift register, namely VAR, is transmitted to the anode of the light-emitting element 220, and the anode of the light-emitting element 220 is reset.

In the embodiment of the utility model, first voltage signal VGH 1's voltage absolute value is V_GH1The absolute value of the voltage of the second voltage signal VGH2 is V_GL1The absolute value of the voltage of the third voltage signal VGH3 is V_GH2The absolute value of the fourth voltage signal VGH4 is V_GL2. Since the light emitting element 22The reset signal for the 0 anode is typically low and, thus, optionally | V_GH1-V_GH2|≤|V_GL1-V_GL2|。

Furthermore, since the potential of the reset signal cannot be too low in some application scenarios, it is optional, wherein | V_GH1-V_GH2|≤V_GH2And | V_GL1-V_GL2|≥V_GL2。

In the above embodiments, only the display panel includes one driving circuit for illustration, the invention is not limited thereto, fig. 19 is a schematic plan view of another display panel provided by the invention, referring to fig. 19, and optionally, the display panel includes a first driving circuit 140 and a second driving circuit 150, the first driving circuit 140 includes N1 shift registers cascaded with each other, the second driving circuit 150 includes N2 shift registers cascaded with each other, N1 is greater than or equal to 2, and N2 is greater than or equal to 2.

Wherein, at least one of the third voltage signal in the first driving circuit 140 and the third voltage signal in the second driving circuit 150 has a higher potential than the other; and/or the potential of at least one of the fourth voltage signal in the first driving circuit 140 and the fourth voltage signal in the second driving circuit 150 is lower than that of the other, so that the voltages of the output signal of the first driving circuit 140 and the output signal of the second driving circuit 150 are different to meet different voltage requirements of different signals in the pixel circuit 210.

With reference to fig. 19, optionally, the display panel further includes a pixel circuit 210, the first driving circuit 140 provides a third driving signal for the pixel circuit 210, the second driving circuit 150 provides a fourth driving signal for the pixel circuit 210, that is, the output signal of the first driving circuit 140 is the third driving signal of the pixel circuit 210, and the output signal of the second driving circuit 150 is the fourth driving signal of the pixel circuit 210. The third driving signal and the fourth driving signal are different driving signals, such as reset signals with different voltages, so as to satisfy different voltage requirements of different signals in the pixel circuit 210. Of course, the present invention is not limited thereto, and in other embodiments, the third driving signal and the fourth driving signal may also be signals with different timings, so as to provide two signals with different timings to the pixel circuit 210. For example, one of the third driving signal and the fourth driving signal is a reset signal, and the other is a scan signal.

In some optional embodiments, please refer to fig. 20, fig. 20 is a schematic plan view of a display device according to the present invention, and the display device 1000 provided in this embodiment includes the display panel 000 provided in the above embodiments of the present invention. The embodiment of fig. 20 only takes a mobile phone as an example to explain the display device 1000, and it should be understood that the display device 1000 provided by the embodiment of the present invention may also be other display devices 1000 with a display function, such as a computer, a television, a vehicle-mounted display device, etc., and the present invention is not limited thereto. The embodiment of the utility model provides a display device 1000 has the beneficial effect of the display panel 100 that the embodiment of the utility model provides, can specifically refer to above-mentioned each embodiment to the specific explanation of display panel 000, this embodiment is no longer repeated here.

According to the above embodiment, the utility model provides a display panel and display device has realized following beneficial effect at least:

Although certain specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, comprising:

the driving circuit comprises N stages of shift registers which are mutually cascaded, wherein N is more than or equal to 2;

the shift register includes:

a first control unit for receiving an input signal and controlling a signal of a first node in response to a first clock signal;

a second control unit for receiving a first voltage signal and a second voltage signal and controlling a signal of a second node in response to a signal of the first node, the first clock signal, and a second clock signal;

a third control unit, configured to receive the first voltage signal and the second voltage signal, and control a signal of a fourth node in response to a signal of the second node and a signal of a third node, where the third node is connected to the first node, the first voltage signal is a high-level signal, and the second voltage signal is a low-level signal;

a fourth control unit for receiving a third voltage signal and a fourth voltage signal and generating an output signal in response to the signal of the second node and the signal of the fourth node; wherein,

the third voltage signal is a high level signal, and the fourth voltage signal is a low level signal;

the potential of the first voltage signal is higher than the potential of the third voltage signal, and/or

The potential of the second voltage signal is lower than the potential of the fourth voltage signal.

2. The display panel according to claim 1,

the fourth control unit includes a first transistor and a second transistor;

the first transistor receives the third voltage signal, and the second transistor receives the fourth voltage signal to generate the output signal.

3. The display panel according to claim 2,

the first transistor and the second transistor are both PMOS transistors;

the source electrode of the first transistor is connected with the third voltage signal, the drain electrode of the first transistor is connected with the output signal, and the grid electrode of the first transistor is connected with the fourth node;

the source of the second transistor is connected to the fourth voltage signal, the drain of the second transistor is connected to the output signal, and the gate of the second transistor is connected to the second node.

4. The display panel according to claim 2,

the first transistor and the second transistor are both NMOS transistors;

the source electrode of the first transistor is connected with the third voltage signal, the drain electrode of the first transistor is connected with the output signal, and the grid electrode of the first transistor is connected with the second node;

the source of the second transistor is connected to the fourth voltage signal, the drain of the second transistor is connected to the output signal, and the gate of the second transistor is connected to the fourth node.

5. The display panel according to claim 2,

the first transistor and the second transistor are both PMOS transistors;

6. The display panel according to claim 2,

the first transistor and the second transistor are both NMOS transistors;

7. The display panel according to claim 2,

the fourth control unit further comprises a first capacitor and a second capacitor;

a first plate of the first capacitor is connected with one of the first voltage signal, the second voltage signal, the third voltage signal or the fourth voltage signal, and a second plate of the first capacitor is connected with the fourth node;

the first plate of the second capacitor is connected to the second node, and the second plate of the second capacitor is connected to the output signal or one of the first voltage signal, the second voltage signal, the third voltage signal, or the fourth voltage signal.

8. The display panel according to claim 7,

the capacitance value of the first capacitor is smaller than or equal to the capacitance value of the second capacitor.

9. The display panel according to claim 2,

the width-to-length ratio of the channel region of the second transistor is greater than or equal to the width-to-length ratio of the channel region of the first transistor.

10. The display panel according to claim 1,

in the N stages of the shift registers of the driving circuit, a signal of the fourth node of the Mth stage of the shift register is connected to an input signal end of the M +1 th stage of the shift register and is used as the input signal of the M +1 th stage of the shift register, wherein M is more than or equal to 1 and less than or equal to N.

11. The display panel according to claim 1,

the display panel comprises a pixel circuit, the driving circuit provides a first driving signal for the pixel circuit through a first driving signal line, and the first driving signal is the output signal; wherein,

the pixel circuit comprises a driving transistor, wherein the grid electrode of the driving transistor is coupled to the first driving signal line, and the first driving signal is used for selectively resetting the grid electrode of the driving transistor.

12. The display panel according to claim 11,

the absolute value of the voltage of the first voltage signal is V_GH1The absolute value of the voltage of the second voltage signal is V_GL1The absolute value of the voltage of the third voltage signal is V_GH2The absolute value of the voltage of the fourth voltage signal is V_GL2(ii) a Wherein,

the driving transistor is a PMOS transistor, then |. V_GH1-V_GH2|≤|V_GL1-V_GL2L, |; or,

the drive transistor is an NMOS transistor, then |. V_GH1-V_GH2|≥|V_GL1-V_GL2|。

13. The display panel according to claim 12,

the drive transistor is a PMOS transistor, then

∣V_GH1-V_GH2|≤V_GH2And | V_GL1-V_GL2|≥V_GL2(ii) a Or,

the drive transistor is an NMOS transistor

∣V_GH1-V_GH2|≥V_GH2And | V_GL1-V_GL2|≤V_GL2。

14. The display panel according to claim 11,

the pixel circuit comprises a data writing module, a compensation module and a reset module;

the data writing module is connected to the source electrode of the driving transistor;

the compensation module is connected between the grid electrode and the drain electrode of the driving transistor;

the reset module is connected to the drain electrode of the driving transistor;

the working process of the pixel circuit comprises a reset stage and a bias stage, wherein in the reset stage, the reset module and the compensation module are both started, and the grid electrode of the driving transistor receives a reset signal; in the bias stage, the reset module is turned on, the compensation module is turned off, and the drain of the driving transistor receives a bias signal.

15. The display panel according to claim 14,

the driving transistor is a PMOS transistor, the reset signal is the fourth voltage signal, and the bias signal is the third voltage signal; or,

the driving transistor is an NMOS transistor, the reset signal is the third voltage signal, and the bias signal is the fourth voltage signal.

16. The display panel according to claim 11,

the display panel further includes a light emitting element, the driving circuit supplies a second driving signal to the pixel circuit through a second driving signal line, the second driving signal being the output signal; wherein,

the anode of the light emitting element is coupled to the second driving signal line, and the second driving signal is used for selectively resetting the light emitting element.

17. The display panel according to claim 16,

the absolute value of the voltage of the first voltage signal is V_GH1The absolute value of the voltage of the second voltage signal is V_GL1The absolute value of the voltage of the third voltage signal is V_GH2The absolute value of the fourth voltage signal is V_GL2(ii) a Wherein,

∣V_GH1-V_GH2|≤|V_GL1-V_GL2|。

18. the display panel according to claim 16,

∣V_GH1-V_GH2|≤V_GH2and | V_GL1-V_GL2|≥V_GL2。

19. The display panel according to claim 1,

the display panel comprises a first driving circuit and a second driving circuit, wherein the first driving circuit comprises N1 cascaded shifting registers, the second driving circuit comprises N2 cascaded shifting registers, N1 is more than or equal to 2, and N2 is more than or equal to 2; wherein,

at least one of the third voltage signal in the first drive circuit and the third voltage signal in the second drive circuit has a higher potential than the other; and/or the presence of a gas in the gas,

at least one of the fourth voltage signal in the first drive circuit and the fourth voltage signal in the second drive circuit has a potential lower than that of the other.

20. The display panel according to claim 19,

the display panel further comprises a pixel circuit, the first driving circuit provides a third driving signal for the pixel circuit, the second driving circuit provides a fourth driving signal for the pixel circuit, and the third driving signal and the fourth driving signal are different driving signals.

21. The display panel according to claim 2,

the shift registers are cascaded with each other along a first direction, and the first transistor and the second transistor are arranged along a second direction, wherein the first direction is parallel to the second direction.

22. The display panel according to claim 1,

the display panel further includes:

a first voltage signal line for providing a first voltage signal to the driving circuit;

a second voltage signal line for providing a second voltage signal to the driving circuit;

a third voltage signal line for providing a third voltage signal to the driving circuit;

a fourth voltage signal line for providing a fourth voltage signal to the driving circuit; wherein,

at least one of the third voltage signal line and the fourth voltage signal line is located at a side of at least one of the first voltage signal line and the second voltage signal line facing a display area of the display panel.

23. The display panel according to claim 22,

the third voltage signal line and the fourth voltage signal line are both positioned on one side of the first voltage signal line and one side of the second voltage signal line, which face the display area of the display panel.

24. The display panel according to claim 22,

the first voltage signal line and the second voltage signal line are positioned on one side of the driving circuit, which is deviated from the display area of the display panel;

the third voltage signal line and the fourth voltage signal line are positioned on one side of the driving circuit facing the display area of the display panel.

25. The display panel according to claim 22,

the first voltage signal line, the second voltage signal line, the third voltage signal line and the fourth voltage signal line are all located on one side, away from the display area of the display panel, of the driving circuit.

26. The display panel according to claim 22,

at least one of the first voltage signal line and the second voltage signal line has a line width greater than at least one of the third voltage signal line and the fourth voltage signal line.

27. The display panel according to claim 7,

the third control unit includes:

a third transistor having a source connected to the first voltage signal, a drain connected to the fourth node, and a gate connected to the second node;

a fourth transistor, a source of which is connected to the second voltage signal, a drain of which is connected to the fourth node, and a gate of which is connected to the third node; wherein,

the aspect ratio of the channel region of the first transistor is larger than the aspect ratio of the channel region of the third transistor, or the aspect ratio of the channel region of the second transistor is larger than the aspect ratio of the channel region of the fourth transistor.

28. The display panel according to claim 27,

the third control unit further includes:

a first plate of the third capacitor is connected with the first voltage signal, and a second plate of the third capacitor is connected with the second node;

a first plate of the fourth capacitor is connected with the second clock signal or the second voltage signal, and a second plate of the fourth capacitor is connected with the third node; wherein,

the capacitance values of the first capacitor and the second capacitor are larger than the capacitance value of the third capacitor and larger than the capacitance value of the fourth capacitor.

29. The display panel according to claim 28,

the first control unit includes:

a fifth transistor, a source of which is connected to the input signal, a drain of which is connected to the first node, and a gate of which is connected to the first clock signal;

the second control unit includes:

a sixth transistor, a source of which is connected to the first node, a drain of which is connected to a drain of the seventh transistor, and a gate of which is connected to the second clock signal;

a seventh transistor, a source of which is connected to the first voltage signal, a drain of which is connected to the drain of the sixth transistor, and a gate of which is connected to a fifth node;

a source of the eighth transistor is connected to the first clock signal, a drain of the eighth transistor is connected to the fifth node, and a gate of the eighth transistor is connected to the first node;

a ninth transistor, a source of which is connected to the second clock signal, a drain of which is connected to the fifth node, and a gate of which is connected to the first clock signal;

a tenth transistor, a source of which is connected to the second clock signal, a drain of which is connected to a sixth node, and a gate of which is connected to the fifth node;

an eleventh transistor, wherein a source of the eleventh transistor is connected to the sixth node, a drain of the eleventh transistor is connected to the second node, and a gate of the eleventh transistor is connected to the second clock signal;

a twelfth transistor, a source of which is connected to the first voltage signal, a drain of which is connected to the second node, and a gate of which is connected to the third node;

and a first pole of the fifth capacitor is connected to the fifth node, and a second pole of the fifth capacitor is connected to the sixth node.

30. The display panel according to claim 29,

the capacitance value of the fifth capacitor is smaller than that of the first capacitor and smaller than that of the second capacitor.

31. The display panel according to claim 30,

the capacitance value of the fifth capacitor is smaller than that of the third capacitor and smaller than that of the fourth capacitor.

32. The display panel according to claim 29,

the second control unit includes:

a thirteenth transistor, wherein a source of the thirteenth transistor is connected to the fifth node, a drain of the thirteenth transistor is connected to a gate of the tenth transistor, and a gate of the thirteenth transistor is connected to the second voltage signal;

a fourteenth transistor, having a source connected to the first node, a drain connected to the third node, and a gate connected to the second voltage signal.

33. A display device characterized by comprising the display panel according to any one of claims 1 to 32.