CN214505486U - Semiconductor packaging structure and electronic product - Google Patents
Semiconductor packaging structure and electronic product Download PDFInfo
- Publication number
- CN214505486U CN214505486U CN202120789487.1U CN202120789487U CN214505486U CN 214505486 U CN214505486 U CN 214505486U CN 202120789487 U CN202120789487 U CN 202120789487U CN 214505486 U CN214505486 U CN 214505486U
- Authority
- CN
- China
- Prior art keywords
- chip
- passivation layer
- conductive pin
- layer
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application discloses a semiconductor packaging structure and an electronic product, which are realized by a mode of hybrid bonding of an organic plug connector and a chip. The organic plug connector is provided with a first conductive pin, wherein a first passivation layer located on one side of the organic plug connector where the first conductive pin is located is formed on the organic plug connector, and the first conductive pin is exposed from one side, far away from the second conductive pin, of the first passivation layer; a second passivation layer is formed on the chip, and the chip pins are exposed from the second passivation layer. Therefore, the first conductive pin is connected with the chip pin in a hybrid bonding mode, the first passivation layer and the second passivation layer are connected in the hybrid bonding mode, an additional connecting piece is not needed, an additional process structure is not needed, and an I/O structure with higher density can be realized.
Description
Technical Field
The application relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure and an electronic product with the same.
Background
When the chip is mounted on the circuit substrate, the circuit substrate and the chip can be bonded by arranging the organic dielectric layer, so that a high-density I/O (Input/Output, abbreviated as Input/Output) structure can be realized, but the scheme also needs to be used for configuring a corresponding silicon dielectric layer (silicon interface) and arranging a silicon via hole, so that the structure is relatively complex and the cost is high. Another solution is to connect the circuit substrate and the chip by using a conventional soldering process, but the conventional soldering process forms solder balls between the circuit substrate and the chip, which leads to a decrease in I/O density.
In view of the above, it is desirable to provide a semiconductor package structure that is low in cost and capable of realizing a high density I/O structure.
SUMMERY OF THE UTILITY MODEL
The present application provides a semiconductor package structure capable of achieving high density I/O on a low cost basis.
In a first aspect, an embodiment of the present application provides a semiconductor package structure, including:
the organic plug connector comprises a first conductive pin and a second conductive pin which are manufactured and formed based on the organic insulating layer and are respectively positioned on two opposite sides of the organic insulating layer;
the first passivation layer is positioned on one side of the organic plug connector where the first conductive pin is positioned, and the first conductive pin is exposed from one side of the first passivation layer, which is far away from the second conductive pin;
the chip is located on one side, far away from the organic plug connector, of the first passivation layer, the chip comprises a second passivation layer and chip pins exposed from the second passivation layer, the first conductive pins are connected with the chip pins in a hybrid bonding mode, and the first passivation layer is connected with the second passivation layer in the hybrid bonding mode.
In a possible implementation manner of the first aspect, the organic insulating layer further includes a redistribution layer, and each redistribution structure in the redistribution layer is connected between the corresponding first conductive pin and the corresponding second conductive pin through a via hole opened in the organic insulating layer, so as to conduct the corresponding first conductive pin and the corresponding second conductive pin.
In one possible implementation of the first aspect, the redistribution layer is a multilayer.
In one possible implementation manner of the first aspect, the first redistribution structure and the second redistribution structure are further included, the first redistribution structure and the second redistribution structure are located in different redistribution layers of different layers, and the first redistribution structure and the second redistribution structure are connected through a via.
In one possible embodiment of the first aspect, further comprising a protective layer;
the protective layer and the chip are located on the same side of the organic plug connector, and the protective layer is used for protecting the chip.
In one possible embodiment of the first aspect, the protective layer is a plastic package body, and the plastic package body is located on a surface of the chip opposite to a contact surface of the first passivation layer and the second passivation layer, and on four side surfaces of the chip.
In one possible implementation manner of the first aspect, the package further includes a solder ball disposed on the second conductive pin.
In one possible embodiment of the first aspect, a vertical projection of the first conductive pin on the chip coincides with a vertical projection of the chip pin on the organic plug.
In one possible embodiment of the first aspect, the first passivation layer and the second passivation layer are organic passivation layers or inorganic passivation layers.
In a second aspect, an embodiment of the present application provides an electronic product, which includes a circuit board and at least one semiconductor package structure of the first aspect, where the semiconductor package structure is mounted on the circuit board.
By adopting the semiconductor packaging structure and the electronic product provided by the embodiment of the application, the semiconductor packaging structure and the electronic product are realized by a hybrid bonding mode of the organic plug connector and the chip. The organic plug connector is provided with a first conductive pin, wherein a first passivation layer located on one side of the organic plug connector where the first conductive pin is located is formed on the organic plug connector, and the first conductive pin is exposed from one side, far away from the second conductive pin, of the first passivation layer; a second passivation layer is formed on the chip, and the chip pins are exposed from the second passivation layer. Therefore, the first conductive pin is connected with the chip pin in a hybrid bonding mode, the first passivation layer and the second passivation layer are connected in a hybrid bonding mode, two passivation layers are directly bonded, an additional connecting piece is not needed, an additional process structure is not needed, and an I/O structure with higher density can be realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below. It is appreciated that the following drawings depict only certain embodiments of the application and are therefore not to be considered limiting of its scope. For a person skilled in the art, it is possible to derive other relevant figures from these figures without inventive effort.
Fig. 1 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the present disclosure;
fig. 2 is a schematic overall structure diagram of a semiconductor package structure according to an embodiment of the present disclosure;
fig. 3 is a schematic overall structure diagram of a semiconductor package structure according to an embodiment of the present disclosure;
fig. 4 is a schematic overall structure diagram of a semiconductor package structure according to an embodiment of the present disclosure;
fig. 5 is a schematic block diagram illustrating a flow of steps of a method for fabricating a semiconductor package structure according to an embodiment of the present disclosure;
fig. 6 to 14 are schematic structural changes of the semiconductor package structure corresponding to each process step in the method for manufacturing the semiconductor package structure according to the embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
In the description of the present application, it is to be understood that the terms "upper", "lower", "inner", "outer", "left", "right", and the like, refer to orientations or positional relationships that are based on the orientations or positional relationships shown in the drawings, or the orientations or positional relationships that the products of the application conventionally position when in use, or the orientations or positional relationships that are conventionally understood by those skilled in the art, and are used for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and therefore, should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
The following detailed description of embodiments of the present application will be made with reference to the accompanying drawings.
In order to solve the technical problems of the background art, please refer to fig. 1 and fig. 2 in combination, in which fig. 1 is a schematic structural diagram of a semiconductor package structure 1 according to an embodiment of the present disclosure, and fig. 2 is a schematic structural diagram of an entire semiconductor package structure 1 according to an embodiment of the present disclosure.
The semiconductor package 1 includes an organic plug 10 and a chip 20. The organic plug 10 includes a first conductive lead 102 and a second conductive lead 103 formed on the basis of the organic insulating layer 101 and respectively located on two opposite sides of the organic insulating layer 101, and the chip 20 includes a second passivation layer 201 and a chip lead 202 exposed from the second passivation layer 201. The first passivation layer 30 is disposed on the organic plug 10 at a side where the first conductive leads 102 are located, and the first conductive leads 102 are exposed from a side of the first passivation layer 30 away from the second conductive leads 103. By such design, the first conductive lead 102 and the chip lead 202 are connected by hybrid bonding, and the first passivation layer 30 and the second passivation layer 201 are connected by hybrid bonding.
The first passivation layer 30 on the organic plug 10 may be formed on the organic plug 10 on the side where the first conductive leads 102 are located by a deposition (e.g., Chemical vapor deposition) process, and the first conductive leads 102 may be exposed from the first passivation layer 30 after Chemical Mechanical Polishing (Chemical Mechanical Polishing) is performed on the first passivation layer 30. In the embodiment of the present application, the chip leads 202 of the chip 20 may also be exposed on the second passivation layer 201 by chemical mechanical polishing. It should be understood that the chip leads 202 and the first conductive leads 102 may be located in a one-to-one correspondence to facilitate subsequent alignment bonding.
Through the arrangement, the first conductive lead 102 and the chip lead 202 can be directly bonded, and meanwhile, the first passivation layer 30 and the second passivation layer 201 are directly bonded, and are bonded together through van der waals force. Compared with an organic hybrid bonding mode in the related technology, the method does not need to arrange a silicon through hole, does not need to relate to complex processes such as etching, exposure and the like required in the process of manufacturing the silicon through hole, and further can reduce the cost on the basis of lower process difficulty. Compared with the scheme of using the conventional soldering process to connect the chip 20 and the substrate in the related art, since soldering is not required and no solder ball is located between the first conductive pin 102 and the chip pin 202, the space utilization rate is high, and the scheme of high-density I/O can be realized.
With reference to fig. 1 and fig. 2, in a possible implementation, the organic insulating Layer 101 further includes a Redistribution Layer (RDL) 104, and each Redistribution structure in the Redistribution Layer 104 is connected between the corresponding first conductive pin 102 and the second conductive pin 103 through a via 105 formed in the organic insulating Layer 101, so as to conduct the corresponding first conductive pin 102 and the second conductive pin 103.
In one possible implementation, the redistribution layer 104 is multi-layered.
It should be understood that, in order to satisfy diversified functions of the chip 20 or different functions of a plurality of chips 20, a plurality of redistribution layers 104 may be provided, and the redistribution structures included in the respective redistribution layers 104 may be matched with each other or independently perform functions required by the chip 20. If there are rewiring structures located in different rewiring layers 104 that need to be electrically connected to each other, the rewiring structures may also be electrically connected to each other through vias 105. With the above structure, a fan-out (fan out) semiconductor package structure can be obtained, and in addition, a fan-in (fan in) semiconductor package structure, a 2.5D semiconductor package structure, and a 3D semiconductor package structure can be adapted by using the above structure, which is not limited in the embodiments of the present application.
Referring to fig. 3, in one possible embodiment, the semiconductor package structure 1 may further include a protection layer 40. The protection layer 40 is located on the same side of the organic plug 10 as the chip 20, and the protection layer 40 is used for protecting the chip 20.
In order to protect the chip 20, in the embodiment of the present application, the protection layer 40 may be formed by performing at least one of a plastic molding process, a dry film process, and a coating process on the chip 20.
Referring to fig. 4, in one possible embodiment, the method further includes forming a solder ball 50 on the second conductive lead 103 by a ball-mounting process.
In addition to the protection layer 40 for protecting the chip 20, the solder ball 50 may be formed on the second conductive pin 103 by a ball-mounting process, and the second conductive pin 103 may be a metal bump formed on the bottom of the organic insulating layer 101 by a metal bump forming process, and thus may be referred to as an Under Bump Metallurgy (UBM). The solder balls 50 formed on the second conductive leads 103 can be used for mounting the semiconductor package structure 1 on a corresponding circuit board by a process such as reflow soldering when the semiconductor package structure 1 needs to be mounted on the corresponding circuit board of an electronic product after the whole semiconductor package structure 1 is prepared subsequently.
Fig. 5 is a schematic flow chart illustrating a method for manufacturing a semiconductor package structure 1 according to an embodiment of the present application, and the process steps included in the method will be described in detail with reference to fig. 6 to 14.
In step S101, as shown in fig. 6, a substrate carrier 60 is provided.
In step S102, as shown in fig. 7, the organic plug 10 is formed on one side of the substrate carrier 60. The organic plug 10 includes a first conductive lead 102 and a second conductive lead 103 formed on the basis of the organic insulating layer 101 and respectively located on two opposite sides of the organic insulating layer 101.
As a possible implementation manner, the foregoing step S102 may be implemented by the following specific steps:
in sub-step S102-1, a temporary bonding paste 70 is applied to one side of the substrate carrier 60.
In the substep S102-2, the organic connector 10 is fabricated on the side of the temporary bonding paste 70 away from the substrate carrier.
The substrate carrier 60 is used as a subsequent removable part, only as a bearing part for manufacturing the organic plug connector 10, the organic plug connector 10 can be temporarily fixed on the substrate carrier 60 by coating the temporary bonding glue 70, the temporary bonding glue 70 can be completely removed when the substrate carrier 60 needs to be removed subsequently, the temporary bonding glue 10 cannot remain on the organic plug connector 10, meanwhile, the temporary bonding glue 70 is arranged to realize a certain buffering effect, and then the collision problem possibly generated by external mechanical force between the substrate carrier 60 and the organic plug connector 10 in the subsequent process flow is prevented to a certain extent.
In step S103, as shown in fig. 8, a first passivation layer 30 is formed on the side of the organic plug 10 having the first conductive pin 102, and the first conductive pin 102 is exposed from the side of the first passivation layer 30 away from the second conductive pin 103.
As a possible implementation manner, the foregoing step S103 may be implemented by the following steps.
In sub-step S103-1, a first passivation layer 30 is deposited on the side of the organic plug 10 having the first conductive leads 102.
Sub-step 103-2, chemical mechanical polishing the first passivation layer 30 exposes the first conductive leads 102 from the first passivation layer 30.
It should be understood that in an actual production process, the semiconductor package 1 may be mass-produced, the organic plug 10 may be multiple, and the following steps may be referred to implement the fabrication of the organic plug 10.
(1) A metal pad layer (i.e., the first conductive pin 102, the multiple wiring layer 104, and the second conductive pin 103) may be fabricated on the Organic insulating layer 101(Organic substrate).
(2) The first passivation layer 30 is deposited on the organic insulating layer 101 at the side where the first conductive pin 102 is located by a PECVD (Plasma Enhanced Chemical Vapor Deposition) process.
It is noted that the inorganic passivation layer may be manufactured by a PECVD process, and both the first passivation layer 30 and the second passivation layer 201 may be inorganic passivation layers. In another embodiment provided in the present embodiment, the first passivation layer 30 and the second passivation layer 201 may also be made of organic passivation layers, and furthermore, the first passivation layer 30 and the second passivation layer 201 may also be made of organic passivation layers and inorganic passivation layers, respectively, as long as the molecular polarity can be satisfied to achieve connection through van der waals force, which is not limited herein.
(3) The first passivation layer 30 is polished and planarized by a CMP (Chemical Mechanical Polishing) process to expose the first conductive leads 102 and to smooth the surface of the first passivation layer 30.
Step S104, as shown in fig. 9 and 10, provides the chip 20 to be packaged. Wherein the chip 20 includes a second passivation layer 201 and a chip lead 202 exposed from the second passivation layer 201.
Accordingly, in order to realize the solution of mass production of the semiconductor package 1, a wafer fabricated with a chip array may be provided, the wafer including a second passivation layer 201 and chip pins 202 covered by the second passivation layer 201, as shown in fig. 9. A CMP process may be performed on the wafer such that the chip pins 202 are exposed from the second passivation layer 201, and a SAW process (dicing process) is performed on the wafer according to a predetermined size, resulting in a plurality of individual chips 20 to be packaged, as shown in fig. 10. In the embodiment of the present application, the position of the chip lead 202 on the manufactured chip 20 may correspond to the position of the first conductive lead 102 on the organic insulating layer 101, so as to enable direct bonding in the following. In the embodiment of the present application, the first conductive pin 102 and the chip pin 202 may be made of copper, tin, or other conductive metal, which is not limited herein.
In step S105, as shown in fig. 11, the chip 20 is mounted on the organic plug 10 by hybrid bonding, such that the first conductive leads 102 and the chip leads 202 are hybrid bonded, and the first passivation layer 30 and the second passivation layer 201 are hybrid bonded.
As described above, the batch mounting of the plurality of chips 20 can be realized by performing the chip 20 introduction (Pick and place) and mounting the plurality of chips 20 cut by the SAW process on the corresponding organic plug 10 so that the first conductive leads 102 and the chip leads 202 are hybrid-bonded and the first passivation layer 30 and the second passivation layer 201 are hybrid-bonded.
The semiconductor package structure 1 manufactured through the steps has the characteristics that the first conductive pin 102 is directly bonded with the chip pin 202, and the first passivation layer 30 is directly bonded with the second passivation layer 201, every two parts are combined through van der waals force, no additional connecting structure needs to be arranged, and compared with the related technology in which a silicon through hole needs to be arranged to realize connection, the scheme provided by the application has the advantages of simple structure and lower cost, compared with the related technology in which a solder ball needs to be used to realize connection, the scheme provided by the application does not need other connecting pieces, and therefore, high-density I/O is provided.
In addition to the foregoing embodiments, the present application examples provide the following examples.
In step S106, after the chip 20 is mounted on the organic plug 10, the protective layer 40 for protecting the chip 20 is formed.
In step S107, the substrate carrier 60 is removed from the organic plug 10.
In order to improve the manufacturing efficiency, at least one of a plastic Molding process, a dry film pressing process, and a coating process (Molding or coating) may be performed on one side of the organic connector 10 where the plurality of chips 20 are located, so as to form a protective layer 40 for protecting the chips 20, as shown in fig. 12. De-carrier (removal of the substrate carrier 60) may then be performed while removing the temporary bonding paste 70, as shown in fig. 13.
In order to describe the embodiment of the present application more clearly, as a possible implementation manner, in the organic plug 10, the organic plug further includes a redistribution layer 104 located in the organic insulating layer 101, and each redistribution structure in the redistribution layer 104 is connected between the corresponding first conductive pin 102 and the corresponding second conductive pin 103 through a via 105 opened in the organic insulating layer 101, so as to conduct the corresponding first conductive pin 102 and the corresponding second conductive pin 103, the method further includes:
in step S108, Ball bonding (Ball drop) is performed on each second conductive pin 103 of the organic plug 10.
By using a ball-mounting process, a solder ball 50 is formed on each second conductive lead 103, and is cut (saw) according to a predetermined specification, so as to obtain a single Fan-out package product (Fan out package product), as shown in fig. 14.
Through the steps, the product manufacturing of the semiconductor split charging structure of the high-density I/O can be realized without additional connecting pieces and at lower cost.
In summary, the semiconductor package structure and the electronic product provided in the embodiments of the present application are implemented by hybrid bonding of an organic plug and a chip. The organic plug connector is provided with a first conductive pin, wherein a first passivation layer located on one side of the organic plug connector where the first conductive pin is located is formed on the organic plug connector, and the first conductive pin is exposed from one side, far away from the second conductive pin, of the first passivation layer; a second passivation layer is formed on the chip, and the chip pins are exposed from the second passivation layer. Therefore, the first conductive pin is connected with the chip pin in a hybrid bonding mode, the first passivation layer and the second passivation layer are connected in the hybrid bonding mode, an additional connecting piece is not needed, an additional process structure is not needed, and an I/O structure with higher density can be realized.
The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical applications, to thereby enable others skilled in the art to best utilize the disclosure and various embodiments with various modifications as are suited to the particular use contemplated. The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical applications, to thereby enable others skilled in the art to best utilize the disclosure and various embodiments with various modifications as are suited to the particular use contemplated.
Claims (10)
1. A semiconductor package structure, comprising:
the organic plug connector comprises a first conductive pin and a second conductive pin which are manufactured and formed based on an organic insulating layer and are respectively positioned on two opposite sides of the organic insulating layer;
the first passivation layer is positioned on one side of the organic plug connector where the first conductive pin is positioned, and the first conductive pin is exposed from one side of the first passivation layer, which is far away from the second conductive pin;
the chip is located on one side, far away from the organic plug connector, of the first passivation layer, the chip comprises a second passivation layer and a chip pin exposed out of the second passivation layer, the first conductive pin is connected with the chip pin in a hybrid bonding mode, and the first passivation layer is connected with the second passivation layer in the hybrid bonding mode.
2. The semiconductor package structure according to claim 1, wherein the organic insulating layer further comprises a redistribution layer, and each redistribution structure in the redistribution layer is connected between the corresponding first conductive pin and the corresponding second conductive pin through a via hole formed in the organic insulating layer, so as to conduct the corresponding first conductive pin and the corresponding second conductive pin.
3. The semiconductor package structure of claim 2, wherein the redistribution layer is multi-layered.
4. The semiconductor package structure of claim 3, further comprising a first redistribution structure and a second redistribution structure, wherein the first redistribution structure and the second redistribution structure are located on different levels of redistribution layers, and wherein the first redistribution structure and the second redistribution structure are connected by the via.
5. The semiconductor package structure of claim 1, further comprising a protective layer;
the protective layer and the chip are located on the same side of the organic plug connector, and the protective layer is used for protecting the chip.
6. The semiconductor package structure of claim 5, wherein the protection layer is a plastic package body covering a surface of the chip opposite to contact surfaces of the first passivation layer and the second passivation layer, and four side surfaces of the chip.
7. The semiconductor package structure of claim 1, further comprising a solder ball disposed on the second conductive lead.
8. The semiconductor package structure of claim 1, wherein a vertical projection of the first conductive pin on the chip coincides with a vertical projection of the chip pin on the organic plug.
9. The semiconductor package structure of claim 1, wherein the first passivation layer and the second passivation layer are organic passivation layers or inorganic passivation layers.
10. An electronic product, characterized in that the electronic product comprises a circuit board and at least one semiconductor package according to any one of claims 1-9, the semiconductor package being mounted on the circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120789487.1U CN214505486U (en) | 2021-04-16 | 2021-04-16 | Semiconductor packaging structure and electronic product |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120789487.1U CN214505486U (en) | 2021-04-16 | 2021-04-16 | Semiconductor packaging structure and electronic product |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214505486U true CN214505486U (en) | 2021-10-26 |
Family
ID=78203519
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120789487.1U Active CN214505486U (en) | 2021-04-16 | 2021-04-16 | Semiconductor packaging structure and electronic product |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN214505486U (en) |
-
2021
- 2021-04-16 CN CN202120789487.1U patent/CN214505486U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11233036B2 (en) | Interconnect structure with redundant electrical connectors and associated systems and methods | |
| US10777502B2 (en) | Semiconductor chip, package structure, and pacakge-on-package structure | |
| US20210272932A1 (en) | Semiconductor device having laterally offset stacked semiconductor dies | |
| US10867897B2 (en) | PoP device | |
| TWI573236B (en) | Semiconductor device and method of bonding different size semiconductor die at the wafer level | |
| CN105374693A (en) | Semiconductor packages and methods of forming the same | |
| US20240088123A1 (en) | Integrated Circuit Package and Method | |
| CN111952274A (en) | Electronic package and manufacturing method thereof | |
| US9548283B2 (en) | Package redistribution layer structure and method of forming same | |
| CN111883505A (en) | Electronic package, bearing substrate thereof and manufacturing method | |
| CN114975416A (en) | Three-dimensional fan-out type memory packaging structure and packaging method thereof | |
| US20200075510A1 (en) | Semiconductor package and manufacturing method thereof | |
| TWI723414B (en) | Electronic package and manufacturing method thereof | |
| TWI441312B (en) | A three dimensional chip stacking electronic package with bonding wires | |
| CN214505486U (en) | Semiconductor packaging structure and electronic product | |
| CN118039572A (en) | Electronic package and method for manufacturing the same | |
| CN115224012A (en) | Semiconductor device with multiple substrates and die stacks | |
| CN110828430A (en) | Packaging structure and preparation method thereof | |
| TW202137342A (en) | Chip embedded substrate structure, chip package structure and methods of manufacture thereof | |
| TWI804094B (en) | Chip package structure and manufacturing method thereof | |
| US20230387078A1 (en) | Semiconductor structure with integrated passive device having opposed solder bumps | |
| CN220585231U (en) | Packaging structure | |
| US20240274578A1 (en) | Stacked semiconductor device | |
| CN210516718U (en) | Packaging structure | |
| KR20240049104A (en) | Semiconductor package and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: No.12 Shangyang Road, high tech Zone, Chengdu, Sichuan 610000 Patentee after: Chengdu Yicheng Technology Co.,Ltd. Address before: No.12 Shangyang Road, high tech Zone, Chengdu, Sichuan 610000 Patentee before: Chengdu yisiwei System Technology Co.,Ltd. |