CN214315268U - SWP main interface circuit and terminal - Google Patents

Abstract

The present disclosure provides a SWP main interface circuit and a terminal, wherein the circuit includes: an SWP host interface; a voltage pulse transmitting unit; the current transmitting unit is used for generating a first current modulation signal and sending the first current modulation signal to the current receiving unit; the current receiving unit is used for receiving a first current modulation signal based on a current threshold value, outputting a digital modulation signal according to the received first current modulation signal, and receiving a second current modulation signal sent by the SWP slave interface from the SWP master interface based on the current threshold value; the threshold adjusting unit is used for adjusting the current threshold; and the performance detection unit is used for detecting the performance of the SWP main interface circuit according to the digital modulation signal. The circuit can realize the detection and evaluation of the circuit performance through the current transmitting unit and the performance detecting unit, reduce the later test cost, compensate the change of the current threshold value along with the change of the process by adjusting the current threshold value, and improve the receiving performance of the circuit.

Description

SWP main interface circuit and terminal

Technical Field

The present disclosure relates to the field of near field communication technologies, and in particular, to an SWP main interface circuit and a terminal.

Background

Near Field payment is a mobile payment technology based on Near Field Communication (NFC) technology, and can be conveniently applied to embedded smart devices such as mobile phones, hand rings, computers, and the like, and at present, a main Near Field payment scheme is an SWP-SIM Card scheme, in which an SWP (single wire protocol) interface on NFC is used as a master interface of SWP-SIM Communication, and an SWP interface on UICC (Universal Integrated Circuit Card) is used as a slave interface of SWP-SIM Communication. Therefore, the design and research of the high-performance and low-cost SWP main interface circuit have very important significance. The SWP main interface is a key interface for realizing single-wire full-duplex communication between the UICC card and the NFC front-end chip, and the performance of the SWP main interface is directly related to the communication quality of the NFC front-end chip card and the UICC card.

In the related art, the SWP main interface circuit includes an SWP main interface, a voltage pulse transmitting unit, and a current receiving unit. However, the SWP main interface circuit cannot automatically evaluate the performance of the SWP main interface, and the evaluation and test cost at the later stage is high.

SUMMERY OF THE UTILITY MODEL

The present disclosure is directed to solving, at least to some extent, one of the technical problems in the related art.

The main technical scheme of the disclosure is as follows.

An embodiment of a first aspect of the present disclosure provides an SWP main interface circuit, including: an SWP host interface; the voltage pulse transmitting unit is connected with the SWP main interface and used for controlling the SWP main interface to send a voltage pulse signal to the SWP slave interface; the current transmitting unit is connected with the voltage pulse transmitting unit and used for generating a first current modulation signal and sending the first current modulation signal to the current receiving unit; the current receiving unit is respectively connected with the SWP main interface, the voltage pulse transmitting unit and the current transmitting unit, and is used for receiving a first current modulation signal based on a current threshold value, outputting a digital modulation signal according to the received first current modulation signal, and receiving a second current modulation signal sent by the SWP slave interface from the SWP main interface based on the current threshold value when the SWP main interface sends a voltage pulse signal; the threshold adjusting unit is connected with the current receiving unit and is used for adjusting the current threshold; and the performance detection unit is connected with the current receiving unit and is used for detecting the performance of the SWP main interface circuit according to the digital modulation signal.

In addition, the SWP main interface circuit proposed according to the above embodiment of the present disclosure may also have the following additional technical features.

In some examples of the disclosure, the current transmitting unit includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a first PMOS transistor, and a second PMOS transistor; the drain of the first NMOS transistor is connected to the voltage pulse transmitting unit, the SWP main interface, and the current receiving unit, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the gate of the first NMOS transistor is used for inputting a control signal, the gate of the second NMOS transistor is connected to the gate of the third NMOS transistor, the drain of the third NMOS transistor, and the drain of the first PMOS transistor, the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, the drain of the ninth NMOS transistor, the drain of the tenth NMOS transistor, the drain of the eleventh NMOS transistor, and the drain of the fourth NMOS transistor, the gate of the ninth NMOS transistor, the gate of the tenth NMOS transistor, and the gate of the eleventh NMOS transistor are connected to the first adjusting terminal, a source of the ninth NMOS transistor is connected to a drain of the fifth NMOS transistor, a source of the tenth NMOS transistor is connected to a drain of the sixth NMOS transistor, a source of the eleventh NMOS transistor is connected to a drain of the seventh NMOS transistor, the gate of the fifth NMOS transistor, the gate of the sixth NMOS transistor, the gate of the seventh NMOS transistor, the drain of the eighth NMOS transistor, and the gate of the eighth NMOS transistor are used for inputting a first reference current, the source electrode of the first PMOS transistor and the source electrode of the second PMOS transistor are connected with a power supply end, the source electrode of the second NMOS transistor, the source electrode of the third NMOS transistor, the source electrode of the fourth NMOS transistor, the source electrode of the fifth NMOS transistor, the source electrode of the sixth NMOS transistor, the source electrode of the seventh NMOS transistor and the source electrode of the eighth NMOS transistor are connected with a ground end; the current transmitting unit is specifically configured to generate a first current modulation signal through the first adjusting terminal, and send the first current modulation signal to the current receiving unit through the control signal.

In some examples of the disclosure, the threshold adjusting unit includes: a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, and an eighteenth NMOS transistor; the gate of the twelfth NMOS transistor, the drain of the twelfth NMOS transistor, the gate of the thirteenth NMOS transistor, the gate of the fourteenth NMOS transistor, and the gate of the fifteenth NMOS transistor are used for inputting a second reference current, the drain of the thirteenth NMOS transistor is connected to the source of the sixteenth NMOS transistor, the drain of the fourteenth NMOS transistor is connected to the source of the seventeenth NMOS transistor, the drain of the fifteenth NMOS transistor is connected to the source of the eighteenth NMOS transistor, the gate of the sixteenth NMOS transistor, the gate of the seventeenth NMOS transistor, and the gate of the eighteenth NMOS transistor are connected to a second regulation terminal, the drain of the sixteenth NMOS transistor, the drain of the seventeenth NMOS transistor, and the drain of the eighteenth NMOS transistor are connected to the current receiving unit, and the source of the twelfth NMOS transistor is connected to the current receiving unit, The source electrode of the thirteenth NMOS transistor, the source electrode of the fourteenth NMOS transistor and the source electrode of the fifteenth NMOS transistor are connected with the ground end; the threshold adjusting unit is specifically configured to adjust the current threshold through the second adjusting terminal.

In some examples of the disclosure, the SWP master interface circuit further comprises: an electrostatic protection unit; the electrostatic protection unit includes: a first diode, a second diode and a first resistor; one end of the first resistor is connected to the SWP main interface, the other end of the first resistor is connected to the anode of the first diode, the cathode of the second diode, the voltage pulse transmitting unit, the current transmitting unit and the current receiving unit, respectively, the cathode of the first diode is connected to a power supply terminal, and the anode of the second diode is connected to a ground terminal.

In some examples of the disclosure, the voltage pulse transmitting unit includes: a first buffer, a third PMOS transistor, a nineteenth NMOS transistor, and a second resistor; the input end of the first buffer is used for receiving a voltage modulation signal, the output end of the first buffer is respectively connected with the grid electrode of the third PMOS transistor and the grid electrode of the nineteenth NMOS transistor, the drain electrode of the third PMOS transistor is connected with one end of the second resistor, the other end of the second resistor is respectively connected with the drain electrode of the nineteenth NMOS transistor, the anode of the first diode, the current transmitting unit and the current receiving unit, the source electrode of the third PMOS transistor is respectively connected with the current receiving unit and a power supply end, and the source electrode of the nineteenth NMOS transistor is connected with the ground end.

In some examples of the disclosure, the current receiving unit includes: a fourth PMOS transistor, a third resistor, a comparator and a second buffer; the gate of the fourth PMOS transistor is connected to ground, the source of the fourth PMOS transistor is connected to the source of the third PMOS transistor, the drain of the fourth PMOS transistor is connected to one end of the third resistor, the positive input end of the comparator is connected to the other end of the third resistor and the threshold adjusting unit, the negative input end of the comparator is connected to the anode of the first diode and the current emission unit, and the output end of the comparator is connected to the input end of the second buffer.

In some examples of the disclosure, the SWP master interface circuit further comprises: and the digital demodulation unit is connected with the output end of the current receiving unit and is used for demodulating the output signal output by the current receiving unit so as to analyze the data sent by the SWP from the interface.

An embodiment of a second aspect of the present disclosure provides a terminal, including the SWP main interface circuit provided in the embodiment of the first aspect of the present disclosure.

According to the technical scheme, the circuit performance can be detected and evaluated through the current transmitting unit and the performance detecting unit, the later-stage testing cost is reduced, the current threshold value can be adjusted to make up the change of the current threshold value along with the change of the process, and the receiving performance of the circuit is improved.

Additional aspects and advantages of the disclosure will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosure.

Drawings

The foregoing and/or additional aspects and advantages of the present disclosure will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a schematic block diagram of an SWP host interface circuit according to one embodiment of the present disclosure;

fig. 2A is a schematic structural diagram of a current transmitting unit according to one embodiment of the present disclosure;

fig. 2B is a schematic structural diagram of a current receiving unit according to an embodiment of the present disclosure;

FIG. 2C is a schematic block diagram of an SWP host interface circuit according to one embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a terminal according to an embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and intended to be illustrative of the present disclosure, and should not be construed as limiting the present disclosure.

The embodiment of the disclosure provides an SWP main interface circuit in order to automatically detect or evaluate the performance of an SWP main interface.

The SWP main interface circuit and the terminal of the embodiments of the present disclosure are described below with reference to the drawings.

Fig. 1 is a block diagram of a SWP host interface circuit according to an embodiment of the present disclosure.

As shown in fig. 1, the SWP host interface circuit 100 includes: an SWP main interface 101, a voltage pulse transmitting unit 102, a current transmitting unit 103, a current receiving unit 104, a performance detecting unit 105, and a threshold adjusting unit 106.

The voltage pulse transmitting unit 102 is connected to the SWP master interface 101, and is configured to control the SWP master interface 101 to transmit a voltage pulse signal to the SWP slave interface; the current transmitting unit 103 is connected to the voltage pulse transmitting unit 102, and configured to generate a first current modulation signal and send the first current modulation signal to the current receiving unit 104; the current receiving unit 104 is respectively connected to the SWP master interface 101, the current transmitting unit 103 and the voltage pulse transmitting unit 102, and is configured to receive a first current modulation signal based on a current threshold, and output a digital modulation signal according to the received first current modulation signal, and further configured to receive a second current modulation signal sent by the SWP slave interface from the SWP master interface 101 based on the current threshold when the SWP master interface 101 sends a voltage pulse signal; the performance detection unit 105 is connected to the current receiving unit 104, and is configured to detect performance of the SWP main interface circuit 100 according to the digital modulation signal; a threshold adjusting unit 106, the threshold adjusting unit 106 is connected to the current receiving unit 104, and the threshold adjusting unit 106 is configured to adjust the current threshold.

In the embodiment of the present disclosure, the SWP master interface may be understood as an input/output interface of the SWP master interface Circuit, which may be connected to an SWP slave interface of a UICC (Universal Integrated Circuit Card).

In the embodiment of the present disclosure, the performance of the SWP main interface circuit may be detected or evaluated by simulating the SWP slave interface of the UICC to transmit a current signal, and a unit or a circuit that completes the simulation function may be referred to as a current transmitting unit. The current modulation signal generated and transmitted by the current transmitting unit may be referred to as a first current modulation signal.

Specifically, when the performance of the SWP main interface circuit 100 needs to be evaluated, the current transmitting unit 103 may be controlled to start to operate, that is, the current transmitting unit 103 generates a first current modulation signal and transmits the first current modulation signal to the current receiving unit 104, the current receiving unit 104 receives the first current modulation signal based on a current threshold and outputs a digital modulation signal according to the received first current modulation signal, and the performance detecting unit 105 detects the performance of the SWP main interface circuit 100 according to the digital modulation signal.

Compared with an SWP main interface circuit (without a current transmitting unit and a performance detecting unit) in the related art, the SWP main interface circuit can simulate an SWP slave interface to realize the transmission of a first current modulation signal, and can detect the performance of the SWP main interface circuit according to the first current modulation signal.

It should be noted that, in the embodiment of the present disclosure, before the SWP main interface circuit 100 normally operates, the performance test of the circuit may be implemented through the current transmitting unit 103, the current receiving unit 104 and the performance detecting unit 105, or the performance test of the circuit may be implemented through the current transmitting unit 103, the current receiving unit 104 and the performance detecting unit 105 periodically during the normal operation of the SWP main interface circuit 100, which specific manner may be determined according to an actual situation, which is not specifically limited in this embodiment of the present disclosure.

The SWP main interface circuit of the embodiment of the disclosure can realize automatic detection of the performance of the SWP main interface circuit through the emission function of the analog current, thereby reducing the test cost of the circuit in the later period.

It is understood that, in general, when the SWP master interface circuit 100 is operating normally to implement normal communication, the SWP slave interface may transmit the current modulation signal S2 while the SWP master interface 101 transmits the voltage pulse modulation signal S1 according to the TS 102613 protocol specification defined by ETSI (European Telecommunications Standards Institute), so as to implement single-wire full duplex communication.

Thus, in one embodiment of the present disclosure, the current receiving unit 104 may also be configured to: when the SWP master interface 101 transmits the voltage pulse signal, a second current modulation signal transmitted by the SWP slave interface is received from the SWP master interface 101 based on the current threshold.

Here, the second current modulation signal may be understood as a current modulation signal S2 sent by the SWP slave interface of the UICC.

Specifically, the voltage pulse transmitting unit 102 controls the SWP master interface 101 to send the voltage pulse modulation signal S1 to the SWP slave interface of the UICC, so as to complete transmission of the voltage pulse modulation signal. While the SWP master interface transmits the voltage pulse modulation signal S1, the SWP master interface 101 may receive the current modulation signal S2 transmitted by the SWP slave interface, and at this time, the current receiving unit 103 of the SWP master interface circuit receives the current modulation signal S2 transmitted by the SWP slave interface from the SWP master interface 101 based on the current threshold to complete the reception of the current modulation signal.

It should be noted that, in the related art, the current threshold of the SWP main interface circuit for receiving the current modulation signal is relatively easily affected by the process, that is, the current threshold may change with the process, which affects the receiving performance. Therefore, in the embodiment of the disclosure, the current threshold may be adjusted to compensate for the problem of the reduced receiving performance caused by the change of the current threshold along with the process change.

That is, in this embodiment, referring to fig. 1, before the SWP master interface circuit 101 operates, the current threshold may be adjusted, that is, the threshold adjusting unit 106 may adjust the current threshold and may send the adjusted current threshold to the current receiving unit 104, and the current receiving unit 104 receives the second current modulation signal S2 sent by the SWP slave interface from the SWP master interface 101 based on the adjusted current threshold, so as to complete the reception of the current modulation signal S2.

In the embodiment of the present disclosure, in order to avoid or reduce the influence of the receiving performance on the performance detection and improve the reliability and accuracy of the circuit performance detection, when the SWP main interface circuit 101 performs a circuit performance test (evaluation), the threshold adjusting unit 106 may also adjust the current threshold, and may send the adjusted current threshold to the current receiving unit 104, and then the current receiving unit 104 receives the first current modulation signal S21 sent by the current transmitting unit 103 based on the adjusted current threshold, and outputs the digital modulation signal according to the received first current modulation signal S21, so as to complete the reception of the first current modulation signal S21. The first current modulation signal S21 can be understood as a signal simulating the second current modulation signal S2.

Therefore, the current threshold is adjusted through the threshold adjusting unit, and the change of the current threshold along with the process can be compensated, so that the receiving performance can be improved, and the accuracy and the reliability of circuit performance detection can be improved.

In one embodiment of the present disclosure, as shown in fig. 2A, the current transmitting unit 103 may include: a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N10, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a first PMOS transistor P1, and a second PMOS transistor P2.

Wherein, the drains of the first NMOS transistor N1 are respectively connected to the voltage pulse transmitting unit 102, the SWP main interface 101, and the current receiving unit 104 (not shown in fig. 2A, that is, the first node d1 in fig. 2A is respectively connected to the voltage pulse transmitting unit 102, the SWP main interface 101, and the current receiving unit 104), the source of the first NMOS transistor N1 is connected to the drain of the second NMOS transistor N2, the gate of the first NMOS transistor N1 is used for inputting the control signal EN, the gate of the second NMOS transistor N2 is respectively connected to the gate of the third NMOS transistor N2, the drain of the third NMOS transistor N3, and the drain of the first PMOS transistor P1, the gate of the first PMOS transistor P1 is respectively connected to the gate of the second PMOS transistor P2, the drain of the second PMOS transistor P2, the drain of the ninth NMOS transistor N9, the drain of the tenth NMOS transistor N10, the drain of the eleventh NMOS transistor N11, and the drain of the fourth NMOS transistor N4, a gate of the ninth NMOS transistor N9, a gate of the tenth NMOS transistor N10, a gate of the eleventh NMOS transistor N11 is connected to the first adjustment terminal VTH1_ TRIM <2:0>, a source of the ninth NMOS transistor N9 is connected to the drain of the fifth NMOS transistor N5, a source of the tenth NMOS transistor N10 is connected to the drain of the sixth NMOS transistor N6, a source of the eleventh NMOS transistor N11 is connected to the drain of the seventh NMOS transistor N7, a gate of the fifth NMOS transistor N5, a gate of the sixth NMOS transistor N6, a gate of the seventh NMOS transistor N7, a drain of the eighth NMOS transistor N8 and a gate of the eighth NMOS transistor N8 are used for inputting the first reference current IREF1PU1, a source of the first PMOS transistor P1 and a source of the second PMOS transistor P2 are connected to a power supply terminal, a source of the second NMOS transistor N2, a source of the third NMOS transistor N5, a source of the fourth NMOS transistor N5, a source of the fifth NMOS transistor N5857324, a source of the fifth NMOS transistor N4623 and a source of the fifth NMOS transistor N4624 are connected to a power supply terminal VCC, The source of the sixth NMOS transistor N6, the source of the seventh NMOS transistor N7, and the source of the eighth NMOS transistor N8 are connected to ground.

The current transmitting unit 103 is specifically configured to generate a first current modulation signal S21 through the first adjusting terminal VTH1_ TRIM <2:0>, and send the first current modulation signal S21 to the current receiving unit 104 through the control signal EN.

Specifically, the current transmitting unit 103 may be controlled to generate the first current modulation signal S21 by configuring different values for the first adjusting terminal VTH1_ TRIM <2:0>, wherein the first current modulation signal S21 may have a magnitude range of 300uA to 1000uA (microampere), i.e., the first adjusting terminal VTH1_ TRIM <2:0> adjusts the first current modulation signal S21 within an adjusting range of 300uA to 1000uA, and the adjusting step thereof may be 100 uA/bit. After generating the first current adjustment signal S21, the first NMOS transistor N1 may be controlled to be turned on by the control signal EN, so that the first current adjustment signal S21 is transmitted to the current receiving unit 104 through the first NMOS transistor N1, thereby achieving simulation of the transmitting function of the SWP slave interface, the current receiving unit 104 may receive the first current modulation signal S21 based on a current threshold and output a digital modulation signal according to the received first current modulation signal S21, and the performance detecting unit 105 detects the performance of the SWP master interface circuit 100 according to the digital modulation signal, so as to complete on-line automatic evaluation of the circuit performance.

Specifically, the ninth NMOS transistor N10, the tenth NMOS transistor N10, and the eleventh NMOS transistor N11 may be controlled to turn on and off by configuring different values for the first adjusting terminal VTH1_ TRIM <2:0> to amplify the first reference current IREF1PU1 to generate the first current modulation signal S21, and different first current modulation signals may correspond to the second current modulation signal S2 simulating the SWP slave interface emission of different UICCs, so as to complete the simulation of the SWP slave interface emission function, thereby achieving the automatic evaluation and test of the circuit performance of the SWP master interface, and reducing the cost of the post evaluation and test.

It should be noted that, in order to implement the adjustment of the current threshold by the threshold adjustment unit 106, the embodiment of the present disclosure proposes a structure of the threshold adjustment unit 106, and the following description continues with reference to fig. 2B.

In an embodiment of the present disclosure, as shown in fig. 2B, the threshold adjusting unit 106 may include: a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, a seventeenth NMOS transistor N17, and an eighteenth NMOS transistor N18.

Wherein the gate of the twelfth NMOS transistor N12, the drain of the twelfth NMOS transistor N12, the gate of the thirteenth NMOS transistor N13, the gate of the fourteenth NMOS transistor N14, and the gate of the fifteenth NMOS transistor N15 are used to input the second reference current IREF1PU2, the drain of the thirteenth NMOS transistor N13 is connected to the source of the sixteenth NMOS transistor N16, the drain of the fourteenth NMOS transistor N14 is connected to the source of the seventeenth NMOS transistor N17, the drain of the fifteenth NMOS transistor N15 is connected to the source of the eighteenth NMOS transistor N18, the gate of the sixteenth NMOS transistor N16, the gate of the seventeenth NMOS transistor N17, and the gate of the eighteenth NMOS transistor N18 are connected to the second adjustment terminal VTH2_ TRIM <2:0>, the drain of the sixteenth NMOS transistor N16, the seventeenth NMOS transistor N17, and the drain of the eighteenth NMOS transistor N39n 18 are connected to the current receiving unit 104 (not shown in fig. 2B, i.e., the second node d2 is connected to the current receiving unit 104 in fig. 2B), the source of the twelfth NMOS transistor N12, the source of the thirteenth NMOS transistor N13, the source of the fourteenth NMOS transistor N14, and the source of the fifteenth NMOS transistor N15 are connected to the ground terminal GND.

The threshold adjusting unit 106 is specifically configured to adjust the current threshold through the second adjusting terminal VTH2_ TRIM <2:0 >.

Further, the adjustment range of the current threshold can be 0 uA-700 uA (microampere), and the adjustment step can be 100 uA/bit.

In one embodiment of the present disclosure, as shown in fig. 2C, the SWP master interface circuit 100 may further include: the electrostatic protection unit 107.

Referring to fig. 2C, the electrostatic protection unit 107 may include: a first diode D1, a second diode D2, and a first resistor R1.

One end of the first resistor R1 is connected to the SWP main interface 101 (SWP-IO interface in fig. 2C), the other end of the first resistor R1 is connected to the anode of the first diode D1, the cathode of the second diode D2, the voltage pulse transmitting unit 102 and the current receiving unit 104, the cathode of the first diode D1 is connected to the power supply terminal VCC, and the anode of the second diode D2 is connected to the ground terminal.

Further, referring to fig. 2C, the voltage pulse transmitting unit 102 may include: the first buffer BUF1 includes a third PMOS transistor P3, a nineteenth NMOS transistor N19, and a second resistor R2.

An input end of the first buffer BUF1 is configured to receive a voltage modulation signal SWP _ S1, an output end of the first buffer BUF1 is connected to a gate of the third PMOS transistor P3 and a gate of the nineteenth NMOS transistor N19, respectively, a drain of the third PMOS transistor P3 is connected to one end of the second resistor R2, another end of the second resistor R2 is connected to a drain of the nineteenth NMOS transistor N19, an anode of the first diode D1, and the current receiving unit 104, a source of the third PMOS transistor P3 is connected to the current receiving unit 104 and the power supply terminal VCC, respectively, and a source of the nineteenth NMOS transistor N19 is connected to the ground. It is to be understood that, referring to fig. 2C, the power supply terminal of the first buffer BUF1 is connected to the power supply terminal VCC, and the ground terminal of the first buffer BUF1 is connected to the ground terminal.

Referring to fig. 2C, the current receiving unit 104 may include: a fourth PMOS transistor P4, a third resistor R3, a comparator COM, and a second buffer BUF 2.

The gate of the fourth PMOS transistor P4 is connected to ground, the source of the fourth PMOS transistor P4 is connected to the source of the third PMOS transistor P3, the drain of the fourth PMOS transistor P4 is connected to one end of the third resistor R3, the positive input terminal of the comparator COM is connected to the other end of the third resistor R3 and the threshold adjusting unit 106, the negative input terminal of the comparator COM is connected to the positive electrode of the first diode D1 and the current emitting unit 103, and the output terminal of the comparator COM is connected to the input terminal of the second buffer BUF 2. It is understood that the power supply terminal of the second buffer BUF2 and the power supply terminal of the comparator COM are both connected to the power supply terminal, and the ground terminal of the second buffer BUF2 and the ground terminal of the comparator COM are both connected to the ground terminal.

Specifically, while the SWP master interface 101 is transmitting the voltage pulse modulated signal S1, the SWP master interface 101 may receive the current modulated signal S2 transmitted by the SWP slave interface. The threshold adjusting unit 106 can adjust the current threshold, the comparator COM outputs a high level signal or a low level signal according to the magnitude relation between the adjusted current threshold and the current modulation signal S2, and the output signal of the comparator COM is converted into the signal SWP _ S2 through the second buffer BUF 2.

Specifically, the current magnitude range of the current modulation signal S2 may be 0uA to 1000uA (microampere), the adjustment step may be 100uA/bit, and when the current modulation signal S2 is greater than the current threshold, the output signal of the comparator COM is a high level signal; when the current modulation signal S2 is less than or equal to the current threshold, the output signal of the comparator COM is a low level signal.

According to the embodiment of the disclosure, the variation of the current threshold caused by the deviation of the manufacturing process is compensated through the second adjusting terminal TRIM VTH2_ TRIM <2:0>, so that the automatic calibration of the current threshold received by the SWP main interface can be realized, and the performance of the product is improved.

It should be noted that the first node d1 in fig. 2A is connected to the first node d1 in fig. 2C, and the second node d2 in fig. 2B is connected to the second node d2 in fig. 2C, so as to form the SWP main interface circuit according to an embodiment of the disclosure, that is, the drain of the first NMOS transistor N1 in fig. 2A is connected to the drain of the nineteenth NMOS transistor N19 in fig. 2C, and the drain of the sixteenth NMOS transistor N16, the drain of the seventeenth NMOS transistor N17, and the drain of the eighteenth NMOS transistor N18 in fig. 2B are connected to the positive input terminal of the comparator COM in fig. 2C.

The operation of the SWP host interface circuit is described below by way of a specific example.

Referring to fig. 2A to 2C, after passing through the first buffer BUF1, the digital modulation signal SWP _ S1 drives the third PMOS transistor P3 and the nineteenth NMOS transistor N19 to turn on and off, and transmits the digital modulation signal SWP _ S1 to the SWP slave interface of the UICC via the SWP _ IO port, thereby completing the UICC transmitting function.

While the voltage pulse modulation signal S1 transmitted by the SWP master interface 101 is at a high level, the SWP master interface circuit may receive the current modulation signal S2 transmitted by the SWP slave interface through the SWP _ IO port, and may set: the resistance ratio of R2 and R3 is 1 to 100, the width-length ratio of the P3 and P4 transistors is 100 to 1, the first reference current and the second reference current are both 1uA, IREF1PU1 is IREF1PU2 is 1uA, different values (i.e., VTH2_ TRIM <2:0> is 000 to 111) can be configured for the second adjusting terminal, the adjustable range of the current threshold value received by the SWP main interface circuit can be 100uA to 700uA, and the adjustment precision can be 100uA/bit, for example: VTH2_ TRIM <2:0> -100, when the current signal S2 is greater than 400uA, the COM comparator output is high, otherwise, it is low, the sampling signal is transmitted to the second buffer BUF2, so that the second buffer BUF2 outputs the signal SWP _ S2. If the SWP _ S2 is at a high level, it indicates that the SWP transmits a logic "1" from the interface, that is, the magnitude range of the current signal is 600uA to 1 mA; if SWP _ S2 is low, it indicates that SWP is transmitting a logic "0" from the interface, i.e., the magnitude of the current signal ranges from-20 uA to 0uA, thereby completing the receiving function.

It should be noted that the adjustment range and the adjustment precision of the current threshold in the embodiment of the present disclosure may be determined according to actual requirements, and the size, the range and the adjustment precision of the current threshold are merely exemplary and do not constitute a limitation to the present disclosure.

Therefore, a receiving threshold adjusting circuit is introduced into the SWP main interface circuit, so that the current threshold can be adjusted through the VTH2_ TRIM <2:0> port, the current threshold is compensated to change along with the change of the process, and the receiving performance is improved.

It should be noted that the output signal SWP _ S2 of the second buffer BUF2 can be digitally demodulated to obtain correct data transmitted from the SWP interface. Based on this, the present disclosure proposes the following embodiments.

That is, in one embodiment of the present application, the SWP master interface circuit 100 may further include: and the digital demodulation unit is connected with the output end of the current receiving unit 104 and is used for demodulating the output signal output by the current receiving unit 104 so as to analyze the data sent by the SWP from the interface.

Wherein, the output terminal of the current receiving unit 104 can be the output terminal of its second buffer BUF2, that is to say, the output terminal of the second buffer BUF2 can be connected with the digital demodulation unit.

Specifically, the second buffer BUF2 transmits its output signal SWP _ S2 to the digital demodulation unit, and the numerical demodulation unit performs digital demodulation on the output signal to analyze correct data sent by the SWP slave interface, complete the receiving function of the current modulation signal S2, and implement data reception, thereby improving the receiving accuracy.

To sum up, the SWP main interface circuit of the embodiment of the disclosure can realize the detection and evaluation of the circuit performance through the current transmitting unit and the performance detecting unit, reduce the cost of the evaluation test in the later period, compensate the change of the current threshold along with the change of the process by adjusting the current threshold, reduce the interference signal, improve the yield of the product, and has the advantages of simple structure and easy integration.

The above embodiments are merely illustrative of the basic idea of the present invention, and the constituent circuits related to the present invention are not drawn in terms of the number of constituent circuits, shapes, arrangement of devices, and connection modes in actual implementation. The actual implementation of the method can be changed freely according to the type, number, connection mode, device arrangement mode and device parameters of each circuit.

The embodiment of the disclosure also provides a terminal. Fig. 3 is a schematic structural diagram of a terminal according to an embodiment of the present disclosure.

As shown in fig. 3, the terminal 1000 includes the SWP main interface circuit 100 proposed in the above embodiment.

It should be noted that the terminal 1000 may be an intelligent device such as a mobile phone, a bracelet, and a computer.

The terminal of the embodiment of the disclosure can realize the automatic detection of the performance of the SWP main interface circuit through the transmitting function of the analog current through the SWP main interface circuit, thereby reducing the test cost of the circuit in the later period.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, "a plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present disclosure in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present disclosure.

The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.

It should be understood that portions of the present disclosure may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.

In addition, functional units in the embodiments of the present disclosure may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure, and that changes, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present disclosure.

Claims (8)

1. An SWP host interface circuit, comprising:

an SWP host interface;

the voltage pulse transmitting unit is connected with the SWP main interface and used for controlling the SWP main interface to send a voltage pulse signal to the SWP slave interface;

the current transmitting unit is connected with the voltage pulse transmitting unit and used for generating a first current modulation signal and sending the first current modulation signal to the current receiving unit;

the current receiving unit is respectively connected with the SWP main interface, the voltage pulse transmitting unit and the current transmitting unit, and is used for receiving a first current modulation signal based on a current threshold value, outputting a digital modulation signal according to the received first current modulation signal, and receiving a second current modulation signal sent by the SWP slave interface from the SWP main interface based on the current threshold value when the SWP main interface sends a voltage pulse signal;

the threshold adjusting unit is connected with the current receiving unit and is used for adjusting the current threshold;

and the performance detection unit is connected with the current receiving unit and is used for detecting the performance of the SWP main interface circuit according to the digital modulation signal.

2. The circuit of claim 1, wherein the current transmitting unit comprises:

a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a first PMOS transistor, and a second PMOS transistor;

the drain of the first NMOS transistor is connected to the voltage pulse transmitting unit, the SWP main interface, and the current receiving unit, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the gate of the first NMOS transistor is used for inputting a control signal, the gate of the second NMOS transistor is connected to the gate of the third NMOS transistor, the drain of the third NMOS transistor, and the drain of the first PMOS transistor, the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, the drain of the ninth NMOS transistor, the drain of the tenth NMOS transistor, the drain of the eleventh NMOS transistor, and the drain of the fourth NMOS transistor, the gate of the ninth NMOS transistor, the gate of the tenth NMOS transistor, and the gate of the eleventh NMOS transistor are connected to the first adjusting terminal, a source of the ninth NMOS transistor is connected to a drain of the fifth NMOS transistor, a source of the tenth NMOS transistor is connected to a drain of the sixth NMOS transistor, a source of the eleventh NMOS transistor is connected to a drain of the seventh NMOS transistor, the gate of the fifth NMOS transistor, the gate of the sixth NMOS transistor, the gate of the seventh NMOS transistor, the drain of the eighth NMOS transistor, and the gate of the eighth NMOS transistor are used for inputting a first reference current, the source electrode of the first PMOS transistor and the source electrode of the second PMOS transistor are connected with a power supply end, the source electrode of the second NMOS transistor, the source electrode of the third NMOS transistor, the source electrode of the fourth NMOS transistor, the source electrode of the fifth NMOS transistor, the source electrode of the sixth NMOS transistor, the source electrode of the seventh NMOS transistor and the source electrode of the eighth NMOS transistor are connected with a ground end;

the current transmitting unit is specifically configured to generate a first current modulation signal through the first adjusting terminal, and send the first current modulation signal to the current receiving unit through the control signal.

3. The circuit of claim 1, wherein the threshold adjustment unit comprises:

a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, and an eighteenth NMOS transistor;

the gate of the twelfth NMOS transistor, the drain of the twelfth NMOS transistor, the gate of the thirteenth NMOS transistor, the gate of the fourteenth NMOS transistor, and the gate of the fifteenth NMOS transistor are used for inputting a second reference current, the drain of the thirteenth NMOS transistor is connected to the source of the sixteenth NMOS transistor, the drain of the fourteenth NMOS transistor is connected to the source of the seventeenth NMOS transistor, the drain of the fifteenth NMOS transistor is connected to the source of the eighteenth NMOS transistor, the gate of the sixteenth NMOS transistor, the gate of the seventeenth NMOS transistor, and the gate of the eighteenth NMOS transistor are connected to a second regulation terminal, the drain of the sixteenth NMOS transistor, the drain of the seventeenth NMOS transistor, and the drain of the eighteenth NMOS transistor are connected to the current receiving unit, and the source of the twelfth NMOS transistor is connected to the current receiving unit, The source electrode of the thirteenth NMOS transistor, the source electrode of the fourteenth NMOS transistor and the source electrode of the fifteenth NMOS transistor are connected with the ground end;

the threshold adjusting unit is specifically configured to adjust the current threshold through the second adjusting terminal.

4. The circuit of claim 1, further comprising: an electrostatic protection unit;

the electrostatic protection unit includes: a first diode, a second diode and a first resistor; wherein,

one end of the first resistor is connected with the SWP main interface, the other end of the first resistor is respectively connected with the anode of the first diode, the cathode of the second diode, the voltage pulse transmitting unit, the current transmitting unit and the current receiving unit, the cathode of the first diode is connected with a power supply end, and the anode of the second diode is connected with a ground end.

5. The circuit of claim 4, wherein the voltage pulse transmitting unit comprises: a first buffer, a third PMOS transistor, a nineteenth NMOS transistor, and a second resistor; wherein,

the input end of the first buffer is used for receiving a voltage modulation signal, the output end of the first buffer is respectively connected with the grid electrode of the third PMOS transistor and the grid electrode of the nineteenth NMOS transistor, the drain electrode of the third PMOS transistor is connected with one end of the second resistor, the other end of the second resistor is respectively connected with the drain electrode of the nineteenth NMOS transistor, the anode of the first diode, the current transmitting unit and the current receiving unit, the source electrode of the third PMOS transistor is respectively connected with the current receiving unit and a power supply end, and the source electrode of the nineteenth NMOS transistor is connected with the ground end.

6. The circuit of claim 5, wherein the current receiving unit comprises: a fourth PMOS transistor, a third resistor, a comparator and a second buffer; wherein,

the gate of the fourth PMOS transistor is connected to ground, the source of the fourth PMOS transistor is connected to the source of the third PMOS transistor, the drain of the fourth PMOS transistor is connected to one end of the third resistor, the positive input end of the comparator is connected to the other end of the third resistor and the threshold adjusting unit, the negative input end of the comparator is connected to the anode of the first diode and the current emitting unit, and the output end of the comparator is connected to the input end of the second buffer.

7. The circuit of any of claims 1-6, further comprising:

and the digital demodulation unit is connected with the output end of the current receiving unit and is used for demodulating the output signal output by the current receiving unit so as to analyze the data sent by the SWP from the interface.

8. A terminal, characterized in that it comprises a SWP master interface circuit according to any of claims 1-7.

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