CN203858844U

CN203858844U - Driving circuit, display device and electronic equipment

Info

Publication number: CN203858844U
Application number: CN201420205055.1U
Authority: CN
Inventors: 蒋新喜; 莫良华; 张鹏
Original assignee: FocalTech Systems Ltd
Current assignee: Dun Tai Electronics Co Ltd
Priority date: 2014-04-24
Filing date: 2014-04-24
Publication date: 2014-10-01
Anticipated expiration: 2024-04-24
Also published as: TWM500968U

Abstract

The utility model provides a driving circuit, a display device and electronic equipment. The driving circuit comprises a clock signal generating unit and a control unit, wherein the clock signal generating unit generates clock signals, variation from a first level to a second level in each clock signal is used for triggering a scan driving circuit to generate scanning signals transmitted by scanning lines correspondingly, the variation from the first level to the second level is defined to be effective signal edges of the clock signals, and the time between the adjacent effective signal edges is the clock time; and the control unit controls the clock time of the clock signals to be not completely identical, the clock time comprises first clock time and second clock time, the second clock time is greater than the first clock time, and the control unit is further used for controlling the clock time to reach the second clock time at least once in the process of displaying a frame image by a display panel. The display device and the electronic equipment comprise the driving circuit. According to the driving circuit, the display device and the electronic equipment, the noise caused by electromagnetic interference in the display panel can be reduced.

Description

Drive circuit, display device, and electronic apparatus

Technical Field

The utility model relates to an integrated electronics field especially relates to a drive circuit, display device and electronic equipment.

Background

With the increasing demand for the integration of electronic devices, the display device is often integrated with other electronic devices in an electronic device. For example, the display device and the touch device are integrated into a mobile phone for realizing touch display. However, when the display device displays, the voltage and current in the driving signal may change with time, thereby generating electromagnetic interference. The electromagnetic interference is a noise signal of other electronic devices integrated with the display device.

SUMMERY OF THE UTILITY MODEL

The utility model provides a problem provide a drive circuit, display device and electronic equipment to reduce display device's electromagnetic interference to other electron device's influence.

In order to solve the above problem, the present invention provides a driving circuit for driving a display panel to display images, wherein the display panel includes a plurality of display units and a plurality of scan lines, each scan line is connected to the plurality of display units, and the plurality of scan lines are used for transmitting a scan signal provided by a scan driving circuit to the plurality of display units to activate the display units connected to the scan lines to display images; the drive circuit includes: the scanning driving circuit is used for generating scanning signals correspondingly transmitted by each scanning line, the change from the first level to the second level is defined as an effective signal edge of the clock signal, and the time between adjacent effective signal edges is clock time; the control unit is used for controlling the clock time of the clock signal to be not completely the same, the clock time comprises a first clock time and a second clock time, the second clock time is greater than the first clock time, and the control unit is also used for controlling the clock time to reach the second clock time at least once in the process that the display panel displays one frame of image.

Optionally, the duration of the second level in the clock signal generated by the clock signal generation unit is the same as the duration of the scan signal generated by the scan driving circuit; the control unit is configured to control each time duration of occurrence of the first level of the clock signal to be not completely the same, where the time duration includes a first time duration and a second time duration, and the second time duration is greater than the first time duration, and the control unit is further configured to control the time duration of the first level to reach the second time duration at least once during a process that a display panel displays one frame image, a sum of the first time duration of the first level and the time duration of the second level is the first clock time, and a sum of the second time duration of the first level and the time duration of the second level is the second clock time.

Optionally, the clock signal generating unit is configured to generate two clock signals, so that the scan driving circuit performs progressive scanning on the scan lines connected to the scan driving circuit; the first duration of the first level of one of the two clock signals is the same as the duration of the second level of the other clock signal; the control unit is used for controlling the duration of the first level of the two clock signals for a second duration at least once in the process that the display panel displays one frame of image.

Optionally, the scan driving circuit includes: the scanning circuit comprises a first sub-scanning driving circuit and a second sub-scanning driving circuit, wherein the first sub-scanning driving circuit is used for scanning a first group of scanning lines line by line, the second sub-scanning driving circuit is used for scanning a second group of scanning lines line by line, and the first group of scanning lines and the second group of scanning lines are adjacent scanning lines; the clock signal generating unit is used for generating a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, and the first clock signal and the third clock signal are used for triggering the first sub-scanning driving circuit to scan a first group of scanning lines line by line; the second clock signal and the fourth clock signal are used for triggering the second sub-scanning driving circuit to perform line-by-line scanning on a second group of scanning lines; a first duration of a first level of one of the first clock signal and a third clock signal is the same as a second level duration of the other, a first duration of a first level of one of the second clock signal and a fourth clock signal is the same as a second level duration of the other, an overlap exists between the first clock signal and the second clock signal, and an overlap exists between the third clock signal and the fourth clock signal; the control unit is used for controlling the duration of the first level of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal for a second duration at least once in the process of displaying one frame of image by the display panel.

Optionally, the scan driving circuit includes: the scanning circuit comprises a first sub-scanning driving circuit and a second sub-scanning driving circuit, wherein the first sub-scanning driving circuit is used for scanning a first group of scanning lines line by line, the second sub-scanning driving circuit is used for scanning a second group of scanning lines line by line, and the first group of scanning lines and the second group of scanning lines are adjacent scanning lines; the clock signal generating unit is used for generating a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, and the first clock signal and the third clock signal are used for triggering the first sub-scanning driving circuit to scan a first group of scanning lines line by line; the second clock signal and the fourth clock signal are used for triggering the second sub-scanning driving circuit to perform line-by-line scanning on a second group of scanning lines; the control unit is used for controlling the time durations of the occurrence of the second levels of the first clock signal and the third clock signal not to be completely the same, the time durations comprise a first time duration and a second time duration, and the second duration is longer than the first duration, and the respective durations for controlling the first levels of the second and fourth clock signals to occur are not exactly the same, the durations including a third duration and a fourth duration, and the fourth duration is longer than the third duration, the control unit is further used for displaying one frame of image on the display panel, controlling the second level duration of the first and third clock signals at least once for a second duration, the first level duration time of the second clock signal and the fourth clock signal reaches a fourth duration time; the sum of the duration of the first level of the first clock signal and the third clock signal and the first duration of the second level is the first clock time, and the sum of the duration of the first level and the second duration of the second level is the second clock time; the sum of the duration of the second level of the second clock signal and the fourth clock signal and the third duration of the first level is the first clock time, and the sum of the duration of the second level and the fourth duration of the first level is the second clock time.

Optionally, the sum of the durations of the first level and the second level in the clock signal generated by the clock signal generation unit is the same as the duration of the scan signal generated by the scan driving circuit; the control unit is used for controlling the duration time of the first level of the clock signal to occur not to be completely the same, the duration time comprises a first duration time and a second duration time, the second duration time is longer than the first duration time, the control unit is further used for controlling the duration time of the first level to reach the second duration time at least once in the process that the display panel displays one frame image, the sum of the first duration time of the first level and the duration time of the second level is the first clock time, and the sum of the second duration time of the first level and the duration time of the second level is the second clock time; or, the control unit is configured to control each time duration of occurrence of the second level of the clock signal to be not completely the same, where the time duration includes a first time duration and a second time duration, and the second time duration is greater than the first time duration, and the control unit is further configured to control the time duration of the second level for the second time duration at least once during a process that the display panel displays one frame image, a sum of the first time duration of the second level and the time duration of the first level is the first clock time, and a sum of the second time duration of the second level and the time duration of the first level is the second clock time.

Optionally, the plurality of scan lines are further configured to activate display of each frame image according to a frame synchronization signal provided by a frame synchronization signal unit; the scanning driving circuit is also used for providing a row synchronizing signal; the control unit is connected with the frame synchronization signal unit and the scanning drive circuit and used for judging whether to control the clock time of the clock signal to reach a second clock time or not according to the frame synchronization signal and the line synchronization signal.

Optionally, the control unit comprises: the memory is used for storing preset row information, and the preset row information is the row information of the corresponding scanning line when the clock time is controlled to reach the second clock time; the judging module is connected with the frame synchronizing signal unit, the scanning driving circuit and the memory and is used for judging whether the received line synchronizing signal meets the preset line information or not after receiving a frame synchronizing signal; and the control module is connected with the frame synchronization signal unit, the scanning driving circuit and the judging module and is used for enabling the clock time of the clock signal output by the clock signal generating unit to reach a second clock time when the judging module judges that the line synchronization signal meets the preset line information.

Optionally, the control module is further configured to send the line synchronization signal to the clock signal generation unit, so that the clock signal generation unit generates the clock signal; the control module is configured to stop providing the horizontal synchronization signal to the clock signal generation unit for a first preset time when the judgment module judges that the horizontal synchronization signal meets the preset horizontal information, so that the clock time of the clock signal reaches a second clock time.

Optionally, the control module is configured to form a stop signal when the determining module determines that the line synchronization signal meets the preset line information, where the stop signal includes an invalid signal and a valid signal; the clock signal generating unit is used for immediately enabling the output clock time to reach a second clock time when the stop signal is switched from the invalid signal to the valid signal; or, the clock signal generating unit is used for enabling the output clock time to reach a second clock time after a second preset time when the stop signal is switched from the invalid signal to the valid signal.

Optionally, the stop signal is a square wave signal composed of a third level and a fourth level, and the third level is different from the fourth level in potential; the third level is the active signal and the fourth level is the inactive signal; or, the fourth level is the valid signal, and the third level is the invalid signal.

Optionally, the clock signal generating unit includes: the initial pulse generating module is used for forming an initial pulse; the clock signal generating module is used for generating the clock signal according to the initial pulse; the reset signal generation module is used for forming a reset signal, and the reset signal is used for enabling the initial pulse generation module to output the initial pulse again after a third preset time; the control unit is connected with the reset signal generating module and is used for controlling the reset signal generating module to generate the reset signal at least once in the process of displaying one frame of image on the display panel, so that the clock time of the clock signal output by the clock signal generating module reaches a second clock time.

Optionally, the clock signal generating unit generates at least two clock signals, a second duration of a first level of the at least two clock signals overlaps, and a time that the second duration of the first level of the at least two clock signals overlaps is defined as a pause time, at which the first level of the at least two clock signals causes the scan driving circuit to pause scanning the scan lines, and the clock signal generated by the clock signal generating unit is used for causing the scan driving circuit to provide the scan signal to at least one row of scan lines before the pause time so as to scan the scan lines; the control unit is used for controlling the clock signal generating unit to generate a clock signal for enabling the scanning driving circuit to start scanning from the next row of scanning lines after the pause time.

Optionally, the clock signal generating unit generates at least two clock signals, wherein second durations of first levels of the at least two clock signals overlap, and a time during which the second durations of the first levels of the at least two clock signals overlap is defined as a pause time, and the first levels of the at least two clock signals cause the scan driving circuit to pause scanning the scan lines during the pause time; the clock signal generated by the clock signal generating unit is used for enabling the scanning driving circuit to provide scanning signals for at least one row of scanning lines before the pause time so as to scan the scanning lines; the control unit is used for controlling the clock signal generating unit to generate a clock signal for enabling the scanning driving circuit to start scanning from at least one last row of the scanned scanning lines after the pause time.

Optionally, the clock signal generating unit generates at least two clock signals, a first level of a part of the at least two clock signals is used for driving the scan driving circuit to generate the scan signal, a second level of another part of the at least two clock signals is used for driving the scan driving circuit to generate the scan signal, the second durations of the first levels of the at least two clock signals overlap, defining the time during which the second durations of the first levels of the at least two clock signals overlap as a pause time, and in the pause time, the scanning driving circuit is driven by a first level to generate the clock signal of the scanning signal so that the scanning driving circuit continuously scans the scanning line, and the scanning driving circuit is driven by a second level to generate the clock signal of the scanning signal so that the scanning driving circuit pauses to scan the scanning line.

Optionally, the driving circuit comprises the scan driving circuit.

Correspondingly, the utility model also provides a display device, include: the display panel comprises a plurality of display units and a plurality of scanning lines, wherein each scanning line is connected with the plurality of display units, and the plurality of scanning lines are used for transmitting scanning signals provided by a scanning driving circuit to the plurality of display units so as to activate the display units connected with the scanning lines to display images; drive circuit for drive display panel carries out image display, drive circuit does the utility model provides a drive circuit.

Optionally, the scan driving circuit is disposed on the display panel.

Optionally, the display panel is a liquid crystal display panel.

Correspondingly, the utility model also provides a display device, include: the display panel comprises a plurality of display units and a plurality of scanning lines, wherein each scanning line is connected with the plurality of display units, and the plurality of scanning lines are used for transmitting scanning signals provided by a scanning driving circuit to the plurality of display units so as to activate the display units connected with the scanning lines to display images;

the driving circuit is used for driving the display panel to display images, and the driving circuit is the driving circuit provided by the utility model; the display device further comprises a touch panel and a touch detection circuit connected with the touch panel, wherein the touch detection circuit performs touch detection on the touch panel during the pause time.

Optionally, the touch panel is either an external touch panel or an embedded touch panel.

Correspondingly, the utility model provides an electronic equipment, include: a display device, the display device comprising: the display panel comprises a plurality of display units and a plurality of scanning lines, wherein each scanning line is connected with the plurality of display units, and the plurality of scanning lines are used for transmitting scanning signals provided by a scanning driving circuit to the plurality of display units so as to activate the display units connected with the scanning lines to display images; drive circuit for drive display panel carries out image display, drive circuit does the utility model provides a drive circuit.

Optionally, the scan driving circuit is disposed on the display panel.

Optionally, the display panel is a liquid crystal display panel.

Optionally, the electronic device is a mobile phone, a tablet computer, a notebook computer or a desktop computer. .

Correspondingly, the utility model also provides an electronic equipment, include: the electronic equipment comprises a first device and a second device, wherein the first device is a display device, and the second device works in the pause time.

Optionally, the second device is a touch device.

Optionally, the touch device includes a touch detection circuit connected to the touch panel, and the touch detection circuit performs touch detection on the touch panel during the pause time.

Compared with the prior art, the technical scheme of the utility model have following advantage:

the control unit is used for controlling the clock time to reach the second clock time at least once in the process of displaying a frame image on the display panel, so that the time between adjacent effective signal edges can be prolonged, namely, the scanning circuit is not triggered to generate a scanning signal in a longer time, or the scanning signal scans the current scanning line in a longer time.

In an alternative, the clock times of the control clock signals are different by controlling the duration of the first level of the clock signals, i.e. the respective durations of time during which the first level of the clock signal occurs under the control of the control unit are not exactly the same, the respective durations comprising a first duration and a second duration, and the second duration is longer than the first duration, and during the process of displaying one frame of image on the display panel, controlling a duration of a first level of the clock signal at least once for a second duration, the scanning circuit is not triggered to generate the scanning signal for a longer time, or the scanning signal scans the current scanning line for a longer time, since the scanning signal on the scanning line is kept constant during this time, electromagnetic interference is not generated, and noise can be reduced.

Drawings

Fig. 1 is a functional block diagram of a first embodiment of the driving circuit of the present invention;

fig. 2 is a schematic diagram of an embodiment of a display device according to the present invention;

FIG. 3 is a schematic diagram of the output signals of the clock signal generation unit of FIG. 1;

fig. 4 is a schematic diagram of a second embodiment of the driving circuit of the present invention;

FIG. 5 is a schematic diagram of the control unit of FIG. 4;

FIG. 6 is a schematic scanning view of the control unit of FIG. 4;

FIG. 7 is a signal diagram formed by the driving circuit shown in FIG. 5;

FIG. 8 is another signal diagram formed by the driving circuit shown in FIG. 5;

fig. 9 is a schematic diagram of a third embodiment of the driving circuit of the present invention;

FIG. 10 is a diagram of a scan driving circuit;

FIG. 11 is a signal diagram of the drive circuit of FIG. 9;

fig. 12 is a schematic diagram of a fourth embodiment of the driving circuit of the present invention;

FIG. 13 is a signal schematic of the drive circuit of FIG. 12;

FIG. 14 is another signal schematic of the drive circuit of FIG. 12;

fig. 15 is a scanning schematic diagram of a fifth embodiment of the driving circuit of the present invention;

fig. 16 is a schematic diagram of an embodiment of an electronic device according to the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 1 and 2, fig. 1 and 2 respectively show a functional block diagram of a first embodiment of the driving circuit of the present invention and a schematic diagram of an embodiment of a display device of the present invention. The display device 1 includes a driving circuit 10, a display panel 20, a scan driving circuit 300, and a data line driving circuit (not shown). The driving circuit 10 is connected to the scan driving circuit 300. The scan driving circuit 300 and the data line driving circuit are connected to the display panel 20, respectively. The driving circuit 10 is used for driving the display panel 20 to display images. The display panel 20 includes a plurality of display units 201 and a plurality of scan lines G₁、G₂……G_NEach scanning line G₁、G₂……G_NConnecting a plurality of display units 201, the plurality of scanning lines G₁、G₂……G_NFor transmitting the scan signal provided by the scan driving circuit 300 to the plurality of display units 201 to activate and scan the line G₁、G₂……G_NThe connected display unit 201 performs image display.

Specifically, the display panel 20 may be a liquid crystal display panel or other suitable type of panel. The display unit 201 includes a Thin Film Transistor (TFT) (not shown) and a pixel electrode (not shown) connected to the TFT. The plurality of scanning lines G₁、G₂……G_NConnected to the gate electrode (not labeled) of the thin film transistor, the scan driving circuit 300 provides a scan signal for time-sharing turning on and scanning the line G₁、G₂……G_NTo activate and scan the line G₁、G₂……G_NThe connected display unit 201 supplies a data signal to the turned-on thin film transistor through a data line driving circuit to realize image display.

The driving circuit 10 of the present embodiment includes a clock signal generating unit 200 and a control unit 100 connected to the clock signal generating unit 200.

The clock signal generating unit 200 is configured to generate clock signals, each of the clock signals is a signal in which a first level and a second level appear alternately, potentials of the first level and the second level are different, and a change from the first level to the second level in the clock signals is used to trigger the scan driving circuit 300 to generate a scan signal correspondingly transmitted by each scan line, so that the display unit 201 correspondingly connected to each scan line is activated by the scan signal, and image display is further achieved.

And defining the change from the first level to the second level as an effective signal edge of the clock signal, wherein the time between adjacent effective signal edges is clock time. For example, if the first level is a low level and the second level is a high level, the active signal edge is a rising edge; or, the first level is a high level, the second level is a low level, and the effective signal edge is a falling edge.

The control unit 100 is configured to control the clock times of the clock signals to be different, where the clock times include a first clock time and a second clock time, and the second clock time is greater than the first clock time, and the control unit is further configured to control the clock times to reach the second clock time at least once during a process in which the display panel 20 displays one frame of image.

Alternatively, the duration of the second level in the clock signal generated by the clock signal generation unit 200 is the same as the duration of the scan signal generated by the scan driving circuit 300, and the control unit 100 may control the clock time of the clock signal by controlling the duration of the first level.

Specifically, the respective durations of the first level of the clock signal, which are used by the control unit 100 to control the first level of the clock signal to occur, are not all the same, and each of the respective durations includes a first duration and a second duration, and the second duration is longer than the first duration, and the control unit 100 is further used to control the duration of the first level of the clock signal to be the second duration at least once during the display of one frame of image by the display panel 20. The sum of the first duration of the first level and the duration of the second level is the first clock time, and the sum of the second duration of the first level and the duration of the second level is the second clock time. In this embodiment, the second duration preferably ranges from [9,400] microseconds (us), and the specific value is preferably 200 microseconds.

Fig. 3 shows a schematic diagram of an output signal of the clock signal generating unit 200 in fig. 1. The clock signal generating unit 200 is used for generating two clock signals CK1 and CK2, the two clock signals CK1 and CK2 are clock signals alternately output at a low level and a high level, and the clock signals CK1 and CK2 trigger the scan driving circuit 300 to generate the scan signal at the time of a rising edge (at the time of a low-level to high-level change). The rising edges are valid signal edges and the time between adjacent rising edges is the clock time.

In this embodiment, the first level of the two clock signals CK1 and CK2 is low level for controlling the scan driving circuit not to generate the scan signal, and the second level is high level for driving the scan driving circuit to generate the scan signal. In this embodiment, the low level is in the range of-15V to-7.5V, for example: the low level is-12V. The high level is in the range of 10V to 15V, for example: the high level is 15V.

In this embodiment, the first duration T1 of the low level of the clock signal CK1(CK2) is the same as the duration of the high level of the clock signal CK2(CK1), that is, the first duration T1 of the low level of the clock signal CK1(CK2) is the time when the clock signal CK2(CK1) drives the scan driving circuit 300 to generate the scan signal, so that the scan driving circuit 300 can scan the scan lines connected to the scan driving circuit 300 line by line.

The control unit 100 controls the duration T2 of the low level in the clock signals CK1 and CK2 for a second duration, the second duration T2 being greater than the first duration T1. The time when the second durations T2 of the low levels of the two clock signals CK1 and CK2 overlap is defined as a pause time, in which neither of the clock signals CK1 and CK2 has a rising edge, i.e., no change from low level to high level occurs, so that the scan driving circuit 300 is not activated to generate the scan signal, and the scan driving circuit 300 suspends scanning the scan lines.

As shown in FIG. 3, the scan signals generated by the scan driving circuit are driven by the clock signals CK1 and CK2 to scan the scan lines G_M、G_M+1After the scanning is finished, the scanning line G of the next row is suspended in the suspension time_M+2The scanning is performed until the second duration T2 of CK1 is over, and the low level is changed to the high level to trigger the scanning driving circuit 300 to scan the scanning line G_M+2Scanning is performed, accordinglyUntil the second duration T2 of CK2 is over, the low level is changed to the high level to trigger the scan driving circuit 300 to scan the line G_M+3A scan is performed.

That is, the display panel 20 pauses the scanning line G during the pause time₁、G₂……G_NThe display device 1 does not generate electromagnetic interference due to scanning line scanning, and other electronic devices integrated with the display device can perform operations such as detection during the scanning line scanning, so that the influence of noise can be reduced.

It should be noted that, as shown in fig. 3, the duration of the high level in the clock signals CK1 and CK2 generated by the clock signal generating unit 200 is the duration of the scan signal, in other embodiments, the duration of the high level in the clock signals CK1 and CK2 output by the clock signal generating unit 200 may also be made to reach the second duration under the control of the control unit 100, so that the scan signal scans the current scan line for a longer time.

Similarly, in other embodiments, the scan driving circuit may also be activated to generate the scan signal by a falling edge of the clock signal (when the high level changes to the low level), the control unit 100 controls the duration of the high level in the clock signals CK1 and CK2 for a second duration, that is, under the control of the control unit 100, the clock signals CK1 and CK2 output by the clock signal generating unit 200 have no falling edge for a longer time (pause time), and the clock signals CK1 and CK2 may not activate the scan driving circuit 300 to generate the scan signal for a longer time, so that the scan lines on the display panel 20 have a longer time without transmitting the scan signal, that is, the scan lines are suspended for a longer time, thereby reducing the noise generated by the electromagnetic interference.

In other embodiments, the duration of the low level in the clock signals CK1 and CK2 may be the duration of the scan signal, and the duration of the low level in the clock signals CK1 and CK2 output by the clock signal generating unit 200 may be controlled by the control unit 100 to reach a second duration, so that the scan signal scans the current scan line for a longer time.

Referring to fig. 2 and fig. 3, in the process of displaying one frame of image on the display panel 20, the driving circuit 10 of the present embodiment can pause the scanning line G one or more times₁、G₂……G_NTo suspend the scanning of the scanning line G₁、G₂……G_NThe number, time, and location of scans may be preset.

It should be noted that, in the embodiment shown in fig. 3, the duration of the second level in the clock signal generated by the clock signal generating unit 200 is the same as the duration of the scan signal generated by the scan driving circuit 300. However, the present invention is not limited to this, and in other embodiments, the sum of the durations of the first level and the second level in the clock signal generated by the clock signal generating unit 200 may be the same as the duration of the scan signal generated by the scan driving circuit 300.

Accordingly, the control unit 100 is configured to control each time duration of the first level of the clock signal occurring is not completely the same, the time duration includes a first time duration and a second time duration, and the second time duration is greater than the first time duration, the control unit 100 is further configured to control the time duration of the first level for the second time duration at least once during the display of one frame image by the display panel 20, the sum of the first time duration of the first level and the time duration of the second level is the first clock time, and the sum of the second time duration of the first level and the time duration of the second level is the second clock time. That is, the control unit 100 may implement the control of the clock time by controlling the duration of the first level.

Or, the control unit 100 is configured to control each time duration of occurrence of the second level of the clock signal to be not completely the same, where the time duration includes a first time duration and a second time duration, and the second time duration is greater than the first time duration, the control unit 100 is further configured to control the time duration of the second level for the second time duration at least once during a display of one frame image on the display panel, a sum of the first time duration of the second level and the time duration of the first level is the first clock time, and a sum of the second time duration of the second level and the time duration of the first level is the second clock time. That is, the control unit 200 may implement the control of the clock time by controlling the duration of the second level.

The clock time is controlled to prolong the time of generating the effective signal edge, so that the scanning driving circuit 300 is not triggered to generate the scanning signal in a long time, or the scanning signal scans the current scanning line in a long time.

Referring to fig. 4, a schematic diagram of a second embodiment of the driving circuit of the present invention is shown. It should be noted that the plurality of scan lines are further used for activating the display of each frame image according to the frame synchronization signal VS provided by a frame synchronization signal unit 302; the scan driving circuit 301 is further configured to provide a row synchronization signal HS _ GIP; the driving circuit of the present embodiment can set the position where the pause scanning occurs based on the frame sync signal VS and the row sync signal HS _ GIP.

Specifically, the control unit 101 in the driving circuit of this embodiment is connected to the scan driving circuit 301 of the frame synchronization signal unit 302 and the clock signal generating unit 201, and is configured to determine whether to control the duration of the first level of the clock signal CK to reach the second duration according to the frame synchronization signal VS and the line synchronization signal HS _ GIP. That is, the control unit 101 in the driving circuit of the present embodiment determines the position of the set pause time based on the frame sync signal VS and the row sync signal HS _ GIP.

For example, 1280 rows of scan lines need to be scanned during one frame of image display, and the control unit 101 controls the duration of the first level of the clock signal CK to reach the second duration every 64 rows of the sync signal HS _ GIP after receiving the frame sync signal VS, so as to form a pause time for pausing the scanning of the scan lines, thereby generating 19 pause times during one frame of image display.

However, the present invention is not limited to setting the pause time according to the frame sync signal VS and the line sync signal HS _ GIP, and in other embodiments, the control unit 101 may also determine the pause time according to other manners and generate the pause time by controlling the clock signal generating unit. For example, the control unit 101 may set a position where a pause time is generated according to time, for example, 10ms is required from the start of scanning of the 1 st row to the 1280 th row of scanning lines, and the control unit 101 may control the duration of the first level of the clock signal CK for a second duration at a timing from the start of scanning of the 1 st row to half (5ms) of the total scanning time to pause scanning of the scanning lines between the 64 th row and the 65 th row of scanning lines.

Referring to fig. 5 and 6 in combination, a schematic diagram and a scanning schematic diagram of the control unit of fig. 4 are shown, respectively. Specifically, the control unit 101 includes a memory 1011, a determination module 1012, and a control module 1013.

The memory 1011 is configured to store preset row information, where the preset row information is row information of a corresponding scan line when the clock time reaches a second clock time.

Specifically, in this embodiment, the preset row information is row information of a corresponding scan line when the duration of the first level of the clock signal CK is controlled to reach the second duration. However, the present invention is not limited to this, and in other embodiments, the preset row information may also be row information of a corresponding scan line when the duration of the second level of the control clock signal is longer.

For example, 1280 rows of scanning lines need to be scanned in the process of displaying one frame of image, the preset row information is that after the 64 th row of scanning lines and the 128 th row of scanning lines … … and the 1216 th row of scanning lines are finished, the duration of the first level of the clock signal is controlled for a second duration, so that after the 64 th row of scanning lines are finished and the 65 th row of scanning lines are scanned, … … between the 128 th row of scanning lines and the 129 th row of scanning lines are scanned, and after the 1216 th row of scanning lines are scanned and before the 1217 th row of scanning lines are scanned, the scanning lines are suspended for a pause time respectively.

Specifically, the memory 1011 is an editable memory, and can store different preset lines of information to meet the requirements of different electronic devices.

The determining module 1012 is connected to the frame synchronization signal unit 302, the scan driving circuit 301 and the memory 1011, and configured to determine whether the received row synchronization signal HS _ GIP satisfies the preset row information after receiving a frame synchronization signal VS.

For example, the preset row information is to control the duration of the first level of the clock signal CK for a second duration after the scan line of the 64 th row is completed, so as to suspend scanning the scan line within a suspension time. After the determining module 1012 receives the frame synchronization signal VS sent by the frame synchronization signal unit 302 and before the 64 th row synchronization signal HS _ GIP sent by the scan driving circuit 301 is received, the determining module 1012 determines that the row synchronization signal HS _ GIP does not satisfy the preset row information, and determines that the row synchronization signal HS _ GIP satisfies the preset row information when the 64 th row synchronization signal HS _ GIP sent by the scan driving circuit 301 is received.

The control module 1013 is connected to the frame synchronization signal unit 302, the scan driving circuit 301, and the determining module 1012, and configured to enable the duration of the first level output by the clock signal generating unit 201 to reach a second duration when the determining module 1012 determines that the row synchronization signal HS _ GIP satisfies the preset row information.

For example: the clock signal CK output by the clock signal generating unit 201 is a clock signal alternately output by a high level and a low level, a rising edge of the clock signal CK is used for activating the scan driving circuit 301 to generate the scan signal, and the control module 1013 may enable the low level output by the clock signal generating unit 201 to continue for a second duration so as not to form a rising edge for a longer period of time when the determination module 1012 determines that the row synchronizing signal HS _ GIP satisfies the preset row information, so as not to activate the scan driving circuit 301 to generate the scan signal, thereby reducing noise generated by electromagnetic interference.

It should be noted that the control module 1013 may implement the control on the clock signal generating unit 201 in various ways, and referring to fig. 7, a signal diagram formed by the driving circuit shown in fig. 5 is shown.

Specifically, the control module 1013 is further configured to send the row synchronization signal HS _ GIP to the clock signal generation unit 201. The clock signal generation unit 201 also generates the clock signal CK based on the synchronization signal HS _ GIP.

Here, the clock signal CK output by the clock signal generation unit 201 includes: the first clock signal CK1_ R, the second clock signal CK1_ L, the third clock signal CK2_ R, and the fourth clock signal CK2_ L enable the scan driving circuit 301 to form scan signals respectively supplied to four scan lines. As shown in fig. 7, the synchronization signal HS _ GIP includes a plurality of square wave signals, which are sequentially triggered to generate a first clock signal CK1_ R, a second clock signal CK1_ L, a third clock signal CK2_ R, and a fourth clock signal CK2_ L. Specifically, in the present embodiment, the falling edge of the square wave signal is used to trigger the formation of the clock signal CK.

The control module 1013 is configured to stop providing the horizontal synchronization signal HS _ GIP to the clock signal generation unit 201 for a first preset time when the determining module 1012 determines that the horizontal synchronization signal HS _ GIP satisfies the preset horizontal information, so that the duration of the first level of the clock signal reaches the second duration.

In fig. 7, rising edges of the first clock signal CK1_ R, the second clock signal CK1_ L, the third clock signal CK2_ R, and the fourth clock signal CK2_ L are used to trigger the scan driving circuit 301 to generate a scan signal, and the control module 1013 stops sending the row sync signal HS _ GIP corresponding to the next row of scan lines (e.g., the 65 th row of scan lines) to the clock signal generation unit 201 for a first preset time when the determination module 1012 determines that the row sync signal HS _ GIP satisfies the preset row information (e.g., determines that the row sync signal HS _ GIP corresponds to the row sync signal CK2_ L of the 64 th row of scan lines). In the first preset time, the clock signal generating unit 201 does not form a clock signal because it does not receive the row synchronizing signal HS _ GIP of the next row of scan lines (e.g., the 65 th row of scan lines), and further does not excite the scan driving circuit 301 to generate a scan signal for scanning the next row of scan lines (e.g., the 65 th row of scan lines), thereby reducing noise caused by electromagnetic interference. Until the first preset time, the control module 1013 sends the clock signal generating unit 201 the row synchronization signal HS _ GIP corresponding to the next row of scan lines (e.g., the 65 th row of scan lines) to scan the next row of scan lines (e.g., the 65 th row of scan lines).

In fig. 7, the time between the falling edge of CK2_ L and the rising edge of CK1_ R is the time when the first clock signal CK1_ R, the second clock signal CK1_ L, the third clock signal CK2_ R, and the fourth clock signal CK2_ L overlap, and is a pause time during which the scan driving circuit 301 pauses scanning the scan lines.

The control of the clock signal generating unit 201 by the control unit may also be implemented in other ways, and referring to fig. 8, another signal diagram formed by the driving circuit shown in fig. 5 is shown. The control unit 101 in this embodiment controls the clock signal generating unit 201 by setting the STOP signal STOP.

Specifically, the control module 1013 in the control unit 101 is configured to form a STOP signal STOP when the determination module 1012 determines that the line synchronization signal HS _ GIP satisfies the preset line information, where the STOP signal STOP includes an invalid signal and a valid signal, where the invalid signal does not affect the clock signal CK generated by the clock signal generation unit 201, the invalid signal is switched to the valid signal for triggering control of the clock signal CK, and the valid signal lasts for a time period related to a second duration of the first level in the clock signal.

In this embodiment, the stop signal is a square wave signal configured by a third level (low level) and a fourth level (high level), and the third level is different from the fourth level in potential. Wherein, the low level is an invalid signal, and the high level is an effective signal. As shown in fig. 8, after the STOP signal STOP switches from the low level to the high level, the clock signal generating unit 201 further outputs a third clock signal CK2_ R and a fourth clock signal CK2_ L based on S1 and S2 in the row sync signal HS _ GIP, and then no longer outputs the clock signal CK, so as to enter a pause time capable of pausing the scanning of the scan lines. That is, in the present embodiment, the clock signal generating unit 201 is configured to enable the duration of the first level of the output CK2_ L to be the second duration after the second preset time when the STOP signal STOP is switched from the inactive signal (low level) to the active signal (high level), with a pause time between the falling edge of CK2_ L and the rising edge of CK _ 1R.

With continued reference to fig. 8, when the STOP signal STOP switches from the active signal (high level) to the inactive signal (low level), the clock signal generating unit 201 immediately outputs the clock signal CK (specifically, the first clock signal CK1_ R), that is, immediately restores the first duration when the STOP signal STOP switches from the active signal to the inactive signal.

However, the present invention is not limited to this, and in other embodiments, the clock signal generating unit 201 may also immediately make the duration of the output first level reach the second duration when the stop signal is switched from the inactive signal to the active signal. Or, the first duration of the first level is restored after a preset time after the STOP signal STOP is switched from the active signal to the inactive signal.

Furthermore, the utility model discloses do not do the restriction to the form of STOP signal STOP, except square wave signal, can be notch cuttype signal, trapezoidal signal etc. should not restrict with this the utility model discloses.

Referring to fig. 9, fig. 10 and fig. 11, a schematic diagram of a third embodiment of the driving circuit of the present invention, a scanning driving circuit and a signal schematic diagram of the driving circuit shown in fig. 9 are respectively shown.

In this embodiment, as shown in fig. 10, the scan driving circuit includes: a first sub-scanning drive circuit (not shown) for scanning odd-numbered scanning lines line by line, and a second sub-scanning drive circuit (not shown) for scanning even-numbered scanning lines line by line.

The same parts of the driving circuit of this embodiment as those of the driving circuit of the first embodiment are not repeated, and the clock signal generating unit 202 of the driving circuit of this embodiment includes:

an initial pulse generating module 2021, configured to form a first initial pulse SP _ L and a second initial pulse SP _ R; at the beginning of each frame of image display, the first initial pulse SP _ L and the second initial pulse SP _ R are locked in the shift register RS Cell connected to the scan lines G1 and G2, and are used for propagating to the shift register RS Cell of the next row in the subsequent scanning process of other scan lines until the scanning of one frame is completed.

A clock signal generating module 2022, configured to generate a first clock signal CK1_ R, a second clock signal CK1_ L, a third clock signal CK2_ R and a fourth clock signal CK2_ L according to the first initial pulse SP _ L and the second initial pulse SP _ R. Specifically, the clock signal generating module 2022 starts to sequentially output the first clock signal CK1_ R, the second clock signal CK1_ L, the third clock signal CK2_ R, and the fourth clock signal CK2_ L after the initial pulse generating module 2021 sends out the first initial pulse SP _ L and the second initial pulse SP _ R.

The first clock signal CK1_ R and the third clock signal CK2_ R are used for triggering the first sub-scanning driving circuit to scan odd-numbered scanning lines row by row; the second clock signal CK1_ L and the fourth clock signal CK2_ L are used for triggering the second sub-scanning driving circuit to scan even rows of scanning lines row by row;

a first duration of a first level of one of the first clock signal CK1_ R and a third clock signal CK2_ R is the same as a second level duration of the other, a first duration of a first level of one of the second clock signal CK1_ L and a fourth clock signal CK2_ L is the same as a second level duration of the other, the first clock signal CK1_ R overlaps with the second level duration of the second clock signal CK1_ L, the third clock signal CK2_ R overlaps with the second level duration of the fourth clock signal CK2_ L; the control unit 103 is used to control the duration of the first level of the first, second, third and fourth clock signals CK1_ R, CK1_ L, CK2_ R and CK2_ L for a second duration at least once during the display of one frame image by the display panel.

Specifically, the clock signal generation unit 202 in the driving circuit of the present embodiment further includes a RESET signal generation module 2023 for forming a RESET signal RESET _ L, RESET _ R, the RESET signal RESET _ L, RESET _ R is used for enabling the initial pulse generation module 2021 to re-output the initial pulse after a third preset time, so that the clock signal generation module 2022 outputs the first clock signal CK1_ R, the second clock signal CK1_ L, the third clock signal CK2_ R and the fourth clock signal CK2_ L again after re-outputting the pulse signals. In the third preset time, the signal output by the clock signal generating module 2022 is at a low level for a duration of the second duration, so that during this time, the scan driving circuit suspends scanning the scan lines, and noise generated by electromagnetic interference is reduced.

The control unit 102 is connected to the RESET signal generating module 2023, and configured to control the RESET signal generating module 2023 to generate the RESET signal RESET _ L, RESET _ R at least once during a process that the display panel displays an image frame, so that the first level of the clock signal output by the clock signal generating module 2022 reaches a second duration, thereby suspending scanning a scanning line at least once during the process of an image frame, and reducing the problem of electromagnetic interference.

In other embodiments, the first sub-scanning driving circuit may be further configured to scan even-numbered scan lines line by line, and the second sub-scanning driving circuit may be further configured to scan odd-numbered scan lines line by line. Modifications and variations can be made by those skilled in the art in light of the embodiments illustrated in fig. 9, 10 and 11.

Referring to fig. 12 and 13, a schematic diagram of a fourth embodiment of the driving circuit of the present invention and a signal schematic diagram of the driving circuit in fig. 12 are respectively shown. In this embodiment, the clock signal generating unit 203 includes a plurality of clock signal generators for providing a plurality of clock signals. Specifically, the clock signal generation unit 203 includes a first clock signal generator 2031, a second clock signal generator 2032, a third clock signal generator 2033, and a fourth clock signal generator 2034.

The first clock CK1_ R, the second clock CK1_ L, the third clock CK2_ R and the fourth clock CK2_ L have the same frequency and amplitude, sequentially change from a low level to a high level, and sequentially change from the high level to the low level, so that the scanning driving circuit can provide scanning signals to four rows of scanning lines at a time, respectively, so as to scan the four rows of scanning lines at a time, reduce the time of one frame of image, and improve the image display efficiency.

The control unit 103 is connected to the first, second, third and fourth clock signal generators 2031, 2032, 2033 and 2034, and is configured to control the low level of the first, second, third and fourth clocks CK1_ R, CK1_ L, CK2_ R and CK2_ L for a second duration at least once during a process of displaying a frame image on the display panel.

Between the falling edge of the fourth clock signal CK2_ L and the rising edge of the first clock CK1_ R that recovers the first duration T, the time that the first clock CK1_ R, the second clock CK1_ L, the third clock CK2_ R, and the fourth clock CK2_ L overlap is defined as a pause time in which the first clock signal generator 2031, the second clock signal generator 2032, the third clock signal generator 2033, and the fourth clock signal generator 2034 are kept at a low level for a long time, and the scan driving circuit is not triggered to provide the scan signal to any scan line, so that no electromagnetic interference is generated during the pause time, and the noise is reduced.

It should be noted that, the present invention does not limit the number of clock signal generators in the clock signal generating unit 203, and the clock signal generating unit may include 1 clock signal generator, or a plurality of clock signal generators with a number other than 4.

Referring to fig. 14, another signal schematic of the drive circuit of fig. 12 is shown.

In this embodiment, the control unit is configured to control the durations of the high levels of the first and third clock signals CK1_ R and CK2_ R, which are not identical, wherein the durations include a first duration and a second duration, and the second duration is greater than the first duration, and to control the durations of the low levels of the second and fourth clock signals CK1_ L and CK2_ L, which include a third duration and a fourth duration, and the fourth duration is greater than the third duration.

The sum of the duration of the low level and the first duration of the high level of the first clock signal CK1_ R, the third clock signal CK2_ R is the first clock time, and the sum of the duration of the low level and the second duration of the high level is the second clock time.

The sum of the high level duration and the low level third duration of the second clock signal CK1_ L, the fourth clock signal CK2_ L is the first clock time, and the sum of the high level duration and the low level fourth duration is the second clock time.

The control unit controls the duration of the high level of the first and third clock signals CK1_ R and CK2_ R for a second duration at least once, while controlling the duration of the low level of the second and fourth clock signals CK1_ L and CK2_ L for a fourth duration.

In this embodiment, the first clock signal CK1_ R and the third clock signal CK2_ R have the same potential as the second level of the second clock signal CK1_ L and the fourth clock signal CK2_ L, and the second level of the first clock signal CK1_ R and the third clock signal CK2_ R have the same potential as the first level of the second clock signal CK1_ L and the fourth clock signal CK2_ L.

In this embodiment, the time between the falling edge of the fourth clock signal CK2_ L and the rising edge of the second clock signal CK1_ L when the clock duration is again recovered is a pause time, the first clock signal CK1_ R and the third clock signal CK2_ R remain high unchanged during the pause time, the first clock signal CK1_ R and the third clock signal CK2_ R keep the scanning signal formed by the scanning driving circuit at a high level, while the second and fourth clock signals CK1_ L and CK2_ L remain unchanged at a low level, the second clock signal CK1_ L and the fourth clock signal CK2_ L do not change from a low level to a high level, therefore, the scanning driving circuit is not excited to form the scanning signal, the scanning line is not scanned, therefore, no signal change exists on the scanning lines on the display screen, and the influence caused by electromagnetic interference is reduced.

The utility model discloses drive circuit can make scanning drive circuit suspend at least once and scan the scanning line at a frame image display in-process, and the time of definition scanning line suspension scanning is the pause time. The clock signal generated by the clock signal generating unit may control the clock signal generating unit to generate a clock signal for causing the scan driving circuit to start scanning from a next row of scan lines after a pause time. As shown in fig. 6, scanning is required to be performed on 1280 rows of scanning lines in the process of displaying one frame of image, and after the scanning of the 64 th row of scanning lines is completed, the scanning is suspended, and then the scanning is continued from the 65 th row; after scanning to the 128 th row of scanning line, the scanning is suspended again, then the scanning is performed … … from the 129 th row of scanning line, after the scanning of the 1216 th row of scanning line is completed, the scanning is suspended again, and then the scanning is started from the 1217 th row of scanning line to the 1280 th row of scanning line, thereby completing the display of one frame of picture.

However, the present invention does not limit the manner of continuing the scanning after the pause time, and with reference to fig. 15, the scanning diagram of the fifth embodiment of the driving circuit of the present invention is shown. The clock signal generated by the clock signal generating unit is used for enabling the scanning driving circuit to provide scanning signals for at least one row of scanning lines before the pause time so as to scan the scanning lines; the control unit is used for controlling the clock signal generating unit to generate a clock signal for enabling the scanning driving circuit to start scanning from at least one last row of the scanned scanning lines after the pause time. That is to say, the drive circuit scans part of the row scanning lines before the pause time twice, so that the influence of the pause time on the scanning of the scanning lines can be avoided, and the quality of a display picture can be ensured.

Specifically, as shown in fig. 15, in the process of displaying one frame of image, 1280 rows of scanning lines need to be scanned, after the scanning of the 64 th row of scanning lines is completed, the scanning is suspended, and then the scanning is continued from the 61 st row (that is, the scanning is performed twice on the 61-64 th rows); after scanning to the 128 th row of scanning line, pausing scanning again, then scanning from the 125 th row of scanning line (namely scanning the 125-128 rows twice) … …, after finishing scanning the 1216 th row of scanning line, pausing scanning again, then scanning from the 1213 rd row of scanning line (scanning the 1213-1216 rows twice) until scanning to the 1280 th row of scanning line, thereby finishing one frame of picture display.

It should be noted that the scan driving circuit may be a circuit disposed on the display Panel, for example, the scan driving circuit adopts Gate In Panel (GIP) technology, but the present invention is not limited thereto, and the scan driving circuit may be integrated with the driving circuit of the present invention, that is, the driving circuit of the present invention may include the scan driving circuit.

Accordingly, the present invention provides a display device, as shown in fig. 2, the display device includes:

the display panel 20 comprises a plurality of display units 201 and a plurality of scan lines G₁、G₂……G_NEach scanning line G₁、G₂……G_NConnecting a plurality of display units 201, the plurality of scanning lines G₁、G₂……G_NFor transmitting a scan signal provided by a scan driving circuit 300 to the plurality of display units 201 to activate and scan lines G₁、G₂……G_NThe connected display unit 201 performs image display;

drive circuit 10 for drive display panel 20 carries out image display, drive circuit 10 does the utility model provides a drive circuit. The same contents as those of the related embodiments of the driving circuit are omitted for brevity.

The utility model discloses display device can be when realizing the picture display, at least once pause the scanning in a frame image display process to have less electromagnetic interference in the time of pause scanning, other electronic device that are integrated together with display device can work in this period of time (for example: touch-control device carries out touch-control detection in the time of pause scanning), and reduce display device and other electronic device's mutual interference.

Alternatively, the scan driving circuit 201 may be disposed on the display panel 20 based on the GIP technology. However, the present invention is not limited thereto, and the scan driving circuit 201 may also be integrated in the driving circuit provided by the present invention.

Alternatively, the display panel 20 may be a liquid crystal display panel. The present invention is not limited to the type of the display panel 20.

Optionally, the display device further includes a touch panel (not shown) and a touch detection circuit connected to the touch panel, where the touch detection circuit performs touch detection on the touch panel during the pause time to reduce an influence of electromagnetic interference on the touch detection.

Specifically, the touch panel is either an external touch panel or an embedded touch panel.

Correspondingly, the utility model also provides an electronic equipment, refer to fig. 16, show the utility model discloses the schematic diagram of an electronic equipment embodiment. The electronic device 500 includes a first device 510 and a second device 520, the first device 510 is a display device, and the second device 520 operates when the first device 510 suspends scanning, so as to reduce electromagnetic interference of the display device to the second device 520.

The electronic device may be a mobile phone, a tablet computer, a notebook computer or a desktop computer.

Further, when the second device 520 is a touch device, the touch device includes a touch panel and a touch detection circuit connected to the touch panel. The touch detection circuit performs touch detection on the touch panel when the display device pauses scanning.

The touch device may further be included in a display device. The touch panel is either a panel independent from the display panel or an in-cell touch panel. The embedded touch panel includes an on-cell touch panel and an in-cell touch panel. The touch detection circuit may be integrated with a driving circuit of the display device.

The utility model discloses among the electronic equipment, display device is less to other electron device's (for example touch device) electromagnetic interference at the scanning of suspending, and other electron device can work in this period of time, have reduced display device and other electron device's mutual interference, have improved electronic equipment's integrated level.

The utility model also provides an electronic equipment, include: a display device, the display device comprising: the display panel comprises a plurality of display units and a plurality of scanning lines, wherein each scanning line is connected with the plurality of display units, and the plurality of scanning lines are used for transmitting scanning signals provided by a scanning driving circuit to the plurality of display units so as to activate the display units connected with the scanning lines to display images;

drive circuit for drive display panel carries out image display, drive circuit does the utility model provides a drive circuit.

Optionally, the scan driving circuit is disposed on the display panel. The display panel may be a liquid crystal display panel.

Specifically, the electronic device is a mobile phone, a tablet computer, a notebook computer or a desktop computer.

The utility model discloses electronic equipment can reduce electromagnetic interference's influence.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention, and the scope of the present invention is defined by the appended claims.

Claims

1. A drive circuit is used for driving a display panel to display images, the display panel comprises a plurality of display units and a plurality of scanning lines, each scanning line is connected with the plurality of display units, and the plurality of scanning lines are used for transmitting scanning signals provided by a scanning drive circuit to the plurality of display units so as to activate the display units connected with the scanning lines to display images; characterized in that the drive circuit comprises:

the scanning driving circuit is used for generating scanning signals correspondingly transmitted by each scanning line, the change from the first level to the second level is defined as an effective signal edge of the clock signal, and the time between adjacent effective signal edges is clock time;

the control unit is used for controlling the clock time of the clock signal to be not completely the same, the clock time comprises a first clock time and a second clock time, the second clock time is greater than the first clock time, and the control unit is also used for controlling the clock time to reach the second clock time at least once in the process that the display panel displays one frame of image.

2. The driving circuit according to claim 1, wherein the clock signal generating unit generates the clock signal in which the duration of the second level is the same as the duration of the scan signal generated by the scan driving circuit;

the control unit is configured to control each time duration of occurrence of the first level of the clock signal to be not completely the same, where the time duration includes a first time duration and a second time duration, and the second time duration is greater than the first time duration, and the control unit is further configured to control the time duration of the first level to reach the second time duration at least once during a process that a display panel displays one frame image, a sum of the first time duration of the first level and the time duration of the second level is the first clock time, and a sum of the second time duration of the first level and the time duration of the second level is the second clock time.

3. The drive circuit according to claim 2, wherein a clock signal generating unit is configured to generate two clock signals for causing the scan drive circuit to scan the scan lines connected to the scan drive circuit line by line;

a first duration of a first level of one of the two clock signals is the same as a duration of a second level of the other one;

the control unit is used for controlling the duration of the first level of the two clock signals for a second duration at least once in the process that the display panel displays one frame of image.

4. The drive circuit according to claim 2, wherein the scan drive circuit includes: the scanning circuit comprises a first sub-scanning driving circuit and a second sub-scanning driving circuit, wherein the first sub-scanning driving circuit is used for scanning a first group of scanning lines line by line, the second sub-scanning driving circuit is used for scanning a second group of scanning lines line by line, and the first group of scanning lines and the second group of scanning lines are adjacent scanning lines;

the clock signal generating unit is used for generating a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, and the first clock signal and the third clock signal are used for triggering the first sub-scanning driving circuit to scan a first group of scanning lines line by line; the second clock signal and the fourth clock signal are used for triggering the second sub-scanning driving circuit to perform line-by-line scanning on a second group of scanning lines;

a first duration of a first level of one of the first clock signal and a third clock signal is the same as a second level duration of the other, a first duration of a first level of one of the second clock signal and a fourth clock signal is the same as a second level duration of the other, an overlap exists between the first clock signal and the second clock signal, and an overlap exists between the third clock signal and the fourth clock signal;

the control unit is used for controlling the duration of the first level of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal for a second duration at least once in the process of displaying one frame of image by the display panel.

5. The drive circuit according to claim 1, wherein the scan drive circuit includes: the scanning circuit comprises a first sub-scanning driving circuit and a second sub-scanning driving circuit, wherein the first sub-scanning driving circuit is used for scanning a first group of scanning lines line by line, the second sub-scanning driving circuit is used for scanning a second group of scanning lines line by line, and the first group of scanning lines and the second group of scanning lines are adjacent scanning lines;

the control unit is configured to control respective durations of occurrences of the second levels of the first and third clock signals to be not completely the same, where the durations include a first duration and a second duration, and the second duration is longer than the first duration, and also to control respective durations of occurrences of the first levels of the second and fourth clock signals to be not completely the same, where the durations include a third duration and a fourth duration, and the fourth duration is longer than the third duration,

the control unit is further used for controlling the second level duration time of the first clock signal and the third clock signal to reach the second duration time at least once in the process that the display panel displays one frame of image, and the first level duration time of the second clock signal and the fourth clock signal to reach the fourth duration time;

the sum of the duration of the first level of the first clock signal and the third clock signal and the first duration of the second level is the first clock time, and the sum of the duration of the first level and the second duration of the second level is the second clock time;

the sum of the duration of the second level of the second clock signal and the fourth clock signal and the third duration of the first level is the first clock time, and the sum of the duration of the second level and the fourth duration of the first level is the second clock time.

6. The drive circuit according to claim 1, wherein the clock signal generation unit generates a clock signal in which the sum of the durations of the first level and the second level is the same as the duration of the scan signal generated by the scan drive circuit;

the control unit is used for controlling the duration time of the first level of the clock signal to occur not to be completely the same, the duration time comprises a first duration time and a second duration time, the second duration time is longer than the first duration time, the control unit is further used for controlling the duration time of the first level to reach the second duration time at least once in the process that the display panel displays one frame image, the sum of the first duration time of the first level and the duration time of the second level is the first clock time, and the sum of the second duration time of the first level and the duration time of the second level is the second clock time;

or,

the control unit is configured to control the respective durations of the second levels of the clock signal to be not completely the same, where the durations include a first duration and a second duration, and the second duration is greater than the first duration, and the control unit is further configured to control the duration of the second level for the second duration at least once during a display of one frame image on the display panel, a sum of the first duration of the second level and the duration of the first level is the first clock time, and a sum of the second duration of the second level and the duration of the first level is the second clock time.

7. The driving circuit according to any one of claims 1 to 6, wherein the plurality of scanning lines are further configured to activate display of each frame image according to a frame synchronization signal provided by a frame synchronization signal unit; the scanning driving circuit is also used for providing a row synchronizing signal;

the control unit is connected with the frame synchronization signal unit and the scanning drive circuit and used for judging whether to control the clock time of the clock signal to reach a second clock time or not according to the frame synchronization signal and the line synchronization signal.

8. The drive circuit according to claim 7, wherein the control unit includes:

the memory is used for storing preset row information, and the preset row information is the row information of the corresponding scanning line when the clock time is controlled to reach the second clock time;

the judging module is connected with the frame synchronizing signal unit, the scanning driving circuit and the memory and is used for judging whether the received line synchronizing signal meets the preset line information or not after receiving a frame synchronizing signal;

and the control module is connected with the frame synchronization signal unit, the scanning driving circuit and the judging module and is used for enabling the clock time of the clock signal output by the clock signal generating unit to reach a second clock time when the judging module judges that the line synchronization signal meets the preset line information.

9. The driving circuit of claim 8, wherein the control module is further configured to send the line synchronization signal to the clock signal generation unit to cause the clock signal generation unit to generate the clock signal;

the control module is configured to stop providing the horizontal synchronization signal to the clock signal generation unit for a first preset time when the judgment module judges that the horizontal synchronization signal meets the preset horizontal information, so that the clock time of the clock signal reaches a second clock time.

10. The driving circuit according to claim 8, wherein the control module is configured to form a stop signal when the determination module determines that the line synchronization signal satisfies the preset line information, and the stop signal comprises an invalid signal and a valid signal;

the clock signal generating unit is used for immediately enabling the output clock time to reach a second clock time when the stop signal is switched from the invalid signal to the valid signal;

or,

the clock signal generating unit is used for enabling the output clock time to reach a second clock time after a second preset time when the stop signal is switched from the invalid signal to the valid signal.

11. The drive circuit according to claim 10, wherein the stop signal is a square wave signal composed of a third level and a fourth level, the third level being different in potential from the fourth level;

the third level is the active signal and the fourth level is the inactive signal; or, the fourth level is the valid signal, and the third level is the invalid signal.

12. The drive circuit according to any of claims 1 to 6,

the clock signal generation unit includes:

the initial pulse generating module is used for forming an initial pulse;

the clock signal generating module is used for generating the clock signal according to the initial pulse;

the reset signal generation module is used for forming a reset signal, and the reset signal is used for enabling the initial pulse generation module to output the initial pulse again after a third preset time;

the control unit is connected with the reset signal generating module and is used for controlling the reset signal generating module to generate the reset signal at least once in the process of displaying one frame of image on the display panel, so that the clock time of the clock signal output by the clock signal generating module reaches a second clock time.

13. The driving circuit according to claim 2, wherein the clock signal generating unit generates at least two clock signals, a second duration of first levels of the at least two clock signals overlapping, a time defining the second duration of the first levels of the at least two clock signals overlapping is a pause time, at which the first levels of the at least two clock signals cause the scan driving circuit to pause scanning of the scan lines,

the clock signal generated by the clock signal generating unit is used for enabling the scanning driving circuit to provide scanning signals for at least one row of scanning lines before the pause time so as to scan the scanning lines;

the control unit is used for controlling the clock signal generating unit to generate a clock signal for enabling the scanning driving circuit to start scanning from the next row of scanning lines after the pause time.

14. The driving circuit according to claim 2, wherein the clock signal generating unit generates at least two clock signals, a second duration of the first levels of the at least two clock signals overlaps, and a time defining the overlap of the second duration of the first levels of the at least two clock signals is a pause time, and the first levels of the at least two clock signals cause the scan driving circuit to pause scanning of the scan lines at the pause time;

the control unit is used for controlling the clock signal generating unit to generate a clock signal for enabling the scanning driving circuit to start scanning from at least one last row of the scanned scanning lines after the pause time.

15. The drive circuit according to claim 2, wherein the clock signal generation unit generates at least two clock signals, a first level of a part of the at least two clock signals is used for driving the scanning driving circuit to generate the scanning signals, a second level of another part of the at least two clock signals is used for driving the scanning driving circuit to generate the scanning signals, the second durations of the first levels of the at least two clock signals overlap, defining the time during which the second durations of the first levels of the at least two clock signals overlap as a pause time, and in the pause time, the scanning driving circuit is driven by a first level to generate the clock signal of the scanning signal so that the scanning driving circuit continuously scans the scanning line, and the scanning driving circuit is driven by a second level to generate the clock signal of the scanning signal so that the scanning driving circuit pauses to scan the scanning line.

16. The drive circuit according to claim 1, wherein the drive circuit comprises the scan drive circuit.

17. A display device, comprising:

the display panel comprises a plurality of display units and a plurality of scanning lines, wherein each scanning line is connected with the plurality of display units, and the plurality of scanning lines are used for transmitting scanning signals provided by a scanning driving circuit to the plurality of display units so as to activate the display units connected with the scanning lines to display images;

a driving circuit for driving a display panel to display an image, the driving circuit according to any one of claims 1 to 16.

18. The display device according to claim 17, wherein the scan driver circuit is provided on the display panel.

19. The display device according to claim 17, wherein the display panel is a liquid crystal display panel.

20. A display device, comprising: the display panel comprises a plurality of display units and a plurality of scanning lines, wherein each scanning line is connected with the plurality of display units, and the plurality of scanning lines are used for transmitting scanning signals provided by a scanning driving circuit to the plurality of display units so as to activate the display units connected with the scanning lines to display images;

a driving circuit for driving a display panel to display an image, the driving circuit being as claimed in any one of claims 13 to 15;

the display device further comprises a touch panel and a touch detection circuit connected with the touch panel, wherein the touch detection circuit performs touch detection on the touch panel during the pause time.

21. The display device according to claim 20, wherein the touch panel is either an add-on touch panel or an in-cell touch panel.

22. An electronic device, comprising: a display device for displaying the image of the object,

the display device includes: the display panel comprises a plurality of display units and a plurality of scanning lines, wherein each scanning line is connected with the plurality of display units, and the plurality of scanning lines are used for transmitting scanning signals provided by a scanning driving circuit to the plurality of display units so as to activate the display units connected with the scanning lines to display images;

23. The electronic device according to claim 22, wherein the scan driver circuit is provided over the display panel.

24. The electronic device according to claim 22, wherein the display panel is a liquid crystal display panel.

25. The electronic device of claim 22, wherein the electronic device is a cell phone, a tablet computer, a laptop computer, or a desktop computer.

26. An electronic device, comprising: an electronic device comprising a first device and a second device, wherein the first device is a display device comprising a driver circuit as claimed in any one of claims 13 to 15, and the second device is operated during the pause time.

27. The electronic device of claim 26, wherein the second device is a touch device.

28. The electronic device according to claim 27, wherein the touch device comprises a touch panel and a touch detection circuit connected to the touch panel, the touch detection circuit performing touch detection on the touch panel during the pause time.

29. The electronic device of claim 28, wherein the touch panel is either an add-on touch panel or an in-cell touch panel.