CN202978703U - Switching power supply circuit - Google Patents
Switching power supply circuit Download PDFInfo
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- CN202978703U CN202978703U CN 201220201921 CN201220201921U CN202978703U CN 202978703 U CN202978703 U CN 202978703U CN 201220201921 CN201220201921 CN 201220201921 CN 201220201921 U CN201220201921 U CN 201220201921U CN 202978703 U CN202978703 U CN 202978703U
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Abstract
The utility model provides a switching power supply circuit, which comprises an input port coupled with an input voltage; an output port for providing an output voltage to a load; the energy storage element and the power switch are coupled between the input port and the output port; an error amplifier outputting an error amplified signal at an output terminal based on the feedback signal and the voltage reference signal; an error comparator outputting a frequency control signal at an output terminal thereof based on the error amplification signal and the sawtooth wave signal; a peak current generator generating a peak current signal at an output terminal based on the frequency control signal; a peak current comparator for outputting a peak current control signal at an output terminal based on the peak current signal and the current detection signal; and the logic circuit outputs a gate pole signal at the output end of the logic circuit based on the frequency control signal and the peak current control signal so as to control the on and off of the power switch.
Description
Technical field
The utility model relates to power circuit, and more particularly, the utility model relates to switching power circuit.
Background technology
Switching power circuit is widely used in various occasions.A kind of control model that is usually used in existing switching power circuit is that peak current is controlled.Yet existing peak current adopts the method for constant peak current, in the time of making the circuit load step-down, and Efficiency Decreasing.
The utility model content
The purpose of this utility model is to solve the problems referred to above of prior art, and a kind of improved switching power circuit is provided.
For achieving the above object, the utility model provides a kind of switching power circuit, comprising: input port couples input voltage; Output port provides output voltage to load; Be coupled in energy-storage travelling wave tube and power switch between input port and output port, wherein said power switch has control end; Error amplifier has first input end, the second input and output, and wherein said first input end couples the feedback signal of reflection output voltage, described the second input receiver voltage reference signal, described output output error amplifying signal; Error comparator has first input end, the second input and output, and the output that described first input end is coupled to error amplifier receives error amplification signal, and described the second input receives sawtooth signal, described output output frequency control signal; The peak current generator has input and output, and described input is coupled to the output receive frequency control signal of error comparator, and described output produces peak-current signal; The peak current comparator, have first input end, the second input and output, the output that described first input end is coupled to the peak current generator receives peak-current signal, described the second input receives the current detection signal that the electric current of energy-storage travelling wave tube is flow through in reflection, described output output peak current control signal; Logical circuit, have first input end, the second input and output, wherein said first input end is coupled to the output receive frequency control signal of error comparator, the output that described the second input is coupled to the peak current comparator receives the peak current control signal, and described output output gate signal is to the control end of power switch.
According to embodiment of the present utility model, wherein said logical circuit comprises: oscillator, the clock signal of output fixed frequency; Select circuit, have first input end, the second input and output, described first input end is coupled to oscillator receive clock signal, described the second input is coupled to the error comparator receiving frequency signals, described selection circuit is at frequency signal output frequency signal during less than clock signal, at frequency signal during more than or equal to clock signal, clock signal; Rest-set flip-flop, have set end, reset terminal and output, wherein said set end is coupled to the output of selecting circuit, and the output that described reset terminal is coupled to the peak current comparator receives the peak current control signal, the described gate signal of described output output.
According to embodiment of the present utility model, wherein said peak current generator comprises: the first switch, have first end, the second end and control end, described first end couples the maximum value level signal with the peaked magnitude of voltage of peak-current signal, and described control end couples frequency control signal; The cycle timing unit has input and output, described input receive frequency control signal, described output output timing signal; Second switch has first end, the second end and control end, and described first end is coupled to the second end of the first switch, and the output that described control end is coupled to the cycle timing unit receives timing signal; The 3rd switch has first end and the second end, and described first end is coupled to the second end of second switch, and described the second end couples the minimal value level signal of the magnitude of voltage with peak-current signal minimum value; The first electric capacity has first end and the second end, and described first end is coupled to the tie point of the first switch and second switch, and described the second termination is with reference to ground; The first current source has first end and the second end, and described first end is coupled to the tie point of second switch and the 3rd switch, and described the second end is connected to reference to ground.
According to embodiment of the present utility model, wherein said cycle timing unit comprises: the first timer, receive frequency control signal, output the first timing signal; The second timer couples frequency control signal, output the second timing signal; OR circuit has first input end, the second input and output, and the output that wherein said first input end is coupled to the second timer receives the second timing signal, described the second input receiving frequency signals; Rest-set flip-flop has set end, reset terminal and output, and its set end is coupled to the first timer and receives the first timing signal, and its reset terminal couples the output of OR circuit, described output output timing signal.
for achieving the above object, the utility model has also proposed a kind of switching power circuit, comprise: transformer, former limit power switch, secondary power switch, former limit controller, secondary controller and coupled apparatus, described transformer comprises former limit winding, secondary winding and the tertiary winding, described former limit winding and former limit power switch couple, described secondary winding and secondary power switch couple, described coupled apparatus has input side and outlet side, described input side couples described secondary controller, described outlet side produces frequency control signal, described former limit controller provides the gate signal of the break-make of controlling former limit power switch, described former limit controller comprises: the peak current generator, have input and output, described input receive frequency control signal, described output produces peak-current signal, current comparator, have first input end, the second input and output, wherein first input end receives the current detection signal that the electric current of former limit winding is flow through in reflection, the output that the second input is coupled to the peak current generator receives peak-current signal, described output output peak current control signal, logical circuit, have first input end, the second input and output, the output that wherein said first input end receive frequency control signal, described the second input are coupled to the peak current comparator receives the peak current control signal, described output output gate signal.
According to embodiment of the present utility model, wherein said logical circuit comprises: oscillator, the clock signal of output fixed frequency; Select circuit, has first input end, the second input and output, described first input end is coupled to oscillator receive clock signal, described the second input is coupled to the error comparator receiving frequency signals, and described selection circuit is at frequency signal during less than clock signal, output frequency signal, at frequency signal during more than or equal to clock signal, clock signal; Rest-set flip-flop, have set end, reset terminal and output, wherein said set end is coupled to the output of selecting circuit, and the output that described reset terminal is coupled to the peak current comparator receives the peak current control signal, the described gate signal of described output output.
According to embodiment of the present utility model, wherein said peak current generator comprises: the first switch, have first end, the second end and control end, described first end couples the maximum value level signal with the peaked magnitude of voltage of peak-current signal, and described control end couples frequency control signal; The cycle timing unit has input and output, described input receive frequency control signal, and based on frequency control signal, described output output timing signal; Second switch has first end, the second end and control end, and described first end is coupled to the second end of the first switch, and the output that described control end is coupled to the cycle timing unit receives timing signal; The 3rd switch has first end and the second end, and described first end is coupled to the second end of second switch, and described the second end couples the minimal value level signal of the magnitude of voltage with peak-current signal minimum value; The first electric capacity has first end and the second end, and described first end is coupled to the tie point of the first switch and second switch, and described the second termination is with reference to ground; The first current source has first end and the second end, and described first end is coupled to the tie point of second switch and the 3rd switch, and described the second end is connected to reference to ground.
According to embodiment of the present utility model, wherein said cycle timing unit comprises: the first timer, and the receive frequency control signal, and based on frequency control signal output the first timing signal; The second timer couples frequency control signal, and based on frequency control signal output the second timing signal; OR circuit has first input end, the second input and output, and the output that wherein said first input end is coupled to the second timer receives the second timing signal, described the second input receiving frequency signals; Rest-set flip-flop, have set end, reset terminal and output, its set end is coupled to the first timer and receives the first timing signal, and its reset terminal couples the output of OR circuit, and described rest-set flip-flop is based on the output signal output timing signal of the first timing signal and OR circuit.
According to embodiment of the present utility model, wherein said secondary controller comprises: error amplifier, have first input end, the second input and output, wherein said first input end couples the feedback signal that characterizes output voltage, the second input receiver voltage reference signal, described output output error amplifying signal; Error comparator has first input end, the second input and output, and the output that wherein said first input end is coupled to error amplifier receives error amplification signal, and the second input couples modulation signal, described output output the first comparison signal; The 4th switch has first end, the second end and control end, and the output that wherein said control end is coupled to error comparator receives the first comparison signal, and described the second termination secondary is with reference to ground; Wherein, the input side of described coupled apparatus is coupled between the first end of output port and the first switch.
According to the switching power circuit of the above-mentioned each side of the utility model, effectively improved efficient.
Description of drawings
Fig. 1 shows the electrical block diagram according to the switching power circuit 100 of the utility model one embodiment;
Figure 2 shows that the schematic diagram that concerns of the peak-current signal Vlim of switching power circuit 100 shown in Figure 1 and switching frequency f;
Fig. 3 shows the electrical block diagram according to the switching power circuit peak current generator 105 shown in Figure 1 of the utility model one embodiment;
Fig. 4 illustrates the timing signal ts of peak current generator 105 shown in Figure 3 and the timing waveform of peak-current signal Vlim;
Fig. 5 shows the electrical block diagram according to the switching power circuit 200 of the utility model one embodiment;
The switching frequency f that Fig. 6 illustrates switching power circuit 200 shown in Figure 5 concerns schematic diagram with what the frequency f con of frequency control signal changed;
Fig. 7 shows the electrical block diagram according to the switching power circuit 300 of the utility model one embodiment;
Fig. 8 shows the electrical block diagram according to the switching power circuit 400 of the utility model one embodiment.
Embodiment
The below will describe specific embodiment of the utility model in detail, should be noted that the embodiments described herein only is used for illustrating, and be not limited to the utility model.In the following description, in order to provide thorough understanding of the present utility model, a large amount of specific detail have been set forth.Yet, it is evident that for those of ordinary skills: needn't adopt these specific detail to carry out the utility model.In other examples, for fear of obscuring the utility model, do not specifically describe known circuit, material or method.
In whole specification, " embodiment ", " embodiment ", " example " or mentioning of " example " are meaned: special characteristic, structure or characteristic in conjunction with this embodiment or example description are comprised at least one embodiment of the utility model.Therefore, phrase " in one embodiment ", " in an embodiment ", " example " or " example " that occurs in each place of whole specification differs to establish a capital and refers to same embodiment or example.In addition, can with any suitable combination and/or sub-portfolio with specific feature, structure or property combination in one or more embodiment or example.In addition, it should be understood by one skilled in the art that at this accompanying drawing that provides be all for illustrative purposes, and accompanying drawing is drawn in proportion not necessarily.Should be appreciated that when claiming element " to be connected to " or during " being couple to " another element, it can be directly connect or be couple to another element or can have intermediary element.On the contrary, when claiming element " to be directly connected to " or during " being directly coupled to " another element, not having intermediary element.The identical identical element of Reference numeral indication.Term used herein " and/or " comprise any and all combinations of one or more relevant projects of listing.
Fig. 1 shows the electrical block diagram according to the switching power circuit 100 of the utility model one embodiment.As shown in Figure 1, described switching power circuit 100 comprises: input port 101 couples input voltage VIN; Output port 110 provides output voltage V o; Be coupled in energy-storage travelling wave tube L, power switch M1 and M2 between input port 101 and output port 110; And provide the control circuit of gate signal with power ratio control switch M1 and M2, wherein said control circuit comprises: error amplifier 102, have first input end, the second input and output, wherein said first input end receives the feedback signal Vfb of reflection output voltage V o, described the second input receiver voltage reference signal Vref, based on described feedback signal Vfb and voltage reference signal Vref, described error amplifier 102 is at output output error amplifying signal Vc; Error comparator 103, have first input end, the second input and output, described first input end receives error amplification signal Vc, described the second input receives sawtooth signal Vsaw, based on described error amplification signal Vc and sawtooth signal Vsaw, described error comparator 103 is at its output output frequency control signal Con; Peak current generator 105, have input and output, described input is coupled to the output receive frequency control signal Con of error comparator 103, and based on frequency control signal Con, described peak current generator produces peak-current signal Vlim at output; Peak current comparator 107, have first input end, the second input and output, described first input end is coupled to peak current generator 105 and receives peak-current signal Vlim, described the second input receives the current detection signal Vcs that the electric current of energy-storage travelling wave tube L is flow through in reflection, based on described peak-current signal Vlim and current detection signal Vcs, described peak current comparator 107 is in output output current control signal; Logical circuit 106, have first input end, the second input and output, wherein said first input end is coupled to the output receive frequency control signal Con of error comparator 103, the output that described the second input is coupled to peak current comparator 107 receives the peak current control signal, based on described frequency control signal Con and described peak current control signal, described logical circuit 106 is in the described gate signal of its output output.
Gate signal is used to conducting and the disconnection of power ratio control switch M1 and M2.It will be appreciated by those of ordinary skill in the art that gate signal can strengthen after driving force through driver the break-make of power ratio control switch M1 and M2 usually again.Driver belongs to the common practise of this area, for for simplicity clear, and not expression in Fig. 1.
In one embodiment, described logical circuit 106 comprises the first rest-set flip-flop.Described the first rest-set flip-flop has set end S, reset terminal R and output Q, wherein said set end S receive frequency control signal Con, described reset terminal R receives the peak current control signal, based on frequency control signal Con and peak current control signal, described the first rest-set flip-flop is at output output gate signal Gate.
In one embodiment, the switching frequency f of the switching power circuit 100 that characterizes according to frequency control signal Con is at different frequency separations, described peak-current signal Vlim has different relations from frequency control signal Con: a). as switching frequency f greater than first frequency threshold value f1, peak-current signal Vlim along with switching frequency f reduce begin to reduce from peak current maximum Vlim_max; B). when switching frequency f was between first frequency threshold value f1 and second frequency threshold value f2, peak-current signal Vlim was fixed in peak current median Vlim_mid; C). when switching frequency f is between second frequency threshold value f2 and the 3rd frequency threshold f3, peak-current signal Vlim along with switching frequency f reduce begin to reduce from peak current median Vlim_mid; D). during less than the 3rd frequency threshold f3, peak-current signal Vlim is fixed in peak current minimum value Vlim_min when switching frequency; Wherein first frequency threshold value f1 is greater than second frequency threshold value f2, and second frequency threshold value f2 is greater than the 3rd frequency threshold f3.Peak-current signal Vlim shown in Figure 2 and switching frequency f concern schematic diagram, and namely the pass of peak-current signal Vlim and switching frequency f is:
Wherein k is coefficient, and when switching power circuit 300 was determined, k was fixed value.
Because switching frequency f and switch periods ts are reciprocal each other, namely
Peak-current signal Vlim and switch periods ts have following relation;
That is to say, the switch periods ts of the switching power circuit 100 that characterizes according to frequency control signal Con is in different intervals, described peak-current signal Vlim has different relations from frequency control signal Con: a). and greater than period 1 threshold value 1/f1, peak-current signal Vlim reduces along with the increase of switch periods ts begins linearity from peak current maximum Vlim_max as switch periods ts; B). when switch periods ts was between period 1 threshold value 1/f1 and second round threshold value 1/f2, peak-current signal Vlim was fixed in peak current median Vlim_mid; C). when switch periods ts be in second round threshold value 1/f2 and period 3 threshold value 1/f3 between the time, peak-current signal Vlim reduces along with the increase of switch periods ts begins linearity from peak current median Vlim_mid; D). during less than period 3 threshold value 1/f3, peak-current signal Vlim is fixed in peak current minimum value Vlim_min as switch periods ts; Wherein period 1 threshold value 1/f1 is less than threshold value 1/f2 second round, and second round, threshold value 1/f2 was less than period 3 threshold value 1/f3.
In one embodiment, peak current generator 105 can pass through VHDL(Very-High-Speed Integrated Circuit Hardware Description Language, be Very High Speed Integrated Circuit (VHSIC) hardware description language) and Verilog HDL(hardware description language, be hardware description language) auxiliary, function (being above-mentioned functional relation) VHDL and Verilog HDL language description with peak current generator 105 just can generate corresponding circuit automatically.
When the normal operation of switching power circuit 100,102 couples of feedback signal Vfb of error amplifier and voltage reference signal Vref compare, and its difference is amplified obtain error amplification signal Vc.When feedback signal Vfb increased, error amplification signal Vc also increased thereupon; When feedback signal Vfb reduced, error amplification signal Vc also reduced thereupon.The sawtooth signal Vsaw increase of starting from scratch in each switch periods, when it increases to greater than error amplification signal Vc, the frequency control signal Con of error comparator 103 outputs becomes high level, the sawtooth signal Vsaw increase of again starting from scratch subsequently, the high level of error comparator 103 finishes.On the one hand, above-mentioned high level pulse set the first rest-set flip-flop of frequency control signal Con disconnects power switch M1 conducting, power switch M2.Correspondingly, the electric current that flows through energy-storage travelling wave tube L begins to increase.Corresponding therewith, current detection signal Vcs also begins to increase.On the other hand, the switching frequency of peak current generator 105 judgement switching power circuits 100 this moment according to functional relation (1), provides corresponding peak-current signal Vlim.When current detection signal Vcs increased to greater than peak-current signal Vlim, the peak current control signal became high level.Thereby reset the first rest-set flip-flop, with power switch M1 disconnection, power switch M2 conducting.Until sawtooth signal Vsaw is again greater than error amplification signal Vc, thereby the high level pulse of the frequency control signal Con of error comparator 103 outputs is disconnected power switch M1 conducting, power switch M2, switching power circuit 100 enters next switch periods, and operation as mentioned above.
When switching power circuit 100 load saltus step, as by the underloading saltus step being heavy duty, output voltage V o descends, and feedback signal Vfb descends thereupon, thereby causes the error amplification signal Vc of error comparator 102 outputs to descend.And at error comparator 103 places, when sawtooth signal Vsaw increased to the value of error amplification signal Vc, frequency control signal Con produced high level pulse.And the duration between twice high level pulse of frequency control signal Con is the switch periods of switching power circuit 100, therefore the error amplification signal Vc that reduces has shortened the time between twice high level pulse of frequency control signal Con, thereby shortened the switch periods of switching power circuit 100, increased the switching frequency f of switching power circuit 100.Otherwise when switching power circuit 100 loads were underloading by heavily loaded saltus step, output voltage V o increased, and feedback signal Vfb increases thereupon, thereby caused the error amplification signal Vc of error comparator 102 outputs to increase.Correspondingly, the time between twice high level pulse of frequency control signal Con is extended, so the switch periods of switching power circuit 100 is extended, and namely the switching frequency of switching power circuit 100 is lowered.
Fig. 3 shows the electrical block diagram according to the switching power circuit peak current generator 105 shown in Figure 1 of the utility model one embodiment.In the embodiment shown in fig. 3, peak current generator 105 comprises: the first switch S 1, has first end, the second end and control end, described first end couples maximum value level signal 53, described maximum value level signal 53 has the magnitude of voltage of peak-current signal maximum Vlim_max, and described control end couples frequency control signal Con; Cycle timing unit 51, described cycle timing unit 51 comprises: the first timer 501, receive frequency control signal Con, and based on frequency control signal Con output the first timing signal; The second timer 502 couples frequency control signal Con, and based on frequency control signal Con output the second timing signal; OR circuit 504 has first input end, the second input and output, and the output that wherein said first input end is coupled to the second timer 502 receives the second timing signal, described the second input receiving frequency signals Con; Rest-set flip-flop 503, have set end S, reset terminal R and output Q, its set end S is coupled to the first timer 501 and receives the first timing signal, its reset terminal R couples the output of OR circuit 504, and described rest-set flip-flop 503 is based on the output signal output timing signal ts of the first timing signal and OR circuit 504; Second switch S2 has first end, the second end and control end, and described first end is coupled to the second end of the first switch S 1, and described control end is coupled to cycle timing unit 51 and receives timing signal ts; The 3rd switch D3 has first end and the second end, and described first end is coupled to the second end of second switch S2, and described the second end couples minimal value level signal 54, and described minimal value level signal 54 has the magnitude of voltage of peak-current signal minimum value Vlim_min; The first capacitor C 6 has first end and the second end, and described first end is coupled to the tie point of the first switch S 1 and second switch S2, and described the second termination is with reference to ground, and wherein the voltage signal at the first capacitor C 6 two ends is described peak-current signal Vlim; The first current source I1 has first end and the second end, and described first end is coupled to the tie point of second switch S2 and the 3rd switch D3, and described the second end is connected to reference to ground.
In one embodiment, the 3rd switch D3 comprises diode, and the anode of wherein said diode couples minimal value level signal 54, and the negative electrode of described diode is coupled to the second end of second switch S2.
In one embodiment, second switch S2 is the low level control conducting.
In one embodiment, at cycle timing unit 51 places, the timing of all starting from scratch of high level pulse of the every output of frequency control signal Con, the first timer 501 and the second timer 502.When the full 1/f1 time period of the first timer 501 timing, the first timing signal of its output produces a pulse set rest-set flip-flop 503; When the full 1/f2 time period of the second timer 502 timing, the second timing signal of its output produces a pulse reset rest-set flip-flop 503.OR circuit 504 is controlled the reset terminal of rest-set flip-flop 503 with the second timing signal mutually or afterwards with frequency signal Con.Be rest-set flip-flop 504 when frequency signal Con output high level pulse or all be reset during the second timing signal output high level pulse.
When the full 1/f1 time period of the first timer 501 timing, the first timing signal of its output produces a pulse set rest-set flip-flop 503; When the full 1/f2 time period of the second timer 502 timing, the second timing signal of its output produces a pulse reset rest-set flip-flop 503.If twice pulse duration of frequency control signal Con is less than 1/f1, namely this moment switching power circuit 100 switching frequency f greater than first frequency threshold value f1(f f1), the equal no pulse of the first timing signal and the second timing signal produces, the output output initial state low level signal of rest-set flip-flop 503.
If twice pulse duration of frequency control signal Con is greater than 1/f1, less than 1/f2, namely this moment switching power circuit switching frequency f be between first frequency threshold value f1 and second frequency threshold value f2 (f2＜f＜f1), produce pulse from frequency control signal Con, at first rest-set flip-flop 503 is reset, and timing signal ts is low level.The first timing circuit 501 is exported high level pulse when the full 1/f1 of timing, set rest-set flip-flop 503, timing signal ts are high level.And due to this moment frequency control signal Con twice pulse duration less than 1/f2, the second timing signal no pulse produces, therefore when the pulse next time of frequency control signal Con arrived, timing signal ts was maintained high level.
In like manner, if twice pulse duration of frequency control signal Con be greater than 1/f2, namely this moment switching power circuit switching frequency f less than second frequency threshold value f2(f＜f2), after frequency control signal Con produces pulse, at first rest-set flip-flop 503 is reset, and timing signal ts is low level.The first timing circuit 501 is exported high level pulse when the full 1/f1 of timing, set rest-set flip-flop 503, timing signal ts are high level.The second timing circuit 502 is exported high level pulse when the full 1/f2 of timing, by the rest-set flip-flop 503 that resets after AND circuit 504, timing signal ts is low level.
If twice pulse duration of frequency control signal Con is greater than 1/f3, after frequency control signal Con produced pulse, at first rest-set flip-flop 503 was reset, and timing signal ts is low level.The first timing circuit 501 is exported high level pulse when the full 1/f1 of timing, set rest-set flip-flop 503, timing signal ts are high level.The second timing circuit 502 is exported high level pulse when the full 1/f2 of timing, by the rest-set flip-flop 503 that resets after AND circuit 504, timing signal ts is low level, and the pulse next time that is retained to frequency control signal Con arrives.
In the above-described embodiments, the timing signal of the first timer and the second timer output is pulse signal.Rest-set flip-flop 503 is pulse-triggered.In one embodiment, the first timer and the second timer outputs level signals, namely after the timing time of the first timer and the second timer has arrived, the first timing signal of exporting and the upset of the second timing signal level (being high level by the low level upset).Rest-set flip-flop 503 is level triggers, and the priority of reset terminal is higher than the priority of set end.When the first timing signal and the second timing signal were logic low, rest-set flip-flop 503 was initial condition, and it is output as low level (being that timing signal ts is low level); When the first timing signal is high level, when the second timing signal was low level, the output of rest-set flip-flop 503 was set to high level (being that timing signal ts is high level); When the second timing signal is high level, or door 504 output high level signals, the output of rest-set flip-flop 503 is reset to low level (being that timing signal ts is low level).In one embodiment, the rest-set flip-flop 503 of level triggers also can be realized by logic gates.
Those of ordinary skills should be understood that the effect of cycle timing unit 51 is frequency separations of output timing signal indication frequency control signal Con.Any timing signal ts that can make all can be used for the utility model at the circuit that frequency control signal Con is in the level value different from being in other frequency separation of output between frequency separation f1 ~ f2.
Fig. 4 illustrates the timing signal ts of peak current generator 105 shown in Figure 3 and the timing waveform of peak-current signal Vlim.The operation principle of peak current generator 105 shown in Figure 3 is described below with reference to Fig. 4.
When 105 work of peak current generator, when frequency control signal Con output high level pulse, the first switch S 1 is switched on, and the first capacitor C 6 is coupled to maximum value level signal 53; When frequency control signal Con end-of-pulsing, the first switch S 1 is disconnected, and the first capacitor C 6 is charged to peak-current signal maximum Vlim_max.This moment, rest-set flip-flop 503 was reset, timing signal ts is low level, second switch S2 is closed conducting, therefore the first current source I1 begins the first capacitor C 6 discharges, the first capacitor C 6 both end voltage are that peak-current signal Vlim begins linear decline from peak current maximum Vlim_max, as shown in Fig. 4 interval B 1.If before frequency control signal Con exports high level pulse again, the first timer 501 and the second timer be not timing end all, timing signal ts remains low level, and the second capacitor C 6 both end voltage will be by continuous discharge, and peak-current signal Vlim is linear to descend; If before frequency control signal Con exports high level pulse again, the timing signal saltus step is that high level (is that frequency signal f is in frequency separation f1 ~ f2), second switch S2 is disconnected, the second current source I1 was disconnected with the second being connected of capacitor C 6, the second capacitor C 6 both end voltage are that peak-current signal Vlim is fixed in peak-current signal median Vlim_mid, as shown in Fig. 4 interval B 2; If before frequency control signal Con exports pulse again, timing signal ts saltus step again is low level, second switch S2 closed conducting again, the second current source I1 continues to the second capacitor C 6 discharges, the second capacitor C 6 both end voltage are that peak-current signal Vlim begins to continue linear decline from peak-current signal median Vlim_mid, as shown in Fig. 4 interval B 3.Drop to peak-current signal minimum value Vlim_min if the second capacitor C 6 both end voltage are peak-current signal Vlim, the 3rd switch D3 is switched on, thereby makes the second capacitor C 6 couple minimal value level signal 54.Correspondingly, the second capacitor C 6 both end voltage are that peak-current signal Vlim is fixed on peak-current signal minimum value Vlim_min, as shown in Fig. 4 interval B 4.
That is to say, in each switch periods, in the time of frequency control signal Con output high level pulse set the first rest-set flip-flop, peak-current signal Vlim equals Vlim_max.Subsequently, the interval duration of twice high level pulse of peak current generator 105 determination frequency control signal Con (namely judge the switch periods of switching power circuit, that is to say the frequency of judgement switching power circuit) is exported corresponding peak-current signal.When load was heavier, switching frequency was higher, and switch periods is shorter, and this moment, peak current was relatively large as can be seen from Figure 4, and is elongated with the guaranteed output switch conduction, increases the energy that is sent to load; When load was lighter, switching frequency was lower, and switch periods is longer, as can be seen from Figure 4 this moment the peak current less, shorten with the guaranteed output switch conduction time, reduce the energy that is sent to load.Therefore, the switching power circuit according to the utility model embodiment has effectively improved efficient.
In one embodiment, cycle timing unit 51 also can pass through VHDL(Very-High-Speed Integrated Circuit Hardware Description Language, be Very High Speed Integrated Circuit (VHSIC) hardware description language) and Verilog HDL(hardware description language, be hardware description language) auxiliary, function VHDL and Verilog HDL language description with cycle timing unit 51 just can generate corresponding circuit automatically.
Fig. 5 shows the electrical block diagram according to the switching power circuit 200 of the utility model one embodiment.Switching power circuit 200 shown in Figure 5 is similar to switching power circuit 100 shown in Figure 1, compare with switching power circuit 100 shown in Figure 1, the logical circuit 206 of switching power circuit 200 shown in Figure 5 comprises: oscillator 111, and the output fixed frequency is the clock signal clk of fs_max; Select circuit 109, have first input end, the second input and output, wherein said first input end is coupled to the output receive frequency control signal Con of error comparator 103, described the second input is coupled to oscillator 111 receive clock signal CLK, described selection circuit 109 is based on clock signal clk and frequency control signal Con, at the less signal of output output frequency; The first rest-set flip-flop, have set end S, reset terminal R and output Q, wherein said set end S is coupled to the output of selecting circuit 109, the output that described reset terminal R is coupled to peak current comparator 107 receives the peak current control signal, based on output signal and the described peak current control signal of described selection circuit 109, described the first rest-set flip-flop is at the described gate signal Gate of its output Q output.
Therefore, switching power circuit 200 is by selecting circuit 109, when frequency very heavy in load, frequency control signal is very large, select the clock signal clk of fixed frequency, it is the frequency that the maximum operating frequency of switching power circuit has been limited in clock signal clk, avoid the continuation of switching frequency this moment to increase, thereby avoid the lasting increase of power loss, further improved efficient.
In above-described embodiment, the main circuit of switching power circuit is non-isolated topological structure (as Fig. 1 and BUCK circuit topology shown in Figure 5), but the main circuit that those skilled in the art will realize that switching power circuit also can comprise isolated topological structure.Fig. 7 shows the electrical block diagram according to the switching power circuit 300 of the utility model one embodiment.
In the embodiment shown in fig. 7, switching power circuit 300 comprises: input port 301 receives input voltage VIN; Output port 310 provides output voltage V o to load RL; Transformer T1 has former limit winding L p and secondary winding L s, and its limit, Central Plains winding L p and secondary winding L s have respectively first end and the second end, and the first end of described former limit winding L p is coupled to input port 301 to receive input voltage VIN; Former limit power switch M has first end, and the second end and control end, wherein said first end are coupled to the second end of the former limit winding L p of transformer T1, and described the second termination is with reference to ground; Secondary power switch D is coupled between the first end and output port 310 of secondary winding L s of transformer; Secondary controller 202, have and be coupled to the power end VCC that described output port 310 receives output voltage V o, wherein said secondary controller 202 comprises: error amplifier 302, have first input end, the second input and output, wherein said first input end couples the feedback signal Vfb that characterizes output voltage V o, the second input receiver voltage reference signal Vref, based on the first feedback signal Vfb and voltage reference signal Vref, described error amplifier 302 is at output output error amplifying signal Vc; Error comparator 303, have first input end, the second input and output, the output that wherein said first input end is coupled to error amplifier 302 receives error amplification signal Vc, the second input couples modulation signal Vsw, based on error amplification signal Vc and modulation signal Vsw, described error comparator 303 is at output output the first comparison signal; The 4th switch 311, have first end, the second end and control end, the output that wherein said control end is coupled to error comparator 303 receives the first comparison signal, and described the second termination secondary is with reference to ground, based on the first comparison signal, described the 4th switch 311 is switched on or is turned off; Coupled apparatus, comprise input side 301-1 and outlet side 301-2, wherein input side 301-1 is coupled between the first end of output port 310 and the 4th switch 311, and described coupled apparatus is based on the signal at the 4th switch 311 two ends, and 301-2 provides frequency control signal Con at its outlet side; Former limit controller 201, described former limit controller 201 comprises: peak current generator 305 is coupled to the outlet side 301-2 receive frequency control signal Con of coupled apparatus, and based on frequency control signal Con, produces peak-current signal Vlim; Current comparator 307, have first input end, the second input and output, first input end received current detection signal Vcs wherein, the second input is coupled to peak current generator 305 and receives peak-current signal Vlim, the electric current of former limit power switch M is flow through in wherein said current detection signal Vcs reflection, based on described current detection signal Vcs and peak-current signal Vlim, described current comparator 307 is in output output current control signal; Logical circuit 306, have first input end, the second input and output, wherein said first input end is coupled to the outlet side 301-2 receive frequency control signal Con of coupled apparatus, described the second input is coupled to the output received current control signal of peak current comparator 307, based on described frequency control signal Con and described current controling signal, described logical circuit 306 is in its output output gate signal, to control conducting and the disconnection of former limit power switch M.
In the embodiment shown in fig. 7, described coupled apparatus comprises photoelectric coupled device.The input side 301-1 of described photoelectric coupled device comprises light-emitting diode, and its outlet side 301-2 comprises photistor.In one embodiment, the anode of described light-emitting diode is coupled to output port 310 to receive output voltage V o by resistance R 2; Negative electrode is coupled to the first end of the 4th switch 311.One termination former limit of described photistor is with reference to ground, the described frequency control signal Con of other end output.Wherein resistance R 2 is used for the voltage of the anode of adjusting light-emitting diode.If output voltage V o is within the tolerance range of light-emitting diode, resistance R 2 can be omitted.The operation principle of photoelectric coupled device is those of ordinary skills' common practise, and is simple and clear for narrating, and no longer elaborates herein.By reading this specification, those of ordinary skills should be understood that coupled apparatus can comprise any circuit that can realize the function that photoelectric coupled device as shown in Figure 7 is completed, such as hall device etc.
In one embodiment, switching power circuit 300 also comprises current sampling resistor Rcs, is coupled in the second end of former limit power switch M and former limit with reference between ground, so that current sampling signal to be provided.
In the embodiment shown in fig. 7, the set end S of described rest-set flip-flop is that trailing edge triggers.But the set end S that it will be appreciated by those of ordinary skill in the art that described rest-set flip-flop also can be for rising edge triggers, and can couple an inverter this moment before the set end S of rest-set flip-flop.
In one embodiment, the switching frequency f of the switching power circuit 300 that characterizes according to frequency control signal Con is at different frequency separations, described peak-current signal Vlim has different relations from frequency control signal Con: a). as switching frequency f greater than first frequency threshold value f1, peak-current signal Vlim along with switching frequency f reduce begin to reduce from peak current maximum Vlim_max; B). when switching frequency f was between first frequency threshold value f1 and second frequency threshold value f2, peak-current signal Vlim was fixed in peak current median Vlim_mid; C). when switching frequency f is between second frequency threshold value f2 and the 3rd frequency threshold f3, peak-current signal Vlim along with switching frequency f reduce begin to reduce from peak current median Vlim_mid; D). during less than the 3rd frequency threshold f3, peak-current signal Vlim is fixed in peak current minimum value Vlim_min when switching frequency; Wherein first frequency threshold value f1 is greater than second frequency threshold value f2, and second frequency threshold value f2 is greater than the 3rd frequency threshold f3.The switching frequency f that is peak-current signal Vlim and switching power circuit 300 has following functional relation:
Wherein k is coefficient, and when switching power circuit 300 was determined, k was fixed value.
In one embodiment, described secondary controller 202 also comprises modulation signal generator 304.The first end that described modulation signal generator 304 is coupled to secondary winding L s receives synchronizing signal SYN, and based on synchronizing signal, described modulation signal generator 304 output modulation signal Vsw.The function of described modulation signal generator 304 is: when secondary power tube D was closed conducting, synchronizing signal SYN was high, and modulation signal Vsw rises; When modulation signal Vsw rose to error amplification signal Vc, modulation signal Vsw became low level, waited for that when synchronizing signal SYN is high next time, modulation signal Vsw rises again.Modulation signal generator 304 is the common practise of this area, and is simple and clear for narrating, and no longer sets forth its physical circuit herein.
The generation of modulation signal Vsw must be based on synchronizing signal SYN.In one embodiment, described modulation signal Vsw has fixing low level time t in each switch periods, and through after this set time t, modulation signal Vsw begins to rise; When modulation signal Vsw rises to error signal Vc, become low level.Again pass through set time t, modulation signal Vsw rises.Above process is gone round and begun again.Described fixedly low level time can be according to the practical situations setting.
In one embodiment, logical circuit 106 comprises rest-set flip-flop, described rest-set flip-flop has set end S, reset terminal R and output Q, wherein said set end S is coupled to coupled apparatus output 301-2 receive frequency control signal, described reset terminal R couples the output received current comparison signal of current comparator 307, based on described frequency control signal Con and described electric current comparison signal, described rest-set flip-flop provides described gate signal at its output Q.
When switching power circuit 300 operation, modulation signal Vsw increases in each switch periods internal linear, and when it increased to error amplification signal Vc, the frequency control signal of error comparator 303 outputs became high level, makes the 4th switch 311 be closed conducting.Modulation signal Vsw becomes low level subsequently, and begins to increase after set time t.At output port 310 places, output voltage V o forms current path via input side 301-1 and the 4th switch 311 of resistance R 2, coupled apparatus.The outlet side 301-2 of coupled apparatus responds to the electric current that this flows through input side 301-1, makes frequency control signal Con become low level, thereby is high with the gate signal set of logical circuit 306 outputs.Correspondingly, former limit power switch M is switched on, and input signal forms current path via transformer primary side winding L p, former limit power switch M and current sampling resistor Rcs, and the electric current that flows through former limit power switch M begins to increase.Correspondingly, current sampling signal Vcs also begins to increase.When it increased to the peak-current signal Vlim that peak current generator 305 provides, the electric current comparison signal of current comparator 307 outputs became high level, thereby the gate signal of reseting logic circuit 306 outputs disconnects former limit power switch M.Until modulation signal Vsw reaches error amplification signal Vc again, the frequency control signal of error comparator 303 outputs becomes high level, thereby with the 4th closed conducting of switch 311, switching power circuit 300 enters next switch periods, and operation as mentioned above.
Fig. 8 shows the electrical block diagram according to the switching power circuit 400 of the utility model one embodiment.Switching power circuit 400 shown in Figure 8 is similar to switching power circuit 300 shown in Figure 7, compares with switching power circuit 300 shown in Figure 7, and switching power circuit 400 shown in Figure 8 further comprises: oscillator 308, and the output fixed frequency is the clock signal clk of fs_max; Select circuit 309, have first input end, the second input and output, wherein said first input end is coupled to the outlet side 301-2 receive frequency control signal Con of coupled apparatus, described the second input is coupled to oscillator 111 receive clock signal CLK, described selection circuit 109 is based on clock signal clk and frequency control signal Con, and the signal that frequency is less is delivered to logical circuit 306 first input ends as its output signal.
In Fig. 7 and embodiment shown in Figure 8, the secondary controller has been completed the function that generates the first comparison signal based on the feedback voltage that characterizes output voltage V o, coupled apparatus is based on the first comparison signal generated frequency control signal, and frequency control signal is coupled to former limit controller.In one embodiment, secondary controller and former limit controller can be integrated in same controller.In this case, coupled apparatus will characterize the described controller of feedback voltage coupling of output voltage V o.
Although described the utility model with reference to several exemplary embodiments, should be appreciated that term used is explanation and exemplary and nonrestrictive term.Because the utility model can specifically be implemented in a variety of forms and not break away from spirit or the essence of utility model, so be to be understood that, above-described embodiment is not limited to any aforesaid details, and should be in the spirit and scope that the claim of enclosing limits explain widely, therefore fall into whole variations in claim or its equivalent scope and remodeling and all should be the claim of enclosing and contain.
Claims (9)
1. a switching power circuit, is characterized in that, described switching power circuit comprises:
Input port couples input voltage;
Output port provides output voltage to load;
Be coupled in energy-storage travelling wave tube and power switch between input port and output port, wherein said power switch has control end;
Error amplifier has first input end, the second input and output, and wherein said first input end couples the feedback signal of reflection output voltage, described the second input receiver voltage reference signal, described output output error amplifying signal;
Error comparator has first input end, the second input and output, and the output that described first input end is coupled to error amplifier receives error amplification signal, and described the second input receives sawtooth signal, described output output frequency control signal;
The peak current generator has input and output, and described input is coupled to the output receive frequency control signal of error comparator, and described output produces peak-current signal;
The peak current comparator, have first input end, the second input and output, the output that described first input end is coupled to the peak current generator receives peak-current signal, described the second input receives the current detection signal that the electric current of energy-storage travelling wave tube is flow through in reflection, described output output peak current control signal;
Logical circuit, have first input end, the second input and output, wherein said first input end is coupled to the output receive frequency control signal of error comparator, the output that described the second input is coupled to the peak current comparator receives the peak current control signal, and described output output gate signal is to the control end of power switch.
2. switching power circuit as claimed in claim 1, is characterized in that, wherein said logical circuit comprises:
Oscillator, the clock signal of output fixed frequency;
Select circuit, have first input end, the second input and output, described first input end is coupled to oscillator receive clock signal, described the second input is coupled to the error comparator receiving frequency signals, described selection circuit is at frequency signal output frequency signal during less than clock signal, at frequency signal during more than or equal to clock signal, clock signal;
Rest-set flip-flop, have set end, reset terminal and output, wherein said set end is coupled to the output of selecting circuit, and the output that described reset terminal is coupled to the peak current comparator receives the peak current control signal, the described gate signal of described output output.
3. switching power circuit as claimed in claim 1, is characterized in that, wherein said peak current generator comprises:
The first switch has first end, the second end and control end, and described first end couples the maximum value level signal with the peaked magnitude of voltage of peak-current signal, and described control end couples frequency control signal;
The cycle timing unit has input and output, described input receive frequency control signal, described output output timing signal;
Second switch has first end, the second end and control end, and described first end is coupled to the second end of the first switch, and the output that described control end is coupled to the cycle timing unit receives timing signal;
The 3rd switch has first end and the second end, and described first end is coupled to the second end of second switch, and described the second end couples the minimal value level signal of the magnitude of voltage with peak-current signal minimum value;
The first electric capacity has first end and the second end, and described first end is coupled to the tie point of the first switch and second switch, and described the second termination is with reference to ground;
The first current source has first end and the second end, and described first end is coupled to the tie point of second switch and the 3rd switch, and described the second end is connected to reference to ground.
4. switching power circuit as claimed in claim 3, is characterized in that, wherein said cycle timing unit comprises:
The first timer, receive frequency control signal, output the first timing signal;
The second timer couples frequency control signal, output the second timing signal;
OR circuit has first input end, the second input and output, and the output that wherein said first input end is coupled to the second timer receives the second timing signal, described the second input receiving frequency signals;
Rest-set flip-flop has set end, reset terminal and output, and its set end is coupled to the first timer and receives the first timing signal, and its reset terminal couples the output of OR circuit, described output output timing signal.
5. switching power circuit, it is characterized in that, described switching power circuit comprises: transformer, former limit power switch, secondary power switch, former limit controller, secondary controller and coupled apparatus, described transformer comprises former limit winding, secondary winding and the tertiary winding, described former limit winding and former limit power switch couple, described secondary winding and secondary power switch couple, described coupled apparatus has input side and outlet side, described input side couples described secondary controller, described outlet side produces frequency control signal, described former limit controller provides the gate signal of the break-make of controlling former limit power switch, described former limit controller comprises:
The peak current generator has input and output, described input receive frequency control signal, and described output produces peak-current signal;
Current comparator, have first input end, the second input and output, wherein first input end receives the current detection signal that the electric current of former limit winding is flow through in reflection, the output that the second input is coupled to the peak current generator receives peak-current signal, described output output peak current control signal;
Logical circuit, have first input end, the second input and output, the output that wherein said first input end receive frequency control signal, described the second input are coupled to the peak current comparator receives the peak current control signal, described output output gate signal.
6. switching power circuit as claimed in claim 5, is characterized in that, wherein said logical circuit comprises:
Oscillator, the clock signal of output fixed frequency;
Select circuit, has first input end, the second input and output, described first input end is coupled to oscillator receive clock signal, described the second input is coupled to the error comparator receiving frequency signals, and described selection circuit is at frequency signal during less than clock signal, output frequency signal, at frequency signal during more than or equal to clock signal, clock signal;
Rest-set flip-flop, have set end, reset terminal and output, wherein said set end is coupled to the output of selecting circuit, and the output that described reset terminal is coupled to the peak current comparator receives the peak current control signal, the described gate signal of described output output.
7. switching power circuit as claimed in claim 5, is characterized in that, wherein said peak current generator comprises:
The first switch has first end, the second end and control end, and described first end couples the maximum value level signal with the peaked magnitude of voltage of peak-current signal, and described control end couples frequency control signal;
The cycle timing unit has input and output, described input receive frequency control signal, and based on frequency control signal, described output output timing signal;
Second switch has first end, the second end and control end, and described first end is coupled to the second end of the first switch, and the output that described control end is coupled to the cycle timing unit receives timing signal;
The 3rd switch has first end and the second end, and described first end is coupled to the second end of second switch, and described the second end couples the minimal value level signal of the magnitude of voltage with peak-current signal minimum value;
The first electric capacity has first end and the second end, and described first end is coupled to the tie point of the first switch and second switch, and described the second termination is with reference to ground;
The first current source has first end and the second end, and described first end is coupled to the tie point of second switch and the 3rd switch, and described the second end is connected to reference to ground.
8. switching power circuit as claimed in claim 7, is characterized in that, wherein said cycle timing unit comprises:
The first timer, the receive frequency control signal, and based on frequency control signal output the first timing signal;
The second timer couples frequency control signal, and based on frequency control signal output the second timing signal;
OR circuit has first input end, the second input and output, and the output that wherein said first input end is coupled to the second timer receives the second timing signal, described the second input receiving frequency signals;
Rest-set flip-flop, have set end, reset terminal and output, its set end is coupled to the first timer and receives the first timing signal, and its reset terminal couples the output of OR circuit, and described rest-set flip-flop is based on the output signal output timing signal of the first timing signal and OR circuit.
9. switching power circuit as claimed in claim 5, is characterized in that, wherein said secondary controller comprises:
Error amplifier has first input end, the second input and output, and wherein said first input end couples the feedback signal that characterizes output voltage, the second input receiver voltage reference signal, described output output error amplifying signal;
Error comparator has first input end, the second input and output, and the output that wherein said first input end is coupled to error amplifier receives error amplification signal, and the second input couples modulation signal, described output output the first comparison signal;
The 4th switch has first end, the second end and control end, and the output that wherein said control end is coupled to error comparator receives the first comparison signal, and described the second termination secondary is with reference to ground;
Wherein, the input side of described coupled apparatus is coupled between the first end of output port and the first switch.
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| CN 201220201921 CN202978703U (en) | 2012-05-08 | 2012-05-08 | Switching power supply circuit |
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| CN 201220201921 CN202978703U (en) | 2012-05-08 | 2012-05-08 | Switching power supply circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102664525A (en) * | 2012-05-08 | 2012-09-12 | 成都芯源系统有限公司 | Switching power supply circuit and control method thereof |
| CN105245098A (en) * | 2014-07-02 | 2016-01-13 | 南京博兰得电子科技有限公司 | Pulse frequency modulator for power supply converter and modulation method |
| CN108566126A (en) * | 2018-05-07 | 2018-09-21 | 深圳市振华微电子有限公司 | It is a kind of based on or door electric machine control system |
| TWI680635B (en) * | 2018-11-13 | 2019-12-21 | 大陸商昂寶電子（上海）有限公司 | Active frequency control switching power supply system |
| CN112104229A (en) * | 2020-09-25 | 2020-12-18 | 深圳南云微电子有限公司 | BUCK control circuit, control method and reference generation circuit |
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2012
- 2012-05-08 CN CN 201220201921 patent/CN202978703U/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102664525A (en) * | 2012-05-08 | 2012-09-12 | 成都芯源系统有限公司 | Switching power supply circuit and control method thereof |
| CN102664525B (en) * | 2012-05-08 | 2014-08-27 | 成都芯源系统有限公司 | Switching power supply circuit |
| CN105245098A (en) * | 2014-07-02 | 2016-01-13 | 南京博兰得电子科技有限公司 | Pulse frequency modulator for power supply converter and modulation method |
| CN105245098B (en) * | 2014-07-02 | 2019-02-12 | 南京博兰得电子科技有限公司 | Pulse frequency modulator and modulator approach for supply convertor |
| CN108566126A (en) * | 2018-05-07 | 2018-09-21 | 深圳市振华微电子有限公司 | It is a kind of based on or door electric machine control system |
| CN108566126B (en) * | 2018-05-07 | 2023-11-28 | 深圳市振华微电子有限公司 | Motor control system based on OR gate |
| TWI680635B (en) * | 2018-11-13 | 2019-12-21 | 大陸商昂寶電子（上海）有限公司 | Active frequency control switching power supply system |
| CN112104229A (en) * | 2020-09-25 | 2020-12-18 | 深圳南云微电子有限公司 | BUCK control circuit, control method and reference generation circuit |
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