CN202887164U - Signal synchronous output device of quad high-definition liquid crystal display (LCD) - Google Patents

Abstract

The utility model provides a signal synchronous output device of a quad high-definition liquid crystal display (LCD). The signal synchronous output device of the quad high-definition LCD aims at a non-synchronous phenomenon easy to generate when a dynamic image is rapid in change and displayed by a common quad high-definition LCD through four 1080 P signals composed into one 3840*2160 signal. The signal synchronous output device of the quad high-definition LCD comprises a four-way high-definition multimedia interface (HDMI)/ digital video interactive (DVI) signal (1) which is output by a computer and is connected with four independent field programmable gate array (FPGA) chips. One of the FPGA chips is used as a main control FPGA chip (2) which is connected with the other three FPGA chips (3). The signal synchronous output device of the quad high-definition LCD is used for signal synchronous output of the LCD.

Description

Four times of high definition LCD display signal synchronous output devices

Technical field

The utility model relates to a kind of four times of high definition LCD display signal synchronous output devices, belongs to the video technique field.

Background technology

The LCD liquid crystal display is the abbreviation of Liquid Crystal Display, the structure of LCD is to place liquid crystal in the middle of two parallel glass, the tiny electric wire that many vertical and levels are arranged in the middle of two sheet glass, whether seeing through switches on controls shaft-like quartzy molecular changes direction, and light refraction is out produced picture.The advantage of LCD: the little power consumption of low pressure; Flat structure; Passive display type, free from glare does not stimulate human eye, can not cause eye fatigue; Demonstration contains much information; Be easy to colorize, on chromatogram, can reappear very accurately; Electromagnetic-radiation-free to human-body safety, is beneficial to information privacy; Long-life.Therefore become gradually the market mainstream, various forms of LCD display also emerge in an endless stream.Present four times of high definitions (3840x2160@60Hz) LCD display is progressively received by market with its high resolving power, but no matter four times of present high definitions (3840x2160@60Hz) LCD display is from products such as wire rod or computer players, all can't support single HDMI(High-Definition Multimedia Interface, HDMI)/and DVI(Digital Visual Interface, i.e. digital visual interface) the so high resolution of interface output 3840x2160@60Hz.General way is to adopt 4 DVI/HDMI interfaces at present, and each interface output 1920x1080@60Hz signal is by the synthetic 3840x2160 image in different resolution of 4 1080P.

Synthesizing a this mode of 3840x2160 signal by 4 1080P signals is no problem when showing still image, but showing dynamic image, picture changes when comparing faster, just become a problem synchronously between 4 pictures, if bad synchronously, between 4 1080P pictures, just produce easily nonsynchronous phenomenon.

Summary of the invention

The purpose of this utility model is that the problem for above-mentioned existence provides a kind of four times of high definition LCD display signal synchronous output devices, can carry out synchronously to guarantee 4 road HDMI/DVI output, not can because of be 4 different signal sources and produce asynchronously, the nonsynchronous phenomenon of picture appears.

Above-mentioned purpose is achieved through the following technical solutions:

Four times of high definition LCD display signal synchronous output devices, four road HDMI/DVI signals that comprise computer export, described four road HDMI/DVI signals connect four independently fpga chips, one of them described fpga chip is as the master control fpga chip, and described master control fpga chip connects other three fpga chips.

Beneficial effect:

The utility model adopts four road HDMI/DVI signals to process by four independent FPGA, one of them FPGA is as main control chip, this FPGA produces field sync signal according to the HDMI/DVI signal of coming in and exports to other three FPGA, other three FPGA normally carry out data buffer storage, according to the such technical scheme of synchronizing signal output signal with four road HDMI/DVI signal buffer memorys, when field sync signal is arrived, buffer memory four road HDMI/DVI signals are exported simultaneously, can carry out synchronously to guarantee four road HDMI/DVI output, not can because of be four different signal sources and produce asynchronously, the nonsynchronous phenomenon of picture appears.The utility model is four road independent signals, be divided into 1 main 3 from, and from main signal output field synchronizing signal, it is synchronous to guarantee that four times of high definitions show.

Description of drawings

Fig. 1, structural representation of the present utility model.

Embodiment

Below in conjunction with the drawings and specific embodiments, further illustrate the utility model.

Embodiment 1:

As shown in Figure 1: four times of high definition LCD display signal synchronous output devices of the present utility model, four road HDMI/DVI signals 1 that comprise computer export, described four road HDMI/DVI signals connect four independently fpga chips, one of them described fpga chip is as master control fpga chip 2, and described master control fpga chip connects other three fpga chips 3.

The course of work:

Computing machine vision signal out send field sync signal to other 3 fpga chips through main fpga chip by main fpga chip, and other 3 fpga chips normally carry out data buffer storage, and after synchronously, 4 road 1080P signals are synthesized the 3840x2160 output signal.

Claims (1)

1. one kind four times high definition LCD display signal synchronous output devices, four road HDMI/DVI signals that comprise computer export, it is characterized in that: described four road HDMI/DVI signals connect four independently fpga chips, one of them described fpga chip is as the master control fpga chip, and described master control fpga chip connects other three fpga chips.

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