CN201947268U - Testing device for QSFP (quad small form-factor pluggable) module - Google Patents
Testing device for QSFP (quad small form-factor pluggable) module Download PDFInfo
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- CN201947268U CN201947268U CN201120019663XU CN201120019663U CN201947268U CN 201947268 U CN201947268 U CN 201947268U CN 201120019663X U CN201120019663X U CN 201120019663XU CN 201120019663 U CN201120019663 U CN 201120019663U CN 201947268 U CN201947268 U CN 201947268U
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Abstract
The utility model relates to the technical field of micro-electronic devices and discloses a testing device for QSFP (quad small form-factor pluggable) module, which comprises a signal source, a transmitting terminal circuit, a computer, a receiving end circuit, a QSFP connector, a first connector, a second connector and a signal analysis device. The signal source, the signal analysis device, the transmitting terminal circuit and the receiving end circuit are connected with the computer respectively. The signal source is connected with the transmitting terminal circuit through the first connector, the transmitting terminal circuit is connected with the receiving end circuit through the QSFP connector, and the receiving end circuit is connected with the signal analysis device through the second connector, thereby realizing a simultaneous test for multi-channels and multi-modules.
Description
Technical field
The utility model relates to technical field of microelectronic devices, relates in particular to a kind of QSFP(four-way pluggable optical module: testing apparatus Quad Small Form-factor Pluggable).
Background technology
Optical communication system is compared with electrical communication system, have that bandwidth is big, loss is low, do not allow to be subject to electromagnetic interference, weight light, be difficult for by advantages such as eavesdroppings.Increase day by day along with bandwidth demand, in long distance of high speed or high-speed parallel short range communication systems, optical fiber has become the desirable alternative of coaxial cable, optical module provides every passage 155Mbps hot-swappable scheme to the 25Gbps data rate, parallel optical module always transmits data can have vast market prospect up to 120Gbps.
But in the prior art, shortcoming such as the testing apparatus majority that the parameter testing of QSFP module is used is taked the modularization assembling, has the cost costliness, and function is single-minded needs a plurality of testing apparatuss when implementing concurrent testing, and the cost of testing apparatus is very high; And in the system testing process, be isolated mutually between the various testing apparatuss, testing efficiency is lower.In actual production, need to reduce the cost of test and improve the efficient of test, can enhance productivity on the one hand, the reflection module that helps science more on the other hand is the performance under the operating state simultaneously, makes test result more accurate.Owing to the test module that an instrument can assemble is limited, and test module costs an arm and a leg, the method that arbitrarily the increases testing apparatus wasting manpower and material resources that seems, utilizing FPGA(Field-Programmable Gate Array: i.e. field programmable gate array) chip tests, it is the solution of more employing in the prior art, but in high-frequency test, the FPGA design cycle is longer, and design difficulty is bigger.
The utility model content
Therefore testing apparatus at the QSFP module that exists in the prior art costs an arm and a leg, and the technical problem that testing efficiency is not high is necessary to provide a kind of testing apparatus of QSFP module.
The utility model provides a kind of testing apparatus of QSFP module, comprises signal source, transmitting terminal circuit, computer, receiving terminal circuit, QSFP connector, first connector, second connector and signal analysis instrument; Described signal source, signal analysis instrument, transmitting terminal circuit, receiving terminal circuit are connected with computer respectively, described signal source is connected with the transmitting terminal circuit by first connector, described transmitting terminal circuit is connected with receiving terminal circuit by the QSFP connector, and described receiving terminal circuit is connected with the signal analysis instrument by second connector.
Preferably, the generator of described signal source is an Error Detector.
Preferably, described signal analysis instrument is an oscilloscope.
Preferably, described transmitting terminal circuit comprises cross chips and single-chip microcomputer, and described cross chips is connected with computer by single-chip microcomputer.
Preferably, described receiving terminal circuit comprises cross chips and single-chip microcomputer, and described cross chips is connected with computer by single-chip microcomputer.
The beneficial effects of the utility model are: test when realizing the multichannel multimode.This testing apparatus has improved testing efficiency, saves cost.Shortened the research and development test period of product, reduced R﹠D costs, the automation of simplifying test process and realizing test process.
Description of drawings
Fig. 1 is the principle schematic of the checkout gear of QSFP module.
Fig. 2 is the cross bar switch control principle figure of the checkout gear of QSFP module.
Fig. 3 is the schematic diagram that utilizes oscilloscope test module channel signal quality.
Fig. 4 is the schematic diagram that utilizes oscilloscope and Error Detector test signal of the checkout gear of QSFP module.
The structure chart that Fig. 5 tests simultaneously for a plurality of QSFP modules.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearer,, and, the utility model is further described with reference to accompanying drawing below in conjunction with specific embodiment.
The principle schematic of the checkout gear of QSFP module as shown in Figure 1, the checkout gear of described QSFP module comprises cross chips, cross bar switch 101 is set in the described cross chips, described cross bar switch 101 has the high speed input signal in N road (A) [N-1,0]), N road high speed output signal (Y [N-1,0]), high speed input signal (A) [N-1,0]) realizes intersection output by 101 controls of the cross bar switch in the cross chips.
The cross bar switch control principle figure of the checkout gear of QSFP module as shown in Figure 2, the checkout gear of described QSFP module also further comprises: computer 201, single-chip microcomputer 202, connector 203.Described cross chips is connected with connector 203, and described cross chips is connected with computer 201 by single-chip microcomputer 202.The high speed signal of cross chips output is sent to connector 203, as the module input signal.The address of single-chip microcomputer 202 input cross bar switches 101, the configuration output channel realizes the selection of output channel.
The schematic diagram that utilizes oscilloscope test module channel signal quality as shown in Figure 3, the checkout gear of described QSFP module also further comprises signal generator 301, QSFP test module 302, analytical instrument such as oscilloscope 303, circuit board 304.Described signal generator 301 is connected with cross chips, computer 202 respectively; Described QSFP test module 302 is connected with connector 203, oscilloscope 303 respectively; Described oscilloscope 303 is connected with computer 202.The whole forming circuit plate 304 of described cross chips and single-chip microcomputer and corresponding interface thereof.The signal of signal generator 301 emissions is input in the cross bar switch 101, realizes signal output selection by control cross bar switch 301, and the port number of output is according to the quantity and the test parameter decision of the QSFP test module 302 of test.The high speed signal of output is connected to the connector 203 of QSFP test module 302, and as the input signal of QSFP test module 302, the output signal of QSFP test module 302 is connected to oscilloscope 303, and the details of observation signal is judged quality of signals.
The schematic diagram of oscilloscope as shown in Figure 4 and Error Detector test signal, in the checkout gear of described QSFP module, signal generator 301 is preferably Error Detector, the signal of described Error Detector 401 emissions is input in the transmitting terminal cross bar switch 101, realize signal output selection by control transmitting terminal cross bar switch 101, the port number of output is according to the module number and the parameter decision of test.The output high speed signal is connected to the connector of QSFP test module 302, as the input signal of QSFP test module 302, the output signal one tunnel of QSFP test module 302 is connected to analytical instrument, on oscilloscope 303, the details of observation signal is judged quality of signals; Another road of QSFP test module 302 is connected on the Error Detector 401, is used to observe the error rate.Simultaneously computer 201 and analytical instrument (as oscilloscope 409) and Error Detector 401 are connected by the communications cable, and computer 201 can read the test data of oscilloscope 409 and Error Detector 401 at any time and control tester.Wherein, form radiating circuit plate 402 according to not same cross chips of purposes and single-chip microcomputer, another one cross chips and single-chip microcomputer form circuit board for receiving 403.
Topmost beneficial effect of the present utility model comprises can realize simultaneously that a plurality of QSFP test modules test the structure chart that a plurality of QSFP modules are as shown in Figure 5 tested simultaneously simultaneously.Described testing apparatus comprises signal source, transmitting terminal circuit, computer, receiving terminal circuit, QSFP connector, first connector, second connector and signal analysis instrument.Described signal source, signal analysis instrument, transmitting terminal circuit, receiving terminal circuit are connected with computer respectively, described signal source is connected with the transmitting terminal circuit by first connector, described transmitting terminal circuit is connected with receiving terminal circuit by the QSFP connector, and described receiving terminal circuit is connected with the signal analysis instrument by second connector.
Preferably, the generator of described signal source is the Error Detector described in Fig. 4, and described Error Detector is connected with computer, and computer can read the test data of Error Detector at any time.
Preferably, described signal analysis instrument is an oscilloscope, and that oscilloscope utilizes is narrow, by the electron beam that high-velocity electrons are formed, and beats scribbling on the panel of fluorescent material, produces tiny luminous point.
Preferably, described transmitting terminal circuit comprises cross chips and single-chip microcomputer, and as shown in Figure 3, described cross chips is connected with computer by single-chip microcomputer.
Preferably, described receiving terminal circuit comprises cross chips and single-chip microcomputer, and as shown in Figure 3, described cross chips is connected with computer by single-chip microcomputer.
Can use the VSC3316 chip as the cross bar switch chip, have the input channel of 16 road 10Gbps, the output channel of 16 road 10Gbps.The active optical fiber cables module of QSFP has 4 10Gbps transmission channels and 4 10Gbps receive paths as the module of transceiver.So the test macro that uses the VSC3316 chip to build as the basis can be tested 4 active cable modules of QSFP simultaneously.Can realize the test of a lot of parameters, after hardware circuit board designs, finish one and be enclosed within the Control Software of moving on the computer, realize the automation of whole debugging test process.Automatically switch with switch chip on the PC control board comprising realizing, test automatically, finish data acquisition, handle storage etc. with PC with PC control oscilloscope and Error Detector.Several partial functions below the specific implementation:
Optical module optimized parameter debug function:
Use PC by the register input BC of I2C bus in optical module, MC, MPC, tuning parameters such as PE read oscillographic DDJ by transferring survey software, and jitter values such as RJ adopt algorithm to obtain optimum DDJ, the RJ equivalence, thus obtain best parameter.
The whole brake of optical module:
Automatically test with PC control oscilloscope, and gather following data: electricity mouthful amplitude, sensitivity, the rising edge time, the trailing edge time, shake, all side's shakes, peak-to-peak jitter, template is applied mechanically etc.The real time data of oscilloscope collection and the value of database prescribed limit are compared, judge module whether by test.Deposit the test result of each optical module in the SQL database a record.
Calibration and calibration testing:
Because in test process, software can will transfer the final result of surveying to record in the database of big PC, and calibration and calibration testing are exactly to extract the luminous power of making a start of depositing wherein, the receiving end luminous power, bias current, temperature, voltage re-uses highly sensitive instrument and calibrates.
Inspection EEPROM:
A0, product essential information and basic parameter
A2, the parameter of real-time change.
Above-described specific embodiment; the purpose of this utility model, technical scheme and beneficial effect are further described; institute is understood that; the above only is a specific embodiment of the utility model; be not limited to the utility model; all within spirit of the present utility model and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within the protection range of the present utility model.
Claims (5)
1. the testing apparatus of a QSFP module is characterized in that comprising signal source, transmitting terminal circuit, computer, receiving terminal circuit, QSFP connector, first connector, second connector and signal analysis instrument; Described signal source, signal analysis instrument, transmitting terminal circuit, receiving terminal circuit are connected with computer respectively, described signal source is connected with the transmitting terminal circuit by first connector, described transmitting terminal circuit is connected with receiving terminal circuit by the QSFP connector, and described receiving terminal circuit is connected with the signal analysis instrument by second connector.
2. testing apparatus as claimed in claim 1, the generator that it is characterized in that described signal source is an Error Detector.
3. testing apparatus as claimed in claim 2 is characterized in that described signal analysis instrument is an oscilloscope.
4. testing apparatus as claimed in claim 3 is characterized in that described transmitting terminal circuit comprises cross chips and single-chip microcomputer, and described cross chips is connected with computer by single-chip microcomputer.
5. testing apparatus as claimed in claim 4 is characterized in that described receiving terminal circuit comprises cross chips and single-chip microcomputer, and described cross chips is connected with computer by single-chip microcomputer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201120019663XU CN201947268U (en) | 2011-01-21 | 2011-01-21 | Testing device for QSFP (quad small form-factor pluggable) module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201120019663XU CN201947268U (en) | 2011-01-21 | 2011-01-21 | Testing device for QSFP (quad small form-factor pluggable) module |
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| CN201947268U true CN201947268U (en) | 2011-08-24 |
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| CN201120019663XU Expired - Fee Related CN201947268U (en) | 2011-01-21 | 2011-01-21 | Testing device for QSFP (quad small form-factor pluggable) module |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102819477A (en) * | 2012-08-28 | 2012-12-12 | 曙光信息产业(北京)有限公司 | Board fault test method and fault test card |
| CN103200044A (en) * | 2013-03-20 | 2013-07-10 | 烽火通信科技股份有限公司 | Backplane test system and method for verifying quality of 100G backplane interconnected signals |
| CN106301549A (en) * | 2016-09-30 | 2017-01-04 | 成都新易盛通信技术股份有限公司 | A kind of 100G loopback module based on QSFP28 encapsulation |
-
2011
- 2011-01-21 CN CN201120019663XU patent/CN201947268U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102819477A (en) * | 2012-08-28 | 2012-12-12 | 曙光信息产业(北京)有限公司 | Board fault test method and fault test card |
| CN102819477B (en) * | 2012-08-28 | 2015-07-29 | 曙光信息产业(北京)有限公司 | A kind of fault testing method of board and fault test card |
| CN103200044A (en) * | 2013-03-20 | 2013-07-10 | 烽火通信科技股份有限公司 | Backplane test system and method for verifying quality of 100G backplane interconnected signals |
| CN103200044B (en) * | 2013-03-20 | 2016-05-25 | 烽火通信科技股份有限公司 | Rear-panel testing system |
| CN106301549A (en) * | 2016-09-30 | 2017-01-04 | 成都新易盛通信技术股份有限公司 | A kind of 100G loopback module based on QSFP28 encapsulation |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110824 Termination date: 20180121 |
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| CF01 | Termination of patent right due to non-payment of annual fee |